JP2830954B2 - Television signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal processing apparatus, for example, an apparatus for displaying a television signal having an aspect ratio of 4: 3 on a display apparatus for a television signal having an aspect ratio of 16: 9. It can be applied to

[0002]

2. Description of the Related Art For example, when a television signal conforming to the NTSC system is to be displayed on a high-vision television receiver, it is necessary to convert the television signal conforming to the NTSC system into a format conforming to the Hi-Vision signal. There are a non-compression conversion method and a compression conversion method as a method (conversion method from the aspect ratio).

In the non-compression conversion method, a television signal (FIG. 2A) conforming to the NTSC system is double-speed-converted.
The aspect ratio of 4: 3 is maintained, and as shown in FIG. 2 (B), the display area is partly set in the vertical direction, so that it can be displayed on a high-definition television receiver having an aspect ratio of 16: 9. It was made. As shown in FIG. 3, if the description of the synchronization control method is omitted in the vertical direction and the horizontal direction, as shown in FIG. 3, for example, 14.3 is applied to the system conversion circuit 1 centering on two line memories.
Write with a write clock signal WCK of MHz,
Read clock signal RCK of 28.6 MHz which is twice this value
This is done by reading out the data.

On the other hand, the compression conversion method is conceptually based on NT.
The TV signal (FIG. 4A) conforming to the SC system is converted into the signal shown in FIG. 4 while considering the difference between the aspect ratios of 4: 3 and 16: 9.
As shown in FIG. 4 (B), the image is compressed in the horizontal direction, and is double-speed-converted, and as shown in FIG. An image having an aspect ratio of 4: 3 can be displayed on a screen. As shown in FIG. 5, such a signal conversion is performed, for example, at 14.3 MHz with respect to the method conversion circuit 2 centering on two line memories, if the description of the synchronization control method is omitted in the vertical and horizontal directions. Writing is performed by the write clock signal WCK, which is 2.66 times that of about 38.2.
This is performed by performing reading with a read clock signal RCK of MHz. Note that 2.66 times is 2 times related to double speed conversion.
It is the product of the doubling and 1.33 times related to the compression processing.

[0005] The non-compression conversion method has an advantage that an image can be displayed on the entire display screen, but has a disadvantage that only a part of an input image can be displayed. On the other hand, the compression conversion method also has an advantage that the entire input image can be displayed, but a part of the display screen (other than the display area).
Has the disadvantage of becoming black.

[0006] Therefore, a high-definition television receiver has been proposed, in which either the display by the non-compression conversion method or the display by the compression conversion method is possible, and the display is left to the user. In the case of such a high-definition television receiver, a clock signal or the like to be applied to a format conversion circuit can be varied, and other configurations are almost commonly used.

[0007]

As described above, in the conventional high-definition television receiver using both the non-compression conversion method and the compression conversion method, except for the structure for switching the clock frequency and the like applied to the method conversion circuit. Other configurations are commonly used, and a low-pass filter circuit for passing such a converted signal after converting it into an analog signal is also commonly used.

If the cut-off frequency of the low-pass filter circuit is selected in consideration of the non-compression conversion method, the information of the television signal processed and converted according to the compression conversion method will be lost. On the other hand, if the cut-off frequency of the low-pass filter circuit is selected in consideration of the compression conversion method, when a television signal processed according to the non-compression conversion method is converted to an analog signal, aliasing distortion occurs and interference on the screen occurs. There is a problem that arises.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is an uncompressed conversion for converting a television signal having a certain aspect ratio into a television signal having a relatively larger horizontal ratio. A television signal processing apparatus which selectively adopts a system and a compression conversion system, and converts a system-converted signal into an analog signal and does not cause image quality deterioration due to information loss and aliasing distortion even through a low-pass filter circuit. It is intended to provide.

[0010]

According to the present invention, a television signal having a certain aspect ratio is converted into a television signal having a relatively large horizontal ratio in a digital signal stage. Digital / analog conversion means for converting a television signal whose format has been converted into an analog signal in a television signal processing device which selectively employs a non-compression conversion method and a compression conversion method as the conversion method. A first low-pass filter means for filtering the analog signal when the non-compression conversion method is used, and a cut-off frequency lower than the first low-pass filter means for filtering the analog signal when the compression conversion method is used. High second low-pass filter means.

[0011]

When an attempt is made to display a television signal having a certain aspect ratio on a display device for a television signal having a relatively large ratio in the horizontal direction, it is necessary to perform format conversion. There are a non-compression conversion method and a compression conversion method. The present invention relates to a television signal processing device that can selectively employ these conversion methods.

In the case of such a television signal processing apparatus, the system is converted at the stage of a digital signal. Therefore, it is necessary to convert the digital signal into an analog signal by a digital / analog converter and then to pass the analog signal through a low-pass filter. is there. Here, the present invention provides a first low-pass filter means for the non-compression conversion method and a second low-pass filter means for the compression conversion method separately. It was decided to select according to.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a high-definition television receiver will be described in detail with reference to FIG.

A luminance signal Y according to the NTSC system separated by a Y / C separation circuit having a digital configuration (not shown) is
It is provided to the luminance signal type conversion circuit 10. The luminance signal format conversion circuit 10 has two line memories 10a and 10b, and for example, 14.3 MHz write clock signals WCKY and WCKY * (* indicate inverted signals) given from the clock generation circuit 11. )On the basis of,
The input luminance signal Y is stored in the line memory 10a or 10b.
To be stored. A clock generation circuit 11 is also generated in the luminance signal type conversion circuit 10, and a switching circuit 12
Is supplied, and the format conversion circuit for luminance signal 10 outputs the line memory 10a or 1 based on the read clock signal RCKY.
0b is read. The clock generation circuit 11
28.6 MHZ clock signal RC for uncompressed conversion
KY1 is generated, and 38.
The switch circuit 12 generates a 2 MHz clock signal RCKY2, and the switch circuit 12 selects one of the clock signals according to the compression / non-compression control signal CON from the compression / non-compression switching circuit 13 to convert the luminance signal format. To the circuit 10.

Although not shown, a memory control signal such as a write address signal is also supplied to the luminance signal type converter 10, and the input luminance signal Y is alternately written to the line memories 10a and 10b, and , From the line memory 10b or 10a that is not subjected to the write operation.

That is, when the non-compression conversion system clock signal RCKY1 is supplied, the luminance signal system conversion circuit 10 performs double-speed conversion (a double-speed scan line which is not used for display as shown in FIG. 2). (The number of scanning lines is not doubled because no portion is output), and when the compression conversion system clock signal RCK2 is supplied, the luminance signal system conversion circuit 10 performs the so-called double speed conversion of the scanning lines and the horizontal direction conversion. Compression processing is performed in combination.

The luminance signal Y1 thus converted is applied to a digital / analog conversion circuit 14. The digital / analog conversion circuit 14 receives the above-described clock signal R via a switch circuit 15 as a clock signal.
Either CKY1 or RCKY2 is provided. The switch circuit 15 is also supplied with a compression / non-compression control signal CON from the compression / non-compression switching circuit 13, and the switch circuit 15 performs a switching operation in conjunction with the above-described switch circuit 12. Thus, when the luminance signal format conversion circuit 10 performs conversion according to the non-compression conversion method, the digital / analog conversion circuit 14 outputs the clock signal RCKY1.
Is supplied to the first and second low-pass filter circuits 16 and 17 by performing a digital / analog conversion based on the luminance signal Y2 and converting the luminance signal Y2 into an analog signal. On the other hand, when the luminance signal format conversion circuit 10 performs conversion according to the compression conversion method, the digital / analog conversion circuit 14 performs digital / analog conversion based on the clock signal RCKY1 and converts the converted brightness signal into an analog signal. Y2 is supplied to the first and second low-pass filter circuits 16 and 17.

The first low-pass filter circuit 16 is for the non-compression conversion system, and has a cut-off frequency of, for example, 12 MHz, which is lower than that of the second low-pass filter circuit 17. This first low-pass filter circuit 16
Is supplied to a switch circuit 18 having a two-input one-output configuration. On the other hand, the second low-pass filter circuit 17 is for a compression conversion system, and has a cutoff frequency of, for example, 16 MHz higher than that of the first low-pass filter circuit 16. The luminance signal Y4 that has passed through the second low-pass filter circuit 17 is also supplied to the switch circuit 18. The compression / non-compression control signal CON from the compression / non-compression switching circuit 13 is also supplied to the switch circuit 18, and the switch circuit 18 performs a switching operation in conjunction with the switch circuit 12 described above. Thus, the switch circuit 18 selects the luminance signal Y3 that has passed through the first low-pass filter circuit 16 when the luminance signal format conversion circuit 10 performs conversion according to the non-compression conversion method,
When the luminance signal format conversion circuit 10 performs conversion according to the compression conversion method, the second low-pass filter circuit 1
7 is selected and the output luminance signal YO is selected.
UT.

It is also possible to use one variable low-pass filter circuit by switching between non-compression conversion and compression conversion (although in other embodiments), the cut-off frequency can be varied by as much as 4 MHz. It is difficult to obtain a low-pass filter circuit which can be used as described above, and it is practical to provide a separate and select the output as in this embodiment.

The chroma signal C according to the NTSC system separated by a Y / C separation circuit having a digital configuration (not shown) is supplied to a chroma signal system conversion circuit 20.
The chroma signal format conversion circuit 20 has two line memories 20a and 20b. Based on, for example, 14.3 MHz write clock signals WCKC and WCKC * supplied from the clock generation circuit 11, The signal C is stored in the line memory 20a or 20b.
The chroma signal conversion circuit 20 is also supplied with a read clock signal RCKC generated by the clock generation circuit 11 and selected by the switch circuit 12, and the chroma signal conversion circuit 20 receives the read clock signal RCK.
Reading from the line memory 20a or 20b is performed based on the KC. The clock generation circuit 11 generates a clock signal RCKC1 of 28.6 MHZ for the non-compression conversion method, and generates a clock signal RCKC2 of 38.2 MHz for the compression conversion method. One of the clock signals is selected according to the compression / non-compression control signal CON from the compression / non-compression switching circuit 13 and supplied to the system conversion circuit 20.

Although not shown, a memory control signal such as a write address signal is also supplied to the chroma signal format conversion circuit 20, and the input chroma signal C is alternately written to the line memories 20a and 20b. , From the line memory 20b or 20a not used for the write operation.

That is, when the non-compression conversion system clock signal RCKC1 is given, the chroma signal system conversion circuit 20 performs double speed conversion, and when the compression conversion system clock signal RCKC2 is provided, the chroma conversion system The signal format conversion circuit 20 combines the so-called double speed conversion of the scanning line and the compression process in the horizontal direction.

The chroma signal C1 thus converted is
It is provided to two digital / analog conversion circuits 22 and 23.

The digital / analog conversion circuit 22 is supplied with either a clock signal DAC1 or DAC2 generated by the clock generation circuit 11 as a clock signal. The switching circuit 24 also has a compression / non-compression switching circuit 13.
And a compression / non-compression control signal CON from
The switch circuit 24 performs a switching operation in conjunction with the switch circuit 21 described above. Thus, when the chroma signal format conversion circuit 20 is performing conversion according to the non-compression conversion method, the digital / analog conversion circuit 22 performs digital / analog conversion based on the clock signal DAC1, and performs the chroma signal format conversion circuit 20. Is performing conversion according to the compression conversion method, the digital / analog conversion circuit 22 performs digital / analog conversion based on the clock signal DAC2. Here, the writing is performed by the write clock signals WCKC and WCKC * synchronized with the input chroma signal C, and is read. When the read clock signal RCKC is selected as described above, the chroma signal CCK is obtained.
Means that the digital / analog conversion is performed at the timing of the red difference signal component RY. Thus,
The digital / analog conversion circuit 22 outputs a red color difference signal RY converted to an analog signal.
And the fourth low-pass filter circuits 25 and 26.

The third low-pass filter circuit 25 is for the non-compression conversion system, and has a cut-off frequency of 2.3 MHz lower than that of the fourth low-pass filter circuit 26, for example.
Has been selected. This third low-pass filter circuit 2
The red color difference signal RY1 that has passed through 5 is supplied to a switch circuit 27 having a two-input one-output configuration. On the other hand, the fourth low-pass filter circuit 26 is for a compression conversion system, and for example, has a cut-off frequency of the third low-pass filter circuit 2.
3.1 MHz, which is higher than 5, is selected. The red difference signal RY passed through the fourth low-pass filter circuit 26
2 is also supplied to the switch circuit 27. Switch circuit 27
The compression / non-compression control signal CON from the compression / non-compression switching circuit 13 is also supplied to the switch circuit 27.
Performs a switching operation in conjunction with the switch circuit 21 described above.
Thus, the switch circuit 27 selects the red color difference signal RY1 that has passed through the third low-pass filter circuit 25 when the chroma signal format conversion circuit 20 is performing conversion according to the non-compression conversion format, and Signal format conversion circuit 2
0 is performing the conversion according to the compression conversion method, the red difference signal R that has passed through the fourth low-pass filter circuit 26
-Y2 is selected as the output red color difference signal R-YOUT.

The digital / analog conversion circuit 23 to which the chroma signal C1 is supplied has a clock signal DAC
One of a clock signal DAC1 *, which is obtained by inverting 1 through an inverter circuit 28, and a clock signal DAC2 *, which is obtained by inverting a clock signal DAC2 through an inverter circuit 29, is provided through a switch circuit 30. The switch circuit 30 is also supplied with a compression / non-compression control signal CON from the compression / non-compression switching circuit 13, and the switch circuit 30 performs a switching operation in conjunction with the above-described switch circuit 21. Thus, when the chroma signal format conversion circuit 20 is performing conversion according to the non-compression conversion method, the digital / analog conversion circuit 23 performs digital / analog conversion based on the clock signal DAC1 *, and converts the chroma signal format conversion circuit. When the conversion is performed according to the compression conversion method, the digital / analog conversion circuit 23 performs digital / analog conversion based on the clock signal DAC2 *. Here, since the clock signal given to the digital / analog conversion circuit 23 is an inverted signal of the clock signal given to the digital / analog conversion circuit 22, the digital / analog conversion signal is generated at the timing of the blue difference signal component BY in the chroma signal C. This means that analog conversion is being performed. Thus, the digital / analog conversion circuit 23 outputs the blue difference signal BY converted into an analog signal, which is supplied to the fifth and sixth low-pass filter circuits 25 and 26.

The fifth low-pass filter circuit 31 is for the non-compression conversion system. For example, the cut-off frequency is 2.3 MHz, which is lower than that of the sixth low-pass filter circuit 32.
Has been selected. This fifth low-pass filter circuit 3
The blue difference signal BY1 passing through 1 is supplied to a switch circuit 33 having a two-input one-output configuration. On the other hand, the sixth low-pass filter circuit 32 is for a compression conversion method, and for example, has a cut-off frequency of the fifth low-pass filter circuit 3.
3.1 MHz, which is higher than 1, is selected. The blue difference signal BY that has passed through the sixth low-pass filter circuit 32
2 is also supplied to the switch circuit 33. Switch circuit 33
The compression / non-compression control signal CON from the compression / non-compression switching circuit 13 is also supplied to the switch circuit 33.
Performs a switching operation in conjunction with the switch circuit 21 described above.
Thus, the switch circuit 33 selects the blue difference signal BY1 that has passed through the fifth low-pass filter circuit 31 when the chroma signal format conversion circuit 20 is performing conversion according to the non-compression conversion format, and Signal format conversion circuit 2
0 indicates that the blue difference signal B that has passed through the sixth low-pass
-Y2 is selected as the output blue difference signal B-YOUT.

According to the above-described embodiment, the low-pass filter circuits 16, 25, and 31 having a low cut-off frequency are passed when the non-compression conversion method is used, and the cut-off frequency is used when the compression conversion method is used. Is passed through the low-pass filter circuits 17, 26, and 32, so that a signal converted by the compression conversion method is converted into an analog signal and no information is lost even through the low-pass filter circuit. By converting the signal converted by the non-compression conversion method into an analog signal, it is possible to realize a television receiver in which image quality does not deteriorate due to aliasing distortion even through a low-pass filter circuit.

Although the above embodiment has been described as applied to a high-definition television receiver, the present invention can be applied to other television signal processing devices such as a video tape recorder having a format converter. .

The present invention can also be applied to an apparatus that performs the system conversion processing at the stage of three primary color signals or at the stage of a composite video signal.

[0031]

As described above, according to the present invention, even if a signal converted by the compression conversion method is converted into an analog signal and the signal is passed through the low-pass filter circuit, no information is lost. A signal converted by the conversion method is converted into an analog signal, and a television signal processing apparatus can be realized in which image quality does not deteriorate due to aliasing distortion even through a low-pass filter circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an embodiment.

FIG. 2 is a conceptual explanatory diagram of a non-compression conversion method.

FIG. 3 is an explanatory diagram showing a basic configuration of conversion using an uncompressed conversion method.

FIG. 4 is a conceptual explanatory diagram of a compression conversion method.

FIG. 5 is an explanatory diagram showing a basic configuration of conversion of a compression conversion method.

[Explanation of symbols]

10: luminance signal system conversion circuit, 11: clock generation circuit, 12, 15, 18, 21, 24, 27, 30, 33
.., A switch circuit having a two-input one-output configuration; 13, a compression / non-compression switching circuit; 14, 22, 23; a digital / analog conversion circuit; 16, 25, 31; a low-pass filter circuit for a non-compression conversion system; 32: Low-pass filter circuit for compression conversion system, 20: System conversion circuit for chroma signal,
29, 30 ... Inverter circuit.

Claims (1)

(57) [Claims] An apparatus for converting a television signal having a certain aspect ratio into a television signal having a relatively large horizontal ratio at a digital signal stage, wherein the conversion method includes an uncompression conversion method and a non-compression conversion method. In a television signal processing apparatus that selectively employs a compression conversion method, a digital / analog conversion means for converting a television signal whose format has been converted into an analog signal, and filtering the analog signal when an uncompression conversion method is employed. A first low-pass filter, and a second low-pass filter having a higher cut-off frequency than the first low-pass filter for filtering the analog signal when the compression conversion method is employed. Television signal processing device.