JP3277514B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display system (hereinafter abbreviated as "VPS") or a wide display device such as a high-definition television for enlarging and projecting an image. The present invention relates to a video display device that can change the value of the image.

[0002]

2. Description of the Related Art In recent years, with the enhancement of video software, especially movie software, the enlargement of the television screen has been firmly established, and it is considered that the screen will be further shifted to a larger screen using a VPS in the future.

FIG. 6 is a schematic block diagram of a VPS. In the figure, 1 is a Y / C separation circuit for separating a video signal into a luminance signal and a chrominance signal, 2 is a video amplification circuit for amplifying the luminance signal Y, and 3 is a color signal demodulation for returning a color signal to an IQ or a color difference signal. Circuit, 4 is a matrix circuit for obtaining RGB signals, 5 to 7 are RGB cathode ray tubes (hereinafter abbreviated as CRT), 8 to 10 are lenses for focusing light of CRTs 5 to 7,
11 is a sync separation circuit for obtaining a sync signal from the video signal, 1
2 is a vertical deflection circuit, 13 is a horizontal deflection circuit for generating horizontal deflection and high voltage, and 14 is a screen for displaying the projected image.

[0004] Regarding the VPS configured as described above,
The operation will be briefly described below. The input video signal is input to the Y / C separation circuit 1 and is separated into a Y signal representing a luminance signal component and a C signal representing a color signal component in the video signal. The signals pass through a color signal demodulation circuit 3 for demodulation, and are respectively passed through a matrix circuit 4.
And converted into RGB primary color signals.
7 is driven. On the other hand, the synchronization relationship is separated from the video signal by a sync separation circuit 11, one enters a vertical deflection circuit 12 in the vertical direction and the other enters a horizontal deflection circuit 13 and outputs a signal for horizontal scanning. I do. Note that the horizontal deflection circuit 13 also includes a high voltage generation circuit. C
The images projected on the RTs 5 to 7 are projected on the screen 14 by the lenses 8 to 10 to reproduce a large image.

In order to further improve the image quality, consideration is given to converting the horizontal scanning frequency from 15.75 KHz to a double speed of 31.5 KHz by performing a clear vision process.

[0006] The above-described VPS can have the following functions. As shown in FIG. 7, a video signal of the normal NTSC system has an aspect ratio of 4: 3, but a video source includes an image of a cinema size or the like with a lack of upper and lower portions like a movie. In such a case, as shown in FIG. 8, for example, the horizontal screen size can be made variable while keeping the vertical direction constant, and vertically and vertically missing images are stretched to the full length, and horizontally stretched at the same ratio to avoid vertical and horizontal missing. A function to enjoy powerful images is being considered. As means for this extension, it is possible to change the horizontal / vertical deflection current (change the amplitude).

[0007] Depending on the type of the video source lacking the upper and lower parts, a subtitle superimposed is arranged outside the video part. In this case, the superimposed subtitle becomes invisible when the screen is fully enlarged. Therefore, a function has been conceived in which a subtitle superimposed part is stored and delayed using a field memory and synthesized with a video of the next field so that apparently only the subtitle superimposed can be moved and viewed.

FIG. 9 shows a block diagram of a conventional video signal processing apparatus. In this case, since subtitles are mostly white characters, only Y is supported, and processing is performed after Y / C separation in FIG. Reference numeral 15 denotes an A / D converter that performs analog / digital conversion of the Yi signal separated by the Y / C separation circuit 1, 16 denotes a field memory unit (hereinafter, memory) that stores A / D converted video data, and 17 denotes A control signal generator for controlling the blocks; 18 a gate circuit for removing only the subtitle portion of the A / D-converted video data; 19 a subtitle portion of the video data read out with delay from the memory 16 A gate circuit for extracting only the effective video data portion Y of the video data from which the subtitle portion has been removed;
1, a subtitle synthesizing unit for superimposing the subtitle data Y3 delayed to an appropriate position, a scanning conversion unit 21 for doubling the output of the subtitle synthesizing unit 20 using a line memory or the like, and a reference numeral 22. D for performing digital / analog conversion (hereinafter abbreviated as D / A) of the synthesized and double-speed converted video data
/ A converter. Reference numeral 23 denotes a PLL circuit for generating a clock, which outputs a clock frequency locked to the horizontal synchronization signal H. In this system, CLK is 14.38M
Hz (4 fsc, fsc = 3.579545 MHz), 2C
LK is 28.6 MHz (8 fsc) which is twice as large.

The operation of the video signal processing apparatus having the above configuration will be described below.

FIG. 10 shows an operation time chart. Description will be made based on this. Y / C separated Yi signal is A /
The digital signal is converted by the D converter 15. Here, the sampling frequency is selected to be 4 fsc, 8 bits, 256 gradations. The memory 16 uses a Fifo (first-in-first-out) type field memory. This memory 16 is written in synchronization with the basic vertical synchronizing signal V, and is read out in consideration of the delay time so that the caption comes to a desired position of the video data. The video data Y2 delayed in this manner is used to generate subtitle-only video data Y3 in the gate circuit unit 19 by the gate signal B obtained in the control signal generation unit 17, and similarly, the video data Y0 is generated by the gate signal A. , Gate circuit section 18
Then, the video data Y1 having only the effective video portion from which the subtitle portion has been removed is created, and each is input to the video synthesizing circuit 20 to superimpose the video and the subtitle. When super importing, you may mix as it is,
In order to make it easier to see, the video around the subtitles may be sunk or cut.

The synthesized video data Y4 is input to the scan conversion unit 21 and double-speed converted. The operation timing chart is shown in FIG. Conversion to double speed can be realized by writing with 4 fsc CLK in one horizontal cycle unit during writing and reading with 8 fsc 2 CLK in 1/2 horizontal cycle unit in reading. In reading, the same data is read twice. Alternatively, the current scanning line and the interpolation scanning line may be alternately read as in the case of clear vision. In the case of clear vision, each circuit excluding the A / D converter 15, the scan conversion unit 21, the D / A converter 22, and the PLL circuit 23 is further required for the interpolation scanning line.

Video data Y5 synthesized and converted to double speed
Is obtained by the D / A converter 22 as a video signal YO in which the subtitle insertion position is changed.

With the above arrangement, subtitles outside the video can be rearranged in the video. The caption in this case is delayed by one field but can be ignored in time.

[0014]

However, in the above conventional configuration, when an image having an aspect ratio such as a cinema size is enlarged to a screen having a wide aspect ratio as shown in FIG. 8, the amplitude becomes large both horizontally and vertically. However, there is a problem that, together with the enlargement of the image, the caption characters also become large, which affects the image.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides an image signal processing apparatus in which, even when an image is enlarged, subtitle characters are not enlarged.

[0016]

In order to solve the above-mentioned problems, a video signal processing apparatus according to the present invention uses a scan conversion memory independent of a conventional scan conversion for a delayed subtitle signal, and uses a memory for horizontal conversion. It can be realized by setting the frequency of the read clock to a higher value and compressing the data to read it, and then stopping writing twice for vertical speed conversion, or performing double speed conversion only on the current scanning line without using interpolation scanning. . As a specific configuration, A / D conversion means for analog-to-digital conversion of a television signal and a line memory for a first video signal in which a subtitle portion of the A / D-converted video signal is deleted by a first gate are used. A first scanning conversion means for converting the horizontal frequency to twice to obtain a second video signal, and reading the A / D converted first video signal at twice the horizontal frequency using a field memory. A delay means for outputting and delaying the third video signal of only the subtitle portion by the second gate, a control means for controlling the amount of delay by the delay means, and a reading speed of the delay means for writing. Double speed control means for performing at a double speed, clock generating means for generating a clock for writing and reading each memory at a clock frequency locked to a horizontal frequency, and And a D / A converter for digital-to-analog conversion of the synthesized video signal, the synthesizing means for synthesizing the video signal and the third video signal of only the subtitle portion. Is characterized in that the vertical amplitude of the video signal is set to 1/2 of that of the second video signal.

[0017]

According to the present invention, the subtitle signal moved even if the image is enlarged can be arbitrarily changed according to the clock frequency, and the vertical can be changed to 1/2 according to the clock frequency.
And the effect on the image can be reduced.

[0018]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video signal processing apparatus according to an embodiment of the present invention. 15 to 2 in the figure
Up to 3 is the same as in the conventional example, and will not be described. Numeral 28 indicates the reading speed of the field memory 16 as 2 which is the writing speed.
This is a double speed control circuit required to make the speed double.

The operation of the video signal processing device configured as described above will be described based on the timing chart of FIG. The field memory 16 is initially reset in units of a vertical cycle.
The delay is caused by shifting the read reset position. In this case, the period is 15.75 KH
z. Here, 2CLK which is twice the read speed only
When the data is read at (8 fsc), the data is read as Y7 with a horizontal cycle of 1/2. Although the data is read twice, it is a field memory and is delayed by one field, so that there is no inconsistency in the end of the data. This delayed and doubled video signal Y
7 is selected only by the gate circuit 19 in the subtitle part, and is input to the synthesizing circuit 20. On the other hand, the output signal Y0 of the A / D converter 15 passes through the gate circuit 18 so that only the subtitle portion is deleted, enters the scanning converter 21, is output as a double-speed video signal Y6, and is similarly input to the synthesizing circuit 20. . At this point, the double-speed video signal Y6 has been read twice for one horizontal period, and the double-speed video signal Y7 has been read only once. Therefore, when these are combined, the double-speed video signal Y
7 can be halved in the vertical direction with respect to the same double-speed video signal Y6.

As described above, according to this embodiment, the video width in the vertical direction can be halved by doubling the reading speed of the field memory.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to FIG.

In FIG. 3, steps 15 to 23 are the same as those in the conventional example, and therefore will not be described. Reference numeral 24 denotes a PLL circuit which generates a read clock locked to the horizontal synchronizing signal H similarly to the PLL circuit 23, and is configured to change the frequency division ratio and output a clock having a higher frequency than the clock output from the PLL circuit 23. I have. Reference numeral 25 denotes a scan conversion circuit for converting the video signal Y3 delayed and gated by the field memory 16 to double speed, 26 a D / A conversion circuit for D / A output thereof, and 29 a readout circuit of the scan conversion circuit 25. The read clock from the PLL circuit 24 is higher than the scan conversion circuit 21, and the number of clocks in one horizontal scanning period is determined. More specifically, the control is performed using the read enable of the memory. 27 is a D / A conversion circuit 22,
This is a synthesizing circuit for synthesizing the subtitle signal Y11 after returning to an analog signal at 26 with the video signal Y10 from which subtitles have been removed.

[0024] Based on FIG. 4 for the above configuration <br/> be described. The scanning conversion circuit 21 and the D / A conversion circuit 22 are the same as in the conventional example. The write side of the scan conversion circuit 25 is the same as the scan conversion circuit 21, but the read side is higher than the scan conversion circuit 21, and the horizontal time axis is compressed from the double-speed video signal Y6 as shown by Y9 in FIG. Read in the form. In the case of NTSC, the relationship between 4fsc and the horizontal synchronizing signal H is 4fsc, which is 910H. Even if the clock frequency becomes higher on the read side, no problem occurs unless this relationship is broken. As described above, an independent scan conversion circuit 25 is also provided for the subtitle video signal Y3 delayed from the conventional one, and the readout clock is increased to compress the time axis, thereby delaying and extracting the subtitle video. It is also possible to reduce the signal Y3 in the horizontal direction.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to FIG. In FIG. 5, 1
Since steps 5 to 29 have been described above, they are omitted. The video signal YO returned to an analog signal by the D / A conversion circuit 22 is input to the matrix circuit 4 and is calculated as a color signal C and demodulated into an RGB signal. An RGB switching circuit 29 switches between a video signal and an on-screen RGB signal for on-screen display on a CRT.

In the above configuration, the synthesis in FIG. 3 is performed only as a luminance signal. Therefore, the subtitle signal is synthesized as the same white character as the original signal.

In this configuration, the subtitle signal subjected to scan conversion with a delay can be colored by being input to the RGB switching circuit 30 in the same manner as the RGB signal for on-screen after D / A conversion. . In this case, the subtitle signal Y11 is one, and the R
Red can be displayed by inputting only to G, green can be displayed by inputting to G, and cyan can be displayed by inputting to G and B, and it goes without saying that eight colors (including black) can be reproduced by a combination. As the switching signal in this case, a part or output of the input signal of the D / A conversion circuit 26 may be used.

As described above, according to the present embodiment, it is possible to provide coloring by using the RGB switching circuit in the combining circuit and using the subtitle signal Y11 as an on-screen signal input.

[0029]

As described above, according to the present invention, the subtitles are not affected even when the video is enlarged horizontally and vertically, or when the subtitle signal is extracted from the video and delayed for synthesis. Instead, it can be relatively reduced, and the influence on the original video signal can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the video signal processing device according to the first embodiment.

FIG. 3 is a block diagram of a video signal processing device according to a second embodiment of the present invention.

FIG. 4 is a timing chart of a video signal processing device according to a second embodiment.

FIG. 5 is a block diagram of a video signal processing device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a VPS.

FIG. 7 is a diagram showing a display example of a cinema size on a television screen.

FIG. 8 is an enlarged view of FIG. 8;

FIG. 9 is a block diagram of a conventional video signal processing device.

FIG. 10 is an operation timing chart of a conventional video signal processing device.

FIG. 11 is a timing chart of a scan conversion operation of the conventional video signal processing device.

[Explanation of symbols]

 Reference Signs List 24 second PLL circuit 25 second scan conversion circuit 26 second D / A conversion circuit 27 analog synthesis circuit 28 double speed control circuit for field memory 29 double speed control circuit for line memory 30 RGB switching circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/262-5/278 H04N 5/445 H04N 7/015

Claims (5)

(57) [Claims] An A / D converter for converting a television signal from analog to digital, and a subtitle portion of the A / D converted video signal is supplied to a first gate.
A first <br/> scan conversion means for obtaining a second image signal by converting the horizontal frequency doubling using a line memory more first video signal deleting the A / D converted video The signal is read out using a field memory at twice the horizontal frequency and delayed to produce a second signal.
Delay means for obtaining a third video signal of only the subtitle part by the gate of the control means, control means for controlling the amount of delay by the delay means, and double speed control for performing the read speed of the delay means at twice the writing speed Means, clock generation means for generating clocks for writing and reading of the memories at a clock frequency locked to a horizontal frequency, and the second video signal from which only the subtitle portion has been deleted and the third video image having only the subtitle portion Synthesizing means for synthesizing signals; and D / A converting means for digital-to-analog conversion of the synthesized video signal, wherein the vertical amplitude of the delayed third video signal is １ ／ of that of the second video signal. A video signal processing device, characterized in that: 2. A / D conversion means for analog-to-digital conversion of a television signal, and a subtitle portion of the A / D-converted video signal to a first gate.
Required to achieve the first scanning conversion means for obtaining a second image signal by converting the horizontal frequency doubling using a line memory more first video signal deleting, the first scanning conversion means First clock generating means for generating clocks for writing and reading of the memory at a clock frequency locked to a horizontal frequency, and a first for digital-to-analog conversion of the second video signal
D / A conversion means; and delay means for arbitrarily delaying the A / D-converted video signal using a field memory to obtain a third video signal of only a subtitle portion by a second gate . A second scan conversion means for converting the third video signal to a double horizontal frequency using a line memory and obtaining a fourth video signal whose read speed is higher than that of the first scan conversion means; A second D for digital-to-analog conversion of the fourth video signal
/ A conversion means; second clock generation means for locking the read clock of the second scan conversion memory at a horizontal frequency and generating the read clock at a higher frequency than the first clock generation means ; Double speed control means for controlling the read speed of the scan conversion means to perform the writing at twice the writing speed; and a first for digital-to-analog conversion and output of the second video signal from which the subtitle portion of the video signal has been deleted. Synthesizing means for synthesizing an output signal of the D / A converting means and an output signal of the second D / A converting means for performing digital-to-analog conversion of the third video signal of only the subtitle portion and outputting the result; A video signal processing device, wherein the converted fourth video signal is compressed in comparison with the second video signal in a horizontal cycle. 3. A demodulation means for converting an output of the first D / A conversion means into a luminance signal, performing a matrix with a chrominance signal and demodulating to RGB, an RGB output signal from the demodulation means and a second D / A. An RGB switching means for switching the output signals from each other by regarding the output signal from the conversion means as an RGB signal, and for synthesizing the fourth video signal which has been delayed and horizontally compressed and the second video signal which has been scan-converted, 3. The video signal processing device according to claim 2, wherein the fourth video signal is colored. 4. The third video signal of only the subtitle portion is read out by using a second scan conversion memory independent of the first scan conversion, and setting the read clock frequency of the memory higher in the horizontal direction. The third image of only the above subtitle part is compressed by stopping the double writing for double speed conversion in the vertical direction, or by performing double speed conversion only on the current scanning line without using interpolation scanning. Horizontal swing of signal
The width can be arbitrarily compressed by the clock frequency ,
3. The video signal processing device according to claim 1, wherein the direct amplitude is compressed to half . 5. The clock frequency of a second clock generating means.
4. The video signal processing device according to claim 3, wherein the number is arbitrarily variable.