JP4509407B2 - SCH detector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an SCH detection device for an input analog video signal, and more particularly, to an analog signal in a device for converting an analog video signal into digital video or a digital processing device used in a digital video recorder. The present invention relates to a video signal SCH detection apparatus.
[0002]
[Prior art]
The composite video signal in the NTSC system is an interlace system, and is composed of an odd field and an even field. That is, in the case of a still image, the repetition of the image is an odd / even two-field cycle. However, in relation to the color carrier signal, the phase is shifted by 90 degrees for each field, and the original image signal is returned in four fields. This is called a four field sequence and is also called a color field sequence.
[0003]
In connection with the fact that NTSC video signals have this four-field sequence, the conventional EIA RS-170 has been adopted as a studio standard for composite sync signals, particularly for the purpose of preventing horizontal shift of images when recording to a VTR. In contrast, a new EIARS-170A has been created. In this standard, a phase relationship (shown in FIG. 4) between a horizontal synchronizing signal (H-SYNC) and a color subcarrier signal (color burst signal signal phase) is defined. This relationship is called SCH (Sub Carrier to Horizontal).
[0004]
The broadcast VTR is required to be an input signal of the above-mentioned RS-170A standard that defines SCH as the input signal for the purpose of quality control at the time of recording the input signal. However, there are many conventional devices that generally do not satisfy the RS-170A standard. Therefore, there has conventionally been an apparatus (measuring machine) for measuring an SCH by inputting an analog composite television signal.
[0005]
A conventional method for measuring SCH is based on an analog signal having a frequency phase-locked to a color burst signal (color reference signal) of a composite signal. Japanese Patent Laid-Open No. 3-235598 discloses an SCH detection device for measuring the phase relationship between a digital clock having a frequency locked to a color burst signal in a composite signal and a horizontal synchronizing signal, in other words, a difference in analog timing. Is disclosed.
[0006]
[Problems to be solved by the invention]
By the way, regarding the format of the digital video signal, the International Telecommunication Union (ITU) has decided on ITU-R BT. Recommendation 656 (formerly CCIR656) is issued. This recommendation is based on ITU-R BT. 601 is an interface for digital component video signals in 525 line and 625 line television systems operating at 4: 2: 2 levels. ITU-R BT. 601 is a digital television studio encoding parameter for standard 4: 3 aspect ratio and wide screen 16: 9.
[0007]
In the case of an NTSC signal as a television signal, there is a relationship of fsc = (455/2) fh between the color subcarrier signal frequency fsc and the horizontal synchronizing signal frequency fh, and between the vertical synchronizing frequency fv. Has a relationship of fh = (525/2) fv.
[0008]
According to the above-mentioned recommendation, it is necessary to generate a clock (hereinafter abbreviated as fc) of 525 lines, that is, 1716 times the horizontal synchronization frequency of the NTSC standard television signal and a frequency of 27 MHz. This frequency is determined in consideration of mutual conversion between the PAL and NTSC television signals, but is not an integer multiple of the color subcarrier signal frequency of the NTSC television signal. The ratio of fsc and fc is 455/3432 = (13 × 7 × 5) / (13 × 11 × 3 × 2 × 2 × 2) = (7 × 5) / (11 × 3 × 2 × 2 × 2) = 35/264.
[0009]
Therefore, in the apparatus according to the above-mentioned recommendation, there is no clock that is an integral multiple of the color subcarrier signal of the television signal, and therefore, when such a device attempts to measure the SCH of the input signal. This clock cannot be used as in a device using a clock with a color subcarrier frequency four times that of the prior art.
[0010]
Further, the above-described SCH detection apparatus is used when the accuracy of measurement is affected by a delay element that performs analog delay, and such a delay element is used when aiming at an IC, in other words, a complete digitalization. Is impossible.
[0011]
The present invention has been made in view of such problems, and its object is to provide analog television broadcast (terrestrial, CS / BS) NTSC or PAL analog television signals, or the like. The ITU-R BT. It is an object to provide an SCH detection device for an analog video signal that can easily measure the SCH of an input signal in an analog / digital conversion device that converts the digital video signal into a format conforming to 601 or 656.
[0012]
[Means for Solving the Problems]
In order to achieve such an object, the present invention provides an SCH detection apparatus for an analog video signal, wherein the analog video signal is input and the analog video signal is synchronized. An A / D converter for converting a digital signal including a portion and a video portion into a quantized digital signal, and 0 of a horizontal synchronization component in the analog video signal _H Reference point or 0 _H A system clock signal generator for generating a system clock signal for sampling the vicinity of the reference point, and a sin / cos signal phase-coupled to the color burst portion of the color component signal extracted from the quantized video signal. A digital color demodulator having a sin / cos table for outputting, and inputting the color component signal and demodulating the color based on a signal output from the sin / cos table; _H 0 to extract the timing signal associated with the reference point _H A reference extraction circuit, address information of the sin / cos table, and the 0 _H An SCH measurement register that inputs a signal from a reference extraction circuit unit and measures the SCH; and a conversion table that converts an output signal of the SCH measurement register into phase angle data, and outputs the output signal of the conversion table to SCH information. It is characterized by taking out as.
[0013]
The invention according to claim 2 is the SCH detection device according to claim 1, wherein the system clock signal is generated from a PLL with reference to a synchronization component signal of the quantized digital signal. It is characterized by.
[0014]
The invention described in claim 3 is the SCH detection apparatus according to claim 1 or 2, wherein the system clock signal is not an integer multiple of the subcarrier signal frequency. It is.
[0015]
The invention according to claim 4 is the SCH detection apparatus according to any one of claims 1 to 3, wherein the conversion table is 180 degrees with an angle represented by a cos output signal of the sin / cos table. It is characterized by outputting different values.
[0016]
The invention according to claim 5 is an SCH detection device for an analog video signal, which receives an analog video signal and converts it into a quantized digital signal including a synchronization portion and a video portion of the analog video signal. An A / D converter for conversion, a system clock signal generator for generating a system clock signal phase-locked to a horizontal synchronization component of the analog video signal, and 0 of a horizontal synchronization component included in the quantized digital signal _H Reference point or 0 _H Samples with quantized values after the reference point are quasi-zero _H Quasi-zero extracted as a reference point _H Reference point extraction unit and the extracted quasi-zero _H 0 from the reference point sample _H A phase difference output unit that calculates and outputs a phase up to a reference point, and a sin / cos signal that is phase-coupled to a color burst portion of a color component signal extracted from the quantized video signal. a digital color demodulation circuit unit that has a cos table and inputs the color component signal to demodulate the color based on a signal output from the sin / cos table; address information of the sin / cos table; _H And an SCH measurement register that inputs an output signal of the reference extraction means and measures SCH, and generates SCH information based on the output of the SCH measurement register and the phase difference output means. .
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 shows the input of an NTSC television signal to which the present invention is applied, and ITU-RBT. FIG. 2 is a diagram for explaining a main part of an analog / digital conversion apparatus that converts a digital video signal in a format conforming to 601 or 656; In the description, an example in which the clock used for digital processing is not an integer multiple of the color subcarrier signal frequency will be described as an embodiment. However, it is apparent that the present invention can be applied even if it is an integer multiple.
[0019]
The apparatus shown as an embodiment in FIG. 1 also processes an analog composite television signal and an analog separate video signal in which a luminance signal and a color signal are separated, such as an S-VHS signal. Is assumed.
[0020]
In FIG. 1, reference numerals 101 and 102 denote A / D converters that input a luminance signal and a color signal as such analog signals and convert them into digital signals. In the case of a normal television signal, it is digitized only by the A / D converter 101 and separated into a luminance signal and a color signal by the Y / C separation unit at the next stage, and the luminance signal is processed at the luminance signal processing circuit 104 at the next stage. Is processed. In the case of an analog separate video signal, the luminance component signal is A / D converted by the A / D converter 101 and the color signal component signal is A / D converted by the A / D converter 102.
[0021]
The output of the A / D converter 102 and the color signal separated from the Y / C separation unit are switched by a switching unit 105 controlled in conjunction with an input signal switching unit (not shown), and color demodulation processing indicated by reference numeral 106 is performed. Sent to the department.
[0022]
Here, the A / D converter 101 A / D converts both the video component and the range of the synchronization component of the input signal.
[0023]
A clock generator that generates a system clock for digital processing with respect to the video signal processing system as described above inputs a synchronization component signal from the A / D converter 101 as shown in the figure. , A synchronization separation unit 122 that performs synchronization separation, and a PLL unit that receives a signal of the H-SYNC component from the synchronization separation unit 122 and generates a clock signal having a frequency 1716 times the signal frequency. The clock signal from the PLL OSC unit is sent to the A / D converters 101 and 102 and to each processing unit (not shown). To be precise, a clock having a frequency of 13.5 MHz which is 1/2 of 27 MHz generated in the PLL OSC unit (frequency of 858 times the frequency of H-SYNC) is sent to each processing unit.
[0024]
The color demodulation is performed by a color demodulation unit 106 including a multiplier 107/108, an LPF 109/110, a phase difference detection unit and filter unit 111, a DTO (digital time oscillator) unit 112, and a sin / cos table 113. -Y signal and RY signal are generated. This color demodulation method is a digital method realizing a method called X demodulation or Z demodulation.
[0025]
Every color signal is a combination of two signals, the color burst signal phase shifted by 90 degrees (R−Y) and the B−Y signal shifted by 180 degrees. Therefore, the color signal is demodulated based on the phase difference between the color signal and the color burst signal. This demodulation method will be briefly described below.
[0026]
FIG. 2 shows the phase relationship between the color burst signal (reference signal), the color signal (C (ωt)), and the color difference signals Cr and Cb (where Cr = R−Y and Cb = B−Y). ing. Here, if the reference signal = −cos ωt (= cos (π + ωt)), the color signal C (ωt) is
C (ωt) = Cb × sinωt + Cr × cosωt (Formula 1)
It is represented by A signal of this format is output from the switch 105 in FIG. When the equation 1 is multiplied by cos ωt and sin ωt, the following equations 2 and 3 are obtained.
C (ωt) × cosωt = Cb × sinωt × cosωt + Cr × (cosωt) ² ... (Formula 2)
C (ωt) × sinωt = Cb × (sinωt) ² + Cr × cosωt × sinωt (Formula 3)
here,
sin (x) × cos (y) = (1/2) (sin (x + y) + sin (xy), (cos (x)) ² = (1 + cos2x) / 2, (sin (x)) ² = (1-cos2x) / 2
Therefore, Equation 2 and Equation 3 are respectively
C (ωt) × cosωt = Cb × (1/2) × sin2ωt + Cr × (1/2) × (1 + cos2ωt) (Formula 4)
C (ωt) × sinωt = Cb × (1-cos2ωt) / 2 + Cr × (1/2) × sin2ωt (Equation 5)
It becomes.
[0027]
Expressions 4 and 5 described above indicate signals having DC components of Cr / 2 and Cb / 2 and double frequency components, respectively. Accordingly, when the color signal is multiplied by the multipliers 107 and 108 with the cos and sin data from the cos / sin table, the filter processing is performed by the LPF that removes the frequency component twice the color carrier frequency. As a result, Cr, Cb, that is, RY and BY signals are obtained as outputs.
[0028]
For the color burst (color reference signal) portion, the outputs of the multipliers 107 and 108 are as follows.
Reference signal × cosωt = -cos (π + ωt)) cosωt =-(cosπcosωt-sinπsinωt) cosωt = -cosπcosωt ² -sinπsinωtcosωt = -cosπ (1 + cos2ωt) / 2-sinπsin2ωt =-(cosπ) / 2- (cosπcos2ωt) / 2-sinπsin2ωt (Expression 7)
Reference signal × sinωt = -cos (π + ωt)) sinωt =-(cosπcosωt-sinπsinωt) sinωt = -cosπcosωtsinωt-sinπsinωt ² =-(cosπsin2ωt) / 2-sinπ (1-cos2ωt) / 2 =-(cosπsin2ωt) / 2- (sinπ) / 2- (sinπcos2ωt) / 2 (Equation 8)
In the above, focusing on only the DC component, Equations 7 and 8 are-(cosπ) / 2 and-(sinπ) / 2, respectively. Each is 1/2, 0.
[0029]
In the above description, it is assumed that the sin / cos table output is in the above-described relationship in the phase relationship with the color burst signal of the color signal. Actually, a PLL loop including a phase difference detection / filter unit 111, a DTO unit 112, and a sin / cos table is configured. The phase difference detection / filter unit 111 receives the burst flag generated from the synchronization separation unit 122, generates a phase error signal or a frequency error based on the Cb and Cr values of the part, and further calculates an operation error and the like. It is sent to the DTO section through the filter to be removed.
[0030]
FIG. 3 is a diagram for explaining the DTO unit 112 and the SCH detection circuit 124 in more detail. The same parts as those in FIG. 1 are denoted by the same reference numerals.
[0031]
In FIG. 3, the register 302 of the DTO unit is configured with 16 bits, for example, and the adder 301 adds the error signal described above, a constant described later, and the output of the register 302, and uses the addition result as the input of the register 302. Yes. In the embodiment, the clock frequency supplied to this register is 13.5 MHz.
[0032]
When the frequency of the clock for driving these is 13.5 MHz, since one line period is 858 clocks, and this period is 455/2 times the subcarrier frequency, 858 / (455/2) = about 3.771428572 clocks The value represented by these 16 bits changes with the period. This value itself is the same as when a sawtooth wave having the frequency of the subcarrier signal is sampled with a 13.5 MHz clock, and each value represents the phase of the subcarrier signal.
[0033]
With this 16-bit output of DTO, for example, in decimal representation, when outputting a value obtained by adding 17,377 (= 65,536 / 3.771... = 17,376.97 rounded off), Data whose frequency changes at a frequency of 3.579551696 MHz is obtained. In this case, the data string of 1, 1 + 17, 377, 1 + 2 * 17, 377 is 360 // in contrast to the data string of 0, 17, 377, 2 × 17, 377,. It represents a 3.579551696 MHz signal shifted by 65,536 degrees. The exact frequency of the subcarrier signal is 3.579545455 MHz. The difference between the two is about 6 Hz.
[0034]
In the NTSC system, the horizontal frequency f _H , Subcarrier frequency f _SC , Vertical frequency f _V In between, f _H = 4.5MHz / 286, f _SC = F _H (455/2), f _V = 2f _H There is a / 525 relationship.
[0035]
The constants input to the adder 301 in FIG. 3 are 17,377 (decimal notation) because the above-described embodiment is for the NTSC signal. This value is different because the color carrier frequency is different in the case of the PAL signal.
[0036]
Various proposals have been made for the above-described error signal generation method and a specific circuit configuration including the register 302. For example, in the above-described Expressions 7 and 8, the signal of each frequency 2ωt is ignored, and furthermore, since the phase is not locked, π is replaced with a variable, and becomes 0 when this variable is π or 3π. By obtaining a function result having a specific slope at a point as an error signal, the PLL circuit can be operated so as to converge to a desired phase. Therefore, by using such a function result as an error signal, in a converged state, a cos signal having a phase difference of π with respect to the color reference signal and a sin signal having a phase difference of π / 2 are obtained. be able to. Further, as described above, when the color burst signal frequency of the input color signal is 3.579551696 MHz as described above, the error signal becomes zero at the stable time when the PLL operation converges, and this state is maintained. The role of the error signal during the transition means a correction amount of the phase of the register change.
[0037]
In the embodiment, the number of bits of the register 303 is 16 bits from the viewpoint of frequency accuracy. However, the number of bits for driving the sin / cos table is not 16 bits, and in the embodiment, the number of bits of the register 303 is high. Eight bits are used as table address information. In this way, a signal having a change of sin and cos at each table output is obtained.
[0038]
The function of the sin / cos table is to output sin and cos values in one cycle, that is, from 0 degrees to 360 degrees in the range of 0 to 255 in decimal notation in the above-described embodiment. .
[0039]
Next, a system clock that is the basic operation of the circuit described above will be described.
[0040]
FIG. 4 is an excerpt from the RS-170A standard described above. The amplitude level is indicated by IRE, where 100 IRE is the white level, 0 IRE is the blanking level, and −40 IRE is the leading edge level of synchronization. Also, the horizontal base point is 0 in FIG. _H The timing of the level-20IRE portion of the H-SYNC signal shown as the reference point is shown. From this timing, the color burst signal is started after a period corresponding to 19 cycles of the subcarrier signal. In FIG. 4, the vertical axis represents amplitude, the unit is IRE, the horizontal axis is the time axis, and the unit is μs.
[0041]
0 _H If the definition of the reference point is expressed by another expression, the level of a portion called a front porch or a back porch of the horizontal synchronization signal shown as the reference level in FIG. 5 and the SYNC signal shown in FIG. 4 or FIG. This is a timing having a midpoint level with the tip level of 4.7 μs ±, 0.02.
[0042]
H-SYNC leading edge, ie, 0 in FIG. _H The interval from −4IRE to −36IRE is 0.14 ± 0.02 μs (0.14 μs is a half period of the subcarrier signal) so that the signal components before and after the reference point become subcarrier frequency signal components. It has become. This has the purpose of preventing the time relationship between the reference point and the subcarrier signal from being lost even if the frequency characteristic or the phase characteristic is changed.
[0043]
FIG. 1 shows a PLL oscillator that uses H-SYNC in a quantized signal as a reference. In the conventional analog circuit, the H-SYNC signal as the reference signal is generated as follows. A voltage value between the blanking level of the analog video signal and the front-end level of the H-SYNC (the lowest level in the sync signal waveform in the negative direction) is obtained, and an intermediate voltage value is generated. The generated voltage The synchronization portion of the input signal is sliced by value, and the leading edge of the separated synchronization signal (having analog timing) as a result of slicing is used as the reference signal for the PLL. Even with the clock signal generated in this way, the A / D converter uses 0 of RS-170A as indicated by reference numeral 501 in FIG. _H The reference point was not necessarily sampled. This is because the analog time delay of each processing circuit has an influence. There are a delay in the A / D converter, a filter delay before the A / D converter, a system path for A / D conversion and a system path for synchronization separation, and the like. In general, such a delay time slightly changes depending on the temperature or the like. However, if such a delay temperature change or the like is ignored, or if such a change is small and can be ignored, a certain relationship can be maintained. For example, it is possible to match or substantially match by providing a phase adjustment circuit.
[0044]
In this embodiment, instead of the conventional analog synchronization separation, the reference signal to the PLL unit 121 having an analog VCO is obtained by performing synchronization separation from the signal quantized by the A / D converter. It is a signal. Therefore, in order to make it the same as a reference signal having a conventional analog timing, a special comparison is made between the signal obtained by dividing the oscillated clock signal and the signal of the synchronous part that is quantized. Thus, the middle point of H-SYNC indicated by reference numeral 501 in FIG. 5 is finally sampled. To be precise, the clock frequency generated by this part is twice the frequency of 13.5 MHz, and the point indicated by reference numeral 501 in FIG. The error signal is generated digitally so that one of the 5 MHz clocks samples the point indicated by reference numeral 501 in FIG.
[0045]
Normally, the leading edge portion of the sync signal (starting portion of the negative direction signal) has a slope, and this portion is sampled with a nominal 27 MHz frequency sampling clock, so that a quantized value of several clocks is obtained. It is done. One of the quantized data of the leading edge portion of the synchronizing signal having such a quantized value is an intermediate value between the leading value of the synchronizing component level and the blanking level, that is, 0. _H Phase control is executed so as to be a reference point. In other words, the phase error obtained when the timing of the quantized sample after the adjacent quantized sample having the quantized value before and after such an intermediate value is used as the reference signal is assumed to be a virtual 0 _H The phase error up to the reference point is digitally calculated, and the phase error resulting from the calculation is added to generate a final phase error signal. In this case, the above-described 27 MHz is divided into 13.5 MHz, and the changing point of the clock having the frequency of 13.5 MHz is 0. _H Considered to be a reference point.
[0046]
Therefore, 13.5 MHz as a system clock generated from the generated clock having a frequency of 27 MHz, that is, one of the system clock trains of the circuit including the DTO unit described above is from the viewpoint of quantized data. , 0 in RS-170A _H It has a reference point timing. However, a certain amount of error is included depending on the input signal. However, the magnitude of this error can be ignored in view of the accuracy required as the SCH information.
[0047]
From the viewpoint of quantized data, the above-described method is 0 in RS-170A. _H It will be understood that a system clock signal including a reference point is generated and the output value of the DTO is obtained in relation to the phase of the color burst signal in the quantized data.
[0048]
If the input timings of the multipliers 107 and 108 shown in FIG. 1 are used as a reference for examining the phase (processing delay) in digital processing, the preceding stage includes the Y / C separation unit 103 and the switching circuit 105. In the previous stage of this Y / C separation unit, 0 in RS-170A _H A signal associated with the reference point, with a delay of 0 in FIG. _H A signal that is the basis of the reference signal is generated.
[0049]
The processing delay in the Y / C separation unit 103 includes a delay due to filter processing including the preceding and following sample values. Further, the output signal of the DTO on the demodulation circuit side is also advanced by at least one clock with respect to the reference point for the phase examination described above. In the embodiment, since the system clock frequency is 13.5 MHz and is not an integer multiple of the subcarrier signal frequency, the processing returns to the original phase (rotates 360 degrees) with a delay of 4 clocks. I can't.
[0050]
Therefore, 0 _H 0 taken out by the reference extraction circuit _H The SCH shown in FIG. 3 is obtained by delaying one clock signal having the timing of the reference point in units of clocks in consideration of the above-described processing delay and phase matching (or time matching) with the output timing of the DTO. Can be fetched from the register 302 into the register 303. In FIG. 3, 0 supplied to the register 303. _H The signal is a clock signal that is time-matched with the DTO output signal.
[0051]
The line from the register 302 to the register 303 is supplied with the upper bits of the register 302, for example, 8 bits. In this case, for example, if the value represented by 8 bits is 00 in hexadecimal notation, the SCH is 0 degrees, and if it is 128, it represents 180 degrees. In reality, there is jitter in the output value of the DTO, so there is no delay. _H If the reference signal is generated once in one scanning period, for example, a state where 00 and 01 are alternately output for each line in hexadecimal notation is also assumed. In order to avoid this, for example, a clock applied to the register 303 (delay 0) _H By setting the reference signal) to about once per second, it is possible to obtain a data value that changes gently and is easy to read. Since the output of the register 303 is a binary representation and not a frequency unit, it is converted into a frequency by the conversion table 304 and output. In this conversion, as shown in FIG. 2, the phase of the reference signal (color burst signal) is 180 degrees different from the phase of the cos output of the sin / cos table. Need to create.
[0052]
In the above description, 0 _H Consider the error that the determination of whether or not a reference point has on the SCH. Usually, the generated 13.5 MHz has a jitter of about ± 1 degree at the subcarrier frequency, and an error in terms of the quantization accuracy of the synchronization component to be quantized occurs. For example, when a signal having a slope as shown in FIG. 4 or FIG. 5 is quantized, for example, when expressing a peak value 133 IRE including a color signal and a synchronous 40 IRE by 8-bit quantization, The synchronous component 40IRE is divided into about 59 quantized values. Therefore, the range of 0.14 ± 0.02 μs of the leading edge portion of the synchronization signal shown in FIG. 4 corresponds to a period of about 2 clocks, and when the first quantized value is 40, the next quantized value is About 10 is assumed. Then, the difference 30 between the two is that the clock of the frequency of 13.5 MHz is about 95 degrees per clock, so an error of 95 degrees / 30 = about 3.2 degrees with respect to the assumed 1-bit error, Will be generated for the SCH. However, it is possible to reduce the error due to this 1-bit error by averaging.
[0053]
The present invention has been described above by taking the present embodiment as an example, that is, on the premise of an NTSC television signal, but it is easy to change to the following form without departing from the spirit of the present invention.
[0054]
1. System clock signal is 0 _H The reference point or its vicinity was sampled, but 0 _H Even at a position away from the reference point, the 0 _H If the time interval from the reference point is constant, for example, 0 _H If you always sample a point that was sent 1/2 clock from the reference point or a point in the vicinity of it, the SCH information measured based on this sample point has an angle of 95.4545 degrees for one clock of 13.5 MHz. SCH information can be obtained by adding half, 47.72 degrees. If the shift is 1/3 clock, 31.82 (= 95.4545 / 3) degrees may be added.
[0055]
FIG. 6 is a diagram for explaining the above. When sampling is performed stably as shown in FIG. _N Quasi-zero for the time being _H The above-described circuit is operated as a reference point. In this case, the sample _N Is a sample having a quantized value at or below the midpoint of the sync level. Where the sample _N The quantization value of L _N ,sample _N-1 The quantization value of L _N-1 When the midpoint level of the synchronization level is C, the phase difference shown in FIG. _N -L _N-1 | / | L _N This corresponds to a clock of −C |. Expressed as an angle, 95.4545 × | L _N -L _N-1 | / | L _N −C | degrees.
[0056]
Such a case is assumed when a system clock is generated by an analog circuit that is phase-locked to the separated horizontal synchronization component signal.
[0057]
FIG. 7 is a diagram showing a configuration in the case described above. The same parts as those in FIG. 1 are denoted by the same reference numerals. The difference is that the reference signal for phase comparison to the PLL OSC 121 is input to the input signal of the A / D converter 101 and the signal obtained by slicing the midpoint of the synchronous portion in an analog manner is the H-SYNC signal. This is obtained from the sync separator 131 for extracting Further, a signal from the synchronization separation unit 122 that separates the synchronization component of the quantized signal is obtained, and the above-described quasi-zero value is obtained. _H An error (phase difference) detection unit 132 that detects an error (clock phase difference) between the reference point and the timing of the midpoint of the synchronous component at the previous timing by the above-described method is provided. And this error detection part 132, and quasi-zero _H A calculation unit 133 that calculates data from the SCH detection circuit based on the reference point and outputs final SCH information is provided.
[0058]
2. The present invention is applicable even in the case of a PAL signal or in the case of a frequency of a subcarrier signal whose system clock frequency is four times.
[0059]
【The invention's effect】
As described above, according to the present invention, an analog video signal is input and an A / D converter that converts the analog video signal into a quantized digital signal including a synchronization portion and a video portion, and analog video 0 of horizontal sync component in signal _H Reference point or 0 _H It has a system clock signal that samples the vicinity of the reference point and a sin / cos table that outputs a sin / cos signal that is phase-coupled to the color burst portion of the quantized video signal, and is extracted from the quantized signal. In an apparatus including a digital color demodulation circuit that demodulates a color component signal based on a signal output from the sin / cos table, _H 0 to extract the timing signal associated with the reference point _H Reference extraction circuit and 0 _H A register for taking in address information of the sin / cos table by a signal from the reference extraction circuit;
Since a conversion table for inputting the output of the register and converting it into data representing the phase angle is provided, SCH information can be extracted from the output data of the conversion table.
[0060]
Further, the above-described method can be digitally processed and can be integrated into an IC.
[0061]
In addition, when a digital signal processing circuit for a video signal having a digital color demodulation circuit is provided, the sampling point by the system clock signal is 0. _H Even if it is deviated from the reference point, it is 0 from the neighboring sampling points. _H By linearly interpolating the reference point and adding / subtracting the deviation, it is possible to obtain SCH information with a required accuracy.
[Brief description of the drawings]
FIG. 1 is an input of an NTSC television signal to which the present invention is applied, and an ITU-R BT. FIG. 2 is a diagram for explaining a main part of an analog / digital conversion apparatus that converts a digital video signal in a format conforming to 601 or 656;
FIG. 2 is a diagram illustrating a phase relationship among a color burst signal, a color signal, and color difference signals Cr and Cb.
FIG. 3 is a diagram for explaining the DTO unit and the SCH detection circuit part of FIG. 1 in more detail.
FIG. 4 is a diagram for explaining a standard of RS-170A.
FIG. 5 is a diagram illustrating an operation of a clock generation unit that generates from a horizontal synchronization signal.
FIG. 6 is a diagram for explaining a case where a deviation of a sampling point at the leading edge of H-SYNC is converted into an angle.
FIG. 7 is a diagram showing another embodiment of the present invention, which is a modification of the configuration shown in FIG. 1;
[Explanation of symbols]
101, 102 A / D converter
103 Y / C separator
104 Luminance signal processor
105 color signal selector
106 Color signal demodulator
107, 108 multiplier
109, 110 Low-pass filter
111 Phase difference detection, filter
112 DTO Department
113 sin / cos table
121 PLL OSC Department
122 Sync separator
123 0 _H Standard extraction unit
124 SCH detector
131 Sync separator from analog signal
132 Quasi-zero _H Reference sample and 0 _H Error (phase difference) detector with reference timing
133 arithmetic circuit
301 Adder
302 registers
303 registers
304 conversion table
501 0 _H Reference position (midpoint)

Claims (5)

An A / D converter for inputting an analog video signal and converting the analog video signal into a quantized digital signal including a synchronization portion and a video portion of the analog video signal;
A system clock signal generator for generating a system clock signal for sampling the 0 _H reference point of the horizontal synchronization component in the analog video signal or the vicinity of the 0 _H reference point;
A sin / cos table that outputs a sin / cos signal that is phase-coupled to the color burst portion of the color component signal extracted from the quantized video signal, and the signal output from the sin / cos table A digital color demodulator that receives the color component signal and demodulates the color,
A 0 _H reference extraction circuit unit for extracting a signal of timing associated with the 0 _H reference point;
An address information of the sin / cos table, an SCH measurement register that inputs a signal from the 0 _H reference extraction circuit unit and measures SCH;
A conversion table for converting the output signal of the SCH measurement register into phase angle data;
With
An SCH detection apparatus that extracts an output signal of the conversion table as SCH information. 2. The SCH detection apparatus according to claim 1, wherein the system clock signal is generated from a PLL using a synchronization component signal of the quantized digital signal as a reference. The SCH detection apparatus according to claim 1, wherein the system clock signal is not an integer multiple of a subcarrier signal frequency. 4. The SCH detection device according to claim 1, wherein the conversion table outputs a value that is 180 degrees different from an angle represented by a cos output signal of the sin / cos table. 5. An A / D converter for inputting an analog video signal and converting the analog video signal into a quantized digital signal including a synchronization portion and a video portion of the analog video signal;
A system clock signal generator for generating a system clock signal phase-locked to a horizontal synchronization component of the analog video signal;
And quasi 0 _H reference point extracting section for extracting a sample having 0 _H reference point or the 0 _H reference point since the quantized value of the horizontal synchronizing component included in the quantized digital signal as a quasi 0 _H reference point,
A phase difference output unit that calculates and outputs a phase from the sample of the extracted quasi 0 _H reference point to the 0 _H reference point;
A sin / cos table that outputs a sin / cos signal that is phase-coupled to the color burst portion of the color component signal extracted from the quantized video signal, and the signal output from the sin / cos table A digital color demodulation circuit unit that receives the color component signal and demodulates the color,
An SCH measurement register for inputting the address information of the sin / cos table and the output signal of the quasi 0 _H reference extraction means and measuring the SCH;
With
An SCH detection apparatus for analog video signals, wherein SCH information is generated based on outputs of the SCH measurement register and the phase difference output unit.

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