JP2006279300A - Circuit for detecting collar frame and video signal conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a detection circuit for detecting a collar frame that is stably in operation at a fast response. <P>SOLUTION: The detection circuit 12 for a collar frame includes: a burst control oscillation circuit 9 for generating a recovered subcarrier signal synchronously with a color burst signal in an input video signal; a synchronization recovery circuit 12 for counting number of horizontal scanning lines by four frames of the input video signal; a phase shift circuit 13 for generating a modulation subcarrier signal whose phase is shifted by each horizontal scanning line period from the recovered subcarrier signal according to the number of the horizontal scanning line and the frame information of four frames; and a subcarrier/horizontal synchronizing signal detection circuit 14 for detecting a relative phase between the modulation subcarrier signal and a horizontal synchronizing pulse signal. The synchronization recovery circuit 12 controls a phase shift amount of the modulation subcarrier signal in the phase shift circuit 13 on the basis of a plurality of detected relative phases. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a color frame detection circuit and a video signal conversion device, and more particularly to a video signal conversion device that converts a PAL analog composite video signal into a component serial digital signal and a color frame detection circuit used in the device.

  In equipment such as a broadcasting station, a PAL (Phase Alternation by Line) analog video signal (composite signal) may be converted into a component serial digital signal and used. In addition, component signals may be converted back to composite signals for use with existing analog equipment. As described above, when signal conversion is performed from composite signal → component signal → composite signal, image quality deterioration generally occurs.

  In the component conversion, Y / C separation is performed from the composite signal, and further demodulated to obtain a component signal that does not include a subcarrier signal. However, complete Y / C separation is difficult, and components that interfere with each other are mixed. There are two polarities of the subcarrier signal used when such a component signal is converted again into a PAL composite signal by the encoder, and there are cases where image quality does not deteriorate and image quality deteriorates. Since the component signal basically does not include color frame information for restoring the subcarrier signal, the polarity of the subcarrier signal used on the encoder side is indefinite. Furthermore, since the PAL system inverts the phase of the subcarrier that modulates one of the color signals for each scanning line, this information is also required.

  In SMPTE RP186 Video Index Information Coding for 525-and 625-Line Television Systems which defines the television system, a method of adding color frame information to a component signal is defined. The color frame information used when demodulating the PAL signal into the component signal is added to the component video signal in the auxiliary signal format defined by SMPTE RP186 and transmitted, and the color frame information is converted into the PAL composite signal again. It is possible to prevent deterioration in image quality by adjusting the polarity of the subcarriers. In SMPTE RP186, the color frame data is 4-bit information, which is a hexadecimal number, 0h is no information, 1h is color field 1, 2h is color field 2,..., 8h is color field 8, 9h to Fh. Is reserved. Also, the auxiliary signal relates to information indicating even / odd fields, PAL-specific V-axis polarity information used for color signal modulation, and SC / H related to the phases of the subcarrier (SC) and the horizontal synchronizing signal (H). It can be classified into three types of information. This auxiliary signal is transmitted once per field.

  A PAL color signal is composed of two components, a U-axis component and a V-axis component, and the V-axis component is modulated with a subcarrier whose phase is inverted every 1H (one horizontal period). The PAL pulse signal which is synchronization information whose polarity is inverted every 1H is used when encoding. Since one frame is an odd number of 625 lines, the PAL pulse signal repeats with a period of two frames.

  The number of scanning lines of the PAL signal handled here is 625 per frame. In the PAL signal, the relative phase relationship between the subcarrier (SC) and the horizontal synchronization signal is the same every 4 frames (625 lines × 4, 8 fields). In addition, the phase synchronization with the subcarriers, which are continuous sine waves in phase, coincides with the horizontal synchronization in a 4-frame cycle, and the phase is inverted every two frames. When observed on a specific line of 625 scanning lines, the PAL pulse matches every two frames, but the phase of the subcarrier is inverted. Information of the PAL pulse can be detected by a burst control oscillation (BCO, burst control oscillator) circuit for reproducing subcarriers from an input color burst.

  In a PAL color frame detection circuit that detects the order of color fields in a color frame from a composite video signal of such a PAL color television, only a specific line in one frame is simply observed. A circuit for detecting color frame information is disclosed in Patent Document 1.

  Further, as a related technique, Patent Document 2 relates to an improvement of a synchronization signal reproduction circuit for an NTSC system television signal, and the relative phase of the color burst and the synchronization signal is accurate, and the deviation from the time of the input synchronization component. A horizontal synchronizing signal reproducing circuit capable of reproducing a stable synchronizing signal is described.

  Furthermore, as a related technique, Patent Document 3 detects a phase error between a color reproduction carrier wave and a burst signal in a system in which a reference burst signal serving as a reference arrives with a phase shift for each line. A digital phase shifter is described in which when phase control of a color reproduction carrier wave is obtained, the phase of the carrier wave is accurately phased and phase comparison with the burst signal is performed to obtain accurate phase error detection and phase control. Yes. This digital phase shifter uses a cumulative integration type digital oscillator that generates a sawtooth wave digitally, and adds or subtracts an arbitrary digital signal to the output sawtooth wave to accurately shift the phase of the reproduced color carrier wave. ing.

JP 2000-152274 A Japanese Patent Laid-Open No. 5-22627 JP-A-5-308648

  By the way, in the signal transmitted from the relay destination, noise and waveform distortion are remarkably larger than those handled in the broadcasting station, and there are many fluctuations thereof. A device that handles such a signal requires a color frame detection circuit that operates stably against noise and waveform distortion. However, according to the technique described in Patent Document 1, it takes a long time to obtain an averaged output from the detection result of only a specific line, and there is a possibility that it may lack stability when a signal such as a relay is handled. there were.

  An object of the present invention is to provide a color frame detection circuit and a video signal conversion device that operate more stably and have a quick response.

  A color frame detection circuit according to one aspect of the present invention that achieves the above object includes a burst control oscillation circuit that generates a reproduction subcarrier signal synchronized with a color burst signal in an input video signal, and four frames of the input video signal. A synchronous reproduction circuit that counts frame information and horizontal scanning line number, and a phase shift that generates a modulated subcarrier signal whose phase is shifted every horizontal scanning line period from the reproduction subcarrier signal according to the horizontal scanning line number and frame information. And a subcarrier / horizontal synchronization detection circuit for detecting a relative phase between the modulation subcarrier signal and the horizontal synchronization pulse signal of the input video signal, and the synchronous reproduction circuit is based on temporal variation of the relative phase. The phase shift amount with respect to the modulated subcarrier signal in the phase shift circuit is controlled.

  In the color frame detection circuit of the first development form, the synchronous reproduction circuit may control the shift amount by changing the counting order of the horizontal scanning line numbers based on the temporal variation of the relative phase. .

  In the color frame detection circuit of the second development form, the subcarrier / horizontal synchronization detection circuit includes a first counter that counts the horizontal synchronization pulse signal within a predetermined phase range within one cycle of the modulation subcarrier signal, A second counter that counts horizontal synchronization pulses outside a predetermined phase range within one cycle of the carrier signal, and the synchronous reproduction circuit counts the predetermined number first of either the first or second counter The shift amount may be controlled based on whether or not it has been done.

  In the color frame detection circuit of the third development form, the size of the predetermined phase range is set smaller than the size outside the predetermined phase range, and the synchronous reproduction circuit includes a first counter and a second counter. When the predetermined number is counted earlier, the phase of the modulated subcarrier signal may be shifted by 180 degrees.

  In the color frame detection circuit of the fourth development form, the predetermined phase range may be determined from a value obtained by decoding a plurality of upper bits when the modulated subcarrier signal is represented by a digital value.

  In the color frame detection circuit of the fifth development form, the reproduction subcarrier signal is a sawtooth signal represented by a digital value, and the phase shift circuit uses the horizontal scanning line number and the frame information for four frames. The corresponding values may be added to or subtracted from the sawtooth signal, and the calculation result may be output as a modulated subcarrier signal.

  In the color frame detection circuit according to the sixth embodiment, the reproduction subcarrier signal is a sawtooth signal, and the burst control oscillation circuit includes a cumulative integration arithmetic circuit that generates the sawtooth signal, a color burst signal, and a sawtooth signal. And an adjustment circuit that multiplies the wavy signal and adjusts the generation period of the sawtooth signal based on the low-frequency component of the multiplication result.

  In the color frame detection circuit according to the seventh embodiment, the cumulative integration calculation circuit includes a calculation circuit that generates a sawtooth signal by adding a predetermined value for each reference clock, and a predetermined signal in one cycle of the sawtooth signal. And a plurality of correction counters that generate respective correction values at the clock interval, and the arithmetic circuit may add or subtract the correction values in the process of generating the sawtooth signal.

  According to the present invention, it is possible to realize a color frame detection circuit that operates more stably and has a quick response by detecting the relative phase of a color burst and a synchronization signal based on the detection results of a plurality of lines.

  The color frame detection circuit according to the embodiment of the present invention is a synchronous reproduction circuit (12 in FIG. 1) that counts frame information for one color frame (4 frames, 8 fields) period and 625 scanning line numbers (line numbers). ), A burst control oscillation circuit (9 in FIG. 1) that outputs a subcarrier signal synchronized with the input color burst signal, and a modulated subcarrier signal whose phase is shifted in accordance with the scanning line number and frame information for each horizontal period. Subcarrier / horizontal synchronization phase detection for determining the phase between the modulation subcarrier signal and the horizontal synchronization pulse by inputting the output phase shift circuit (13 in FIG. 1), the modulation subcarrier signal and the horizontal synchronization pulse. Circuit (14 in FIG. 1). The determination result of the subcarrier / horizontal synchronization phase detection circuit is fed back to the synchronization reproduction circuit. The subcarrier / horizontal synchronization phase detection circuit having such a configuration uses a modulated subcarrier signal and a reproduced PAL pulse in which the phase of a reproduced subcarrier that is a continuous wave is sequentially shifted every 1H, and only at a specific line number. It operates so as to obtain the subcarrier / horizontal synchronization phase detection result over the entire line, not the detection of. The synchronous reproduction circuit controls the phase shift amount with respect to the modulated subcarrier signal in the phase shift circuit based on the temporal variation of the relative phase of the subcarrier / horizontal synchronization. The color frame detection circuit configured as described above operates so as to average the detection result by majority decision, give the detection characteristic a hysteresis characteristic, and output color frame information.

  Such a color frame detection circuit is used in a video signal converter for converting a PAL composite signal into a component signal, and can detect color frame information stably and at high speed from an input video signal mixed with noise. Hereinafter, with reference to the drawings, a detailed description will be given in accordance with an embodiment.

  FIG. 1 is a block diagram showing a configuration of a video signal conversion apparatus according to an embodiment of the present invention. In FIG. 1, the video signal converter includes an A / D converter 2, a Y / C separation circuit 3, a decoder circuit 4, a formatter 5, a color frame addition (CF addition) circuit 6, a P / S circuit 7, and a burst control oscillation circuit. (BCO) 9, synchronization separation circuit 10, H-PLL circuit 11, synchronization reproduction circuit 12, phase shift circuit 13, and SC / H phase detection circuit 14. Then, the video signal converter converts the PAL analog signal supplied to the input terminal 1 into an SDI (serial digital interface) output signal and outputs it from the output terminal 8.

  The PAL analog signal supplied to the input terminal 1 is converted into a 10-bit parallel digital signal by the A / D converter 2 and separated into a luminance signal and a color signal by the Y / C separation circuit 3. The decoder circuit 4 inputs the color signal output from the Y / C separation circuit 3 and the signal output from the burst control oscillation circuit 9, and outputs a component signal not including a subcarrier to the formatter 5. The formatter 5 inputs the luminance signal output from the Y / C separation circuit 3 and the color signal output from the decoder circuit 4 and adds a color frame to the component parallel signal converted into a predetermined format such as adding a synchronization signal. Output to circuit 6. The color frame addition circuit 6 receives a signal indicating the 8-field sequence output from the synchronous reproduction circuit 12 and outputs it to the P / S circuit 7 as a predetermined auxiliary signal format. The P / S circuit 7 outputs a serial digital signal of 270 Mbps to the output terminal 8.

  Further, the PAL analog signal supplied to the input terminal 1 is also supplied to the sync separation circuit 10. The synchronization separation circuit 10 separates a composite synchronization signal (including horizontal synchronization and vertical synchronization) added to the video signal and supplies it to the H-PLL circuit 11. The H-PLL circuit 11 outputs a clock multiplied by 27 MHz with a period of 1/1728 of one horizontal synchronization signal period (1H), and supplies the clock to each unit. In addition to the horizontal synchronization pulse (H pulse), the H-PLL circuit 11 The synchronization information is also output to the synchronization reproduction circuit 12 together.

  Further, the 10-bit parallel digital signal output from the A / D converter 2 is also supplied to the burst control oscillation circuit 9. The burst control oscillation circuit 9 outputs a reproduction subcarrier signal to the decoder circuit 4 and the phase shift circuit 13 and outputs a PAL pulse generation signal to the synchronous reproduction circuit 12. The phase shift circuit 13 receives the phase control signal output from the synchronous reproduction circuit 12 and supplies the SC / H phase detection circuit 14 with a modulated subcarrier signal whose output phase is changed based on the phase control signal. The SC / H phase detection circuit 14 inputs the modulation subcarrier signal output from the phase shift circuit 13 and the comparison horizontal synchronization pulse output from the synchronous reproduction circuit 12, and receives the comparison horizontal synchronization pulse and the modulation subcarrier. Is detected, and a signal is sent to the synchronous reproduction circuit 12 when the phase is inverted. The synchronous reproduction circuit 12 receives signals output from the H-PLL circuit 11, the burst control oscillation circuit 9, and the SC / H phase detection circuit 14, and reproduces a synchronous signal having an 8-field period.

  Next, details of the burst control oscillation circuit 9 will be described. FIG. 2 is a block diagram showing a configuration of the burst control oscillation circuit. The frequency of the clock used for the circuit for generating the reproduction subcarrier is 27 MHz multiplied (1,728 times) based on the horizontal synchronizing signal (frequency 15.625 KHz). As a method for generating subcarriers (4.43361875 MHz) not having a simple integer ratio with respect to 27 MHz, for example, there is a clock frequency conversion method in Japanese Patent Application No. 10-279297.

  The burst control oscillation circuit 9 generates a subcarrier signal that changes in a sawtooth shape by accumulating unit addition values using a 27 MHz clock. The arithmetic circuit 63 and the latch 64 perform 16-bit cumulative addition, and the values that can be handled are in the range from 0 to 65535. Here, one period of 360 degrees of the sawtooth wave is calculated in correspondence with 65536. When the calculation result is 65536 (360 degrees) by discarding the carry of the arithmetic circuit 63, it is preferably 0 (0 degrees). The carry of the 16-bit arithmetic circuit 63 indicates the number of cycles, that is, indicates a phase of less than 360 degrees with 16 bits. In the PAL system, the 43MHz clock period of 27 MHz coincides with the subcarrier 709 and 379 cycle periods. The period common to both is a period of one frame of the video signal. The target cumulative addition value for one frame period is 709,379 cycles × 65,536 = 46,489,862,144. Accordingly, the unit addition value is 10761.54216, and includes a value after the decimal point that cannot be represented by 16 bits. Therefore, the cumulative addition is performed using the approximate value. The error can be corrected by temporarily changing the unit added value, but if it is performed all at once, jitter is generated, and thus it is dispersed. When the unit addition value 10762 is repeatedly added, the frequency becomes close to the subcarrier frequency, but deviates from the accurate frequency. Here, four corrections are performed as a method of correcting this deviation. The first correction is once every two clocks, the unit addition value is -1, the second correction is once every 24 clocks, +1, the third correction is once every 2015 clocks, +1, and the fourth correction is 2 +1 once every 160,000 clocks. By the correction counters 67, 68, 69, and 70 that perform the first to fourth corrections, the correction value generation circuit 65 generates a signal that disperses the error and outputs the signal to the arithmetic circuit 63. The common period counter 66 counts the 27 MHz clock supplied to the input terminal 52 by 4,320,000, and supplies it as a signal for resetting the correction counters 67, 68, 69, and 70. The correction counters 67, 68, 69 and 70 are also supplied with a 27 MHz clock.

  By configuring the burst control oscillation circuit 9 as described above, a sawtooth signal having a subcarrier frequency with little jitter is generated. However, this alone is not a subcarrier signal synchronized in phase with the input color burst signal. In order to generate a subcarrier signal synchronized in phase with the color burst signal, the output of the latch 64 is converted into a sinusoidal signal by the Sin ROM 57 and supplied to a multiplier (MPY) 58. The parallel digital signal supplied to the input terminal 51 is supplied to a multiplier (MPY) 58 through a band pass filter (BPF) 56 that passes a color burst signal component. Multiplier (MPY) 58 multiplies the output signal of SinROM 57 and the output signal of bandpass filter 56 and outputs the result to lowpass filter (LPF) 59. The output of the low-pass filter (LPF) 59 is a signal that changes according to the phase difference. In PAL, the phase is different by 90 degrees every 1H (1 horizontal synchronization), and when 2H is averaged, a constant value is obtained. The 2H averaging circuit 61 outputs an average value of 2H phase error in accordance with the burst flag supplied to the input terminal 71, and is temporarily supplied to the arithmetic circuit 63 via the switch 62, and converges to a predetermined phase. It has a loop configuration. By adopting such a loop configuration, a sawtooth reproduction subcarrier signal synchronized in phase with the input color burst signal is obtained from the latch 64.

  The signal supplied to the output terminal 54 is a 16-bit signal used by the decoder circuit 4 for demodulating the color signal. The signal supplied to the output terminal 53 is the same signal as the signal supplied to the phase shift circuit 13.

On the other hand, the slicing circuit 60 compares the output signal of the low-pass filter (LPF) 59 with a predetermined value, and outputs a 2H-cycle signal to the output terminal 55 during a period with a color burst. A signal output from the output terminal 55 corresponds to a PAL pulse generation signal supplied to the synchronous reproduction circuit 12. Since 360 degrees is calculated as 2 ¹⁶ as the sawtooth subcarrier signal, the slicing circuit 60 adds a fixed value to the sawtooth subcarrier signal and discards the carry carry to obtain a fixed value. Correspondingly, a signal out of phase can be easily created. Shifting the phase in this way is difficult with analog technology, but easy with digital technology.

  Next, details of the synchronous reproduction circuit 12, the phase shift circuit 13, and the SC / H phase detection circuit 14 will be described. FIG. 3 is a block diagram showing the configuration of the synchronous reproduction circuit, the phase shift circuit, and the SC / H phase detection circuit. 3, the PALFF 38, the comparison circuit 39, the 1Fr counter circuit 40, the 2 frame enable pulse circuit (2FrEN) 41, and the 4Fr pulse counter 42 constitute the synchronous reproduction circuit 12 of FIG. Also, an adder circuit 43, a selector 44, and a multiplier circuit 45. The phase shift operation circuit 29 corresponds to the phase shift circuit 13 of FIG. Further, the SC / H center adjustment circuit 30, the decoder (SCDEC) 32, the inverting circuit (inverter) 33, the NG counter 34, the OK counter 35, and the OR circuit 36 constitute the SC / H phase detection circuit 14 of FIG.

  The H pulse supplied from the H-PLL circuit 11 to the input terminal 23 and the frame period pulse supplied to the input terminal 22 are supplied to the 1Fr counter circuit 40. The 1Fr counter circuit 40 is a 10-bit counter that counts 0 to 624 corresponding to a line number for one frame, and is an odd field related to the interlaced scanning of the counter values LN9 to LN0 and 625 line periods. / A pulse indicating an even field is output to the output terminal 28.

  The PALFF 38 is a flip-flop that inverts in response to the H pulse, is reset by a PAL pulse generation signal supplied from the synchronous reproduction circuit 12 to the input terminal 24, and outputs a symmetrical rectangular wave PAL pulse having a 2H period. The comparison circuit 39 determines whether the least significant bit LN0 of the output of the 1Fr counter circuit 40 matches the 2H cycle signal output from the PALFF 38, and outputs a 1 bit 2 frame cycle signal. The 2-frame enable pulse circuit (2FrEN) 41 inputs the signal output from the comparison circuit 39 and the signal output from the 1Fr counter circuit 40, and outputs a 1H-width pulse in the frame period. The 4Fr pulse counter 42 is a 1-bit counter that is inverted according to the output of the 2-frame enable pulse circuit (2FrEN) 41, and outputs a pulse of a 4-frame period. When the signal from the NG counter 34 is input, the 4Fr pulse counter 42 outputs an inverted signal regardless of the 2-frame pulse signal output from the 2-frame enable pulse circuit (2FrEN) 41. .

  Next, a description will be given of a portion for controlling the phase shift operation circuit 29 to obtain a modulated subcarrier having a constant phase when observed with a delayed H pulse. The multiplication circuit 45 multiplies the signal indicating the line number (0 to 624) output from the 1Fr counter circuit 40 and the fixed value 105 and outputs the result to the phase shift operation circuit 29. At this time, the output value of the multiplication circuit 45 is 0 to 65520. The output of the multiplication circuit 45 is a signal for shifting the reproduction subcarrier by about 0.58 degrees for each line and 360 degrees for one frame. The multiplication circuit 45 is a circuit that performs multiplication with 625 fixed values, and may be realized by using a table by ROM (read only memory).

The 2-bit adder circuit 43 adds and outputs the lower 2 bits of signals LN0 and LN1 output from the 1Fr counter circuit 40 and the other 2-bit signal. The other signal is a 2-bit signal in which the signal output from the 4Fr pulse counter 42 is the upper bit and the signal of the 2-frame period output from the comparison circuit 39 is the lower bit. The selector 44 is 0.75 × 2 ¹⁶ , 0.5 × 2 ¹⁶ corresponding to 270 degrees, 180 degrees, 90 degrees, and 0 degrees, respectively, according to the four signals output from the 2-bit addition circuit 43. , 0.25 × 2 ¹⁶ , and 0 are selected and a signal is output to the phase shift operation circuit 29.

  The phase shift operation circuit 29 inputs a 16-bit sawtooth reproduced subcarrier signal supplied from the output terminal 54 of FIG. 2 to the input terminal 21. Then, by adding or subtracting the 16-bit phase shift control signal output from the selector 44 in increments of 90 degrees and the 16-bit phase shift control signal output from the multiplication circuit 45 that changes over one frame. The reproduction subcarrier signal whose phase changes for each line is converted into a modulated subcarrier signal having a constant phase, and is output to the SC / H center adjustment circuit 30.

  The SC / H center adjustment circuit 30 gives a predetermined fixed phase change to the modulated subcarrier signal output from the phase shift operation circuit 29, and extracts and outputs a signal for the upper 8 bits from the 16-bit signal. . The decoder 32 decodes the upper 2 bits of the signal output from the SC / H center adjustment circuit 30, and outputs a signal having an average duty ratio of 1/4 by dividing 360 degrees into four. The signal output from the decoder 32 is supplied as a count enable for the NG counter 34 and also supplied as a count enable for the OK counter 35 via the inversion circuit 33.

  On the other hand, the H pulse supplied to the input terminal 23 is supplied as a clock for counting to the NG counter 34 and the OK counter 35 through the delay circuit 46. In response to the delayed H pulse, the count value of one of the NG counter 34 and the OKG counter 35 that is enabled for counting increases. Any one of the counters enabled to count outputs a carry when the count value reaches, for example, the maximum value of 15. The output carry resets the NG counter 34 and the OK counter 35 through the OR circuit 36. Here, when the phase of the modulated subcarrier signal has been inverted, the carry of the NG counter 34 comes out first before being reset. This carry signal is sent to the 4Fr pulse counter 42 to invert the output polarity of the 4Fr pulse counter 42. When the output polarity of the 4Fr pulse counter 42 is inverted, the output of the adder circuit 43 is added by 2 and the phase selected by the selector 44 changes by 180 degrees. As a result, the phase shift operation circuit 29 operates so as to generate a modulated subcarrier in which only the OK counter 35 is increased by shifting the phase of the reproduced subcarrier signal by 180 degrees by the outputs of the selector 44 and the multiplier circuit 45.

  FIG. 4 is a diagram schematically showing the phase relationship between the modulation subcarrier and the delayed H pulse. The vertical axis represents the amplitude of the modulation subcarrier (corresponding to the output of the SC / H center adjustment circuit 30), and the horizontal axis represents time. The horizontal axis indicates the position of the delayed H pulse. Further, a region (OK) where the OK counter 35 increases and a region (NG) where the NG counter 34 increases are shown with respect to the relative phases of the modulation subcarrier and the delayed H pulse. As shown in FIG. 4A, when the delayed H pulse is H1, only the OK counter 35 performs the count, and the NG counter 34 is stopped. If the relative phase changes from H1 to H2 for some reason such as noise, only the NG counter 34 increases. When the state of the phase of H2 continues, the NG counter 34 issues a carry and the output of the 4Fr pulse counter 42 is inverted. As a result, the phase of the modulation subcarrier is inverted, and the phase relationship shown in FIG. The area (OK) of the OK counter 35 is wider than the area (NG) of the NG counter 34, and the previous state is maintained in the phase state between H1 and H2. That is, two of the four regions are determined, and the remaining two become regions that have been determined in the past, and an operation with hysteresis is performed. Here, for example, assuming that detection is performed in two divisions, the operation has no hysteresis. In this case, at the intermediate phase, the SC / H detection result frequently undergoes unnecessary inversion due to slight jitter, and the operation becomes unstable. Note that the grid in FIG. 4 represents a scale obtained by dividing 360 degrees into four parts, not 27 MHz clock intervals. The number of clocks of 27 MHz for one cycle period of the subcarrier signal is about 6.09. Therefore, although it is expressed as a scale divided into four on average, the division position is instantaneously changed by the 27 MHz clock.

  By the way, the number of subcarrier cycles in the 1H period of the PAL system is 283.7516 cycles. Focusing on the decimal part, if the phase of the subcarrier is shifted by about 270 degrees and about 0.58 degrees every 1H, it coincides with the H period. The delay circuit 46 shifts the timing so that the OK counter 35 and the NG counter 34 count after the 1Fr counter circuit 40 changes.

  Note that the adder circuit 43 and the selector 44 can be replaced with a ROM having 4 bits of input bits. If SC / H is detected in the 2H cycle, the phase shift signal output from the selector 44 may be two, 0 degree and 180 degrees, and the adder circuit 43 may be 1 bit. However, it is necessary to add a circuit for narrowing the 2H width pulse to the 1H width pulse between the carry output of the NG counter 34 and the 4Fr pulse counter 42. Further, although the number of bits of the phase shift operation circuit 29 is 16 bits, the number of bits can be significantly reduced if accuracy is not required. For example, in the case of 7 bits, 360 degrees is divided into 128, and the error corresponds to 2.8 degrees, but the accuracy of SC / H detection is sufficient. Further, the SC / H center adjustment circuit 30 is not necessarily provided if the phase of the reproduction subcarrier is in an appropriate relationship.

  The SC / H detection circuit according to FIG. 3 generates a modulated subcarrier that always has a constant phase at the timing of H, and detects SC / H. From the delay circuit 46 before the phase shift operation circuit 29, the SC / H detection circuit shown in FIG. There is also a method of slowing down the calculation speed by adding a circuit that latches the reproduction subcarrier using the output signal as a clock. By slowing down, the amount of subsequent processing can be reduced.

  Further, the number of counts until the OK counter 35 and the NG counter 34 carry out may be set as necessary. The number of counts until the carry is issued may be set to 8, for example. When the count number is 8, when the input signal is switched to another color frame signal, at least 8H is waited. Even if it is affected by noise mixed in the input signal, false detection is reduced by waiting for at least 8H. Further, the count value until the carry is generated may be set to 31 for the NG counter, 7 for the OK counter, etc. in order to make it less susceptible to noise. By making the count value in this way, the carry of the OK counter comes out first in the situation where any one counts at half the frequency, making it difficult to invert SC / H. However, the response to switching to the inverted SC / H is delayed. It is preferable to set a count value until a carry occurs as necessary.

  Incidentally, the monitor latch 31 outputs an SC / H monitor signal to the output terminal 25. For example, a PAL signal supplied from a signal source with accurate SC / H is connected to the input of the apparatus (input terminal 1 in FIG. 1), and the phase is fixedly shifted by the SC / H center adjustment circuit 30 and output. The output signal of the terminal 25 can be adjusted while monitoring so as to be a predetermined value, for example, a value in the vicinity of 96 (as shown in FIG. 4). In this case, the signal at the output terminal 25 is an 8-bit signal. However, for example, a comparison circuit indicating whether it is within the range of 96 ± 4 in decimal is added to obtain a 1-bit signal as an output. You may make it do.

FIG. 5 is a diagram illustrating signal values of the respective units in FIG. 3 over a period of four frames. Each column in FIG. 5 will be described. (1) The row number in the column represents the distinction for explanation of the figure, and the video frame transitions between row numbers 8 and 9, 16 and 17, 24 and 25, and 32 and 1, respectively. Indicates. Note that line numbers 6, 14, 22, and 30 have information for 618 lines, but are not shown. The column (2) shows the output signal of the 4Fr pulse counter 42. (3) The column shows the PAL pulse that is the output of the PALFF 38. The column (4) shows the output of the comparison circuit 39, that is, the 2-frame pulse that is the comparison result between the PAL pulse and LN0. The column (5) indicates the 10-bit output signal of the 1Fr counter circuit 40 in decimal. That is, the line number LN is indicated by 0 to 624. The column (6) indicates the lower 2 bits LN1 and LN0 of the 1Fr counter circuit 40. The column (7) shows the 2-bit output of the adder circuit 43, that is, the control input of the selector 44 in decimal. The column (8) indicates the output of the selector 44 by the angle of the subcarrier to be phase shifted. The subcarriers are phase-shifted by 0, 270, 280, 90 degrees corresponding to the case where the 2-bit output of the adder circuit 43 is 0, 1, 2, 3, respectively. The column (9) indicates the output of the multiplication circuit 45 by the angle of the subcarrier to be phase shifted. That is, (a fixed value 105) × (line number LN) × ^{360/2 16} is shown at an angle.

In FIG. 5, taking the line number 11 as an example, the output signal of the 4Fr pulse counter 42 is 0,
Since the 2 frame pulse is 1, LN1 = 1 and LN0 = 0, the output of the adder circuit 43 is 1 + 2 = 3. Correspondingly, the angle at which the subcarrier is phase shifted is 90 degrees. Further, since the line number is 2, the subcarriers are phase-shifted by 105 × 2 × 360/2 ¹⁶ = 1.15 degrees, and the total phase shift angle is 91.15 degrees.

  In FIG. 5, when the NG counter 34 carries out a carry, the output of the 4Fr pulse counter 42 is inverted. Thereby, for example, the state of the 1st to 8th rows changes to the state of the 17th to 24th rows, and even if the line numbers are the same, the value of the column (8) indicates that the value is shifted by 180 degrees.

  The color frame detection circuit generates a modulated subcarrier signal that always has a constant phase when observed at the H timing. Then, the modulation subcarrier signal is generated by being divided into two types of change in units of 90 degrees and change over 625 lines. The phase shift in units of 90 degrees makes a round with 4H period, and the relationship between 4H and one frame is 625/4 = 156.25. Of the 10 bits of one frame counter, only the lower 2 bits are used and the upper 8 bits are not used. In the 0.25 cycle after the decimal point, a signal that continuously changes in 90 units over 4 frames is generated by combining the information of the 2 frame period pulse and the information of the 4 frame period. In this way, only the lower 2 bits of the 10 bits of one frame counter are used.

  As described above, the SC / H phase detection circuit 14 performs the averaging process using the contention counter circuit including the OK counter 35 and the NG counter 34. And it is set as the structure which gave the hysteresis by making it the loop structure which feeds back the result to the 4Fr pulse generation circuit 42. FIG.

  The color frame detection circuit including the SC / H phase detection circuit 14 configured as described above does not detect SC / H using only information on a specific line, but detects SC / H over all lines. Therefore, it is possible to operate more stably against noise contamination by providing hysteresis characteristics at the boundary of phase detection and using a plurality of detection results.

It is a block diagram which shows the structure of the video signal converter concerning the Example of this invention. It is a block diagram which shows the structure of a burst control oscillation circuit. It is a block diagram which shows the structure of a synchronous reproduction circuit, a phase shift circuit, and an SC / H phase detection circuit. It is a figure which shows typically the phase relationship of a modulation | alteration subcarrier and a delay H pulse. It is a figure which shows the value of the signal of each part over 4 frame periods.

Explanation of symbols

1, 2, 22, 23, 24, 51, 52, 71 Input terminal 2 A / D converter 3 Y / C separation circuit 4 Decoder circuit 5 Formatter 6 Color frame addition circuit 7 P / S circuits 8, 25, 26, 27 , 28, 53, 54, 55 Output terminal 9 Burst control oscillation circuit 10 Sync separation circuit 11 H-PLL circuit 12 Synchronous reproduction circuit 13 Phase shift circuit 14 SC / H phase detection circuit 29 Phase shift operation circuit 30 SC / H center adjustment Circuit 31 Monitor latch 32 Decoder 33 Inversion circuit 34 NG counter 35 OK counter 36 OR circuit 38 PALFF
39 Comparison circuit 40 1Fr counter circuit 41 2 frame enable pulse circuit (2FrEN)
42 4Fr pulse counter 43 Adder circuit 44 Selector 45 Multiplier circuit 46 Delay circuit 56 Band pass filter (BPF)
57 SinROM
58 Multiplier (MPY)
59 Low-pass filter (LPF)
60 slice circuit 61 2H averaging circuit 62 switch 63 arithmetic circuit 64 latch 65 correction value generation circuit 66 common period counter 67, 68, 69, 70 correction counter

Claims (9)

A burst control oscillation circuit for generating a reproduction subcarrier signal synchronized with the color burst signal in the input video signal;
A synchronous reproduction circuit for counting frame information and horizontal scanning line number for four frames of the input video signal;
In accordance with the horizontal scanning line number and the frame information, a phase shift circuit that generates a modulated subcarrier signal with a phase shifted for each horizontal scanning line period from the reproduction subcarrier signal;
A subcarrier / horizontal synchronization detection circuit for detecting a relative phase between the modulated subcarrier signal and a horizontal synchronization pulse signal of the input video signal;
With
The color frame detection circuit, wherein the synchronous reproduction circuit controls a phase shift amount with respect to the modulation subcarrier signal in the phase shift circuit based on a temporal variation of the relative phase.   2. The color frame detection according to claim 1, wherein the synchronous reproduction circuit controls the shift amount by changing a counting order of the horizontal scanning line numbers based on a temporal variation of the relative phase. circuit. The subcarrier / horizontal synchronization detection circuit includes:
A first counter that counts the horizontal synchronization pulse signal in a predetermined phase range within one period of the modulated subcarrier signal;
A second counter that counts the horizontal sync pulse outside the predetermined phase range within one period of the modulated subcarrier signal;
Including
2. The color frame detection circuit according to claim 1, wherein the synchronous reproduction circuit controls the shift amount based on whether one of the first and second counters has previously counted a predetermined number.   The size of the predetermined phase range is set to be smaller than the size outside the predetermined phase range, and the synchronous reproduction circuit is configured such that the first counter sets the predetermined number before the second counter. 4. The color frame detection circuit according to claim 3, wherein, when counted, the phase of the modulated subcarrier signal is shifted by 180 degrees.   5. The color frame detection circuit according to claim 3, wherein the predetermined phase range is determined from a value obtained by decoding a plurality of high-order bits when the modulated subcarrier signal is represented by a digital value. The reproduction subcarrier signal is a sawtooth signal represented by a digital value,
The phase shift circuit adds or subtracts a value corresponding to each of the horizontal scanning line number and the frame information for the four frames to the sawtooth signal and outputs a calculation result as the modulation subcarrier signal. The color frame detection circuit according to claim 1. The reproduction subcarrier signal is a sawtooth signal,
The burst control oscillation circuit includes:
A cumulative integration arithmetic circuit for generating the sawtooth signal;
An adjustment circuit that multiplies the color burst signal and the sawtooth signal and adjusts the generation period of the sawtooth signal based on a low frequency component of the multiplication result;
The color frame detection circuit according to claim 1, further comprising: The cumulative integration calculation circuit includes:
An arithmetic circuit for generating a sawtooth signal by adding a predetermined value for each reference clock;
A plurality of correction counters for generating respective correction values at respective predetermined clock intervals in one period of the sawtooth signal;
With
8. The color frame detection circuit according to claim 7, wherein the arithmetic circuit adds or subtracts the correction value in the generation process of the sawtooth signal.   9. A video signal conversion comprising the color frame detection circuit according to claim 1, wherein the PAL analog composite video signal is converted into a component serial digital signal using the frame information for the four frames. apparatus.

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