CN1842167A - Color frame detection circuit and image signal conversion device - Google Patents
Color frame detection circuit and image signal conversion device Download PDFInfo
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- CN1842167A CN1842167A CN 200610058480 CN200610058480A CN1842167A CN 1842167 A CN1842167 A CN 1842167A CN 200610058480 CN200610058480 CN 200610058480 CN 200610058480 A CN200610058480 A CN 200610058480A CN 1842167 A CN1842167 A CN 1842167A
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Abstract
This invention provides a detection circuit for detecting a collar frame that is stably in operation at a fast response. The detection circuit for a collar frame includes: a burst control oscillation circuit for generating a recovered subcarrier signal synchronously with a color burst signal in an input video signal; a synchronization recovery circuit for counting number of horizontal scanning lines by four frames of the input video signal; a phase shift circuit for generating a modulation subcarrier signal whose phase is shifted by each horizontal scanning line period from the recovered subcarrier signal according to the number of the horizontal scanning line and the frame information of four frames; and a subcarrier/horizontal synchronizing signal detection circuit for detecting a relative phase between the modulation subcarrier signal and a horizontal synchronizing pulse signal. The synchronization recovery circuit controls a phase shift amount of the modulation subcarrier signal in the phase shift circuit on the basis of a plurality of detected relative phases.
Description
Technical field
The present invention relates to color frame detection circuit and image signal conversion device, relate in particular to PAL analog composite picture signal is converted to employed color frame detection circuit in the image signal conversion device of component serial digital signal and this device.
Background technology
In playing equipment such as station, with PAL (Phase Alternation by Line; Line-by-line inversion) analog picture signal (composite signal) is converted to the component serial digital signal and uses.In addition, in order in existing analog machine, to use, component signal is reverted to composite signal once more.Like this, carried out the conversion of signals of composite signal → component signal → composite signal after, picture element can take place usually to be worsened.
In the component conversion, carry out Y/C from composite signal and separate, carry out demodulation again, thereby do not comprised the component signal of subcarrier signal.But Y/C separation completely is very difficult, so mix the composition that mutual interference is arranged.The polarity of employed subcarrier signal had two when such component signal was the PAL composite signal by coder transitions once more, when therefore having picture element not worsen, when also having picture element to worsen.In addition, owing to do not comprise basically not being used for subcarrier signal restored and be the color framing information of component signal, so uncertain in the polarity of the subcarrier signal of encoder one side use.In addition, the PAL mode is the phase place that counter-rotating is used to modulate the subcarrier signal of a carrier chrominance signal to each scan line, so this information also is essential.
In the SMPTE RP 186 Video Index Information Codingfor 525-and 625-Line Television Systems that stipulated TV mode, stipulated the method for additional color framing information in component signal.Employed color framing information appended in the component image signal with the form of the auxiliary signal of regulation among the SMPTE RP 186 and transmits when the PAL signal was demodulated into component signal, and it is converted to the PAL composite signal once more, at this moment, owing to using color framing information to make the polarity of subcarrier signal unified, worsen so can not cause picture element.In SMPTE RP 186, the color framing data are 4 information, and 16 systems, 0h represent there is not information, and 1h represents color field 1, and 2h represents color field 2 ..., 8h represents color field 8,9h～Fh is preestablished.In addition, auxiliary signal can be divided three classes, one class is the information of expression even/odd field, and a class is the polarity information that carrier chrominance signal is modulated the distinctive V axle of employed PAL, and another kind of is information about the SC/H related with subcarrier (SC) and horizontal-drive signal (H).This auxiliary signal transmits once by each.
The carrier chrominance signal of PAL mode is become to be grouped into the V axle by U axle composition, and wherein, V axle composition is by modulating by the subcarrier of every 1H inverted phase.By the synchronizing information of every 1H reversed polarity, promptly the PAL pulse signal uses when coding.Because a frame has 625 row, is odd number, so the PAL pulse signal is to repeat in the cycle with two frames.
Here the scan line quantity of the PAL signal of Chu Liing is 625 of each frames.In the PAL signal, the subcarrier (SC) of per 4 frames (* 4,8 of 625 row) and the relative phase relation of horizontal-drive signal are consistent.In addition, be the cycle with 4 frames, be consistent as the subcarrier of the also continuous sine wave of phase place and the relation of horizontal synchronization, and carry out phasing back according to per two frames.If observe, then every the PAL of two frames pulse unanimity and the phasing back of subcarrier at the particular row of 625 scan lines.PAL pulse can vibrate by burst control (BCO, burst control operator; The burst control operator) electric circuit inspection information, described burst control oscillation circuit are used for reproducing subcarrier from the colored burst of input.
The PAL mode color frame detection circuit that detects the color field sequence in its color framing a kind of composite picture signal of the color TV from such PAL mode is disclosed in patent documentation JP-2000-152274A, in this circuit, only observe the particular row in the frame come the sense colors frame information simply.
In addition, as the technology that is associated, in patent documentation JP-H5-22627A, record a kind of horizontal-drive signal reproducing circuit, this circuit relates to the improvement of the synchronizing signal reproducing circuit of NTSC mode TV signal, make that the relative phase of colored burst and synchronizing signal is correct, even and for also obtaining stable synchronizing signal from the moment of importing synchronous composition situation devious.
In addition, as corresponding technology, in patent documentation JP-H5-308648A, record a kind of digital phase shifter, thereby carry out in the system of phase shift arrival at each row at reference burst as benchmark, if detect the phase error that colourity is reproduced carrier wave and burst, thereby obtain the phase control that colourity is reproduced carrier wave, the correct phase shift of phase place that then described phase shifter can make described carrier wave, and carry out bit comparison mutually, thereby obtain correct phase error detection and phase control with described burst.This digital phase shifter uses the cumulative integral type digital oscillator that digitally produces sawtooth waveforms, and carries out plus and minus calculation by the sawtooth waveforms with Any Digit signal and this output and make and reproduce chrominance carrier by correctly phase shift.
Yet, compare with the signal of processing in playing the station, the signal that sends from the transfer destination etc., noise or wave distortion are very big, and its fluctuation is also many.In handling the equipment of such signal, need at noise and wave distortion still can steady operation color frame detection circuit.But, if the technology of being put down in writing among the sampling patent documentation JP-2000-152274A, then need for a long time, and when handling the signal of transfer etc., lack and stablize from the output that only obtains equalization for the testing result of particular row.
Summary of the invention
The object of the present invention is to provide a kind of more operating stably and respond color frame detection circuit and image signal conversion device rapidly.
In order to reach above-mentioned purpose, a kind of color frame detection circuit of the present invention, it comprises: burst control oscillation circuit is used for generating the reproduction subcarrier signal synchronous with the colored burst of received image signal; The reproduced in synchronization circuit is used for the frame information and the horizontal scanning line numbering of the amount of four frames of received image signal are counted; Phase-shift circuit is used for according to horizontal scanning line numbering and frame information, from reproducing the subcarrier signal modulating subcarrier signal of phase place that has been created on each horizontal scanning line period migration; Subcarrier/horizontal synchronization testing circuit is used to detect the relative phase between the horizontal synchronization pulse signal of modulating subcarrier signal and received image signal; Wherein, the reproduced in synchronization circuit comes the side-play amount with respect to the phase place of modulating subcarrier signal in the control phase-shift circuit based on relative phase change in time.
Other execution modes according to the present invention, the reproduced in synchronization circuit based on relative phase in time change and control side-play amount by the counting sequence that changes the horizontal scanning line numbering.
According to other execution modes of the present invention, subcarrier/horizontal synchronization testing circuit comprises: first counter is used in the predetermined phase scope in the one-period of modulating subcarrier signal the horizontal synchronization pulse signal being counted; With second counter, be used for outside the predetermined phase scope in the one-period of modulating subcarrier signal horizontal synchronization pulse being counted; Wherein, the reproduced in synchronization circuit is according to which count down to predetermined number earlier and controls side-play amount in first and second counters.
According to other execution modes of the present invention, the size of predetermined phase scope is set for less than the outer size of predetermined phase range; When the reproduced in synchronization circuit count down to predetermined number at first counter earlier than second counter, make phase deviation 180 degree of modulating subcarrier signal.
According to other execution modes of the present invention, according to the phase range of the value of the multidigit gained of the high position of modulating subcarrier signal decoding when representing with digital value being determined be scheduled to.
According to other execution modes of the present invention, reproducing subcarrier signal is the wavy signal of being represented by digital value of sawtooth; Phase-shift circuit adds or deducts respectively the corresponding value of frame information with the amount of horizontal scanning line numbering and four frames to the wavy signal of sawtooth, and operation result is exported as the modulating subcarrier signal.
According to other execution modes of the present invention, reproducing subcarrier signal is the wavy signal of sawtooth, and burst control oscillation circuit comprises: the cumulative integral computing circuit is used to produce the wavy signal of sawtooth; And regulating circuit, be used for colored burst and the wavy signal of sawtooth are carried out multiplying, and regulate the generation cycle of the wavy signal of sawtooth based on the low-frequency component of multiplication result.
According to other execution modes of the present invention, the cumulative integral computing circuit comprises: computing circuit is used for adding predetermined value at each reference clock, to generate the wavy signal of sawtooth; With a plurality of correction counters, be used in the one-period of the wavy signal of sawtooth, generate separately correction value at interval in separately predetermined clock; Wherein, computing circuit carries out the plus and minus calculation of correction value in the generative process of the wavy signal of sawtooth.
According to the present invention, improve the detection of carrying out colored burst and the relative phase of synchronizing signal based on the testing result of multirow, can realize more operating stably and respond fast color frame detection circuit.
Description of drawings
Fig. 1 is the block diagram of the image signal conversion device of one embodiment of the invention;
Fig. 2 is the block diagram of burst control oscillation circuit;
Fig. 3 is the block diagram of reproduced in synchronization circuit, phase-shift circuit and SC/H phase detecting circuit;
Fig. 4 a is the schematic diagram of the phase relation of demodulation subcarrier and delay H pulse;
Fig. 4 b is the schematic diagram of the phase relation of demodulation subcarrier and delay H pulse;
Fig. 5 is the figure of value of each signal of 4 image durations of expression.
Embodiment
Fig. 1 is the block diagram of the image signal conversion device that contains color frame detection circuit of one embodiment of the invention.As shown in Figure 1, image signal conversion device is used for the PAL composite signal is converted to component signal, comprising A/D converter 2, y/c separation circuit 3, decoding circuit 4, formatter 5, color framing additional (CF is additional) circuit 6, P/S circuit 7, burst control oscillation circuit (BCO) 9, synchronizing separator circuit 10, H-PLL circuit 11, reproduced in synchronization circuit 12, phase-shift circuit 13 and SC/H (subcarrier/horizontal synchronization) phase detecting circuit 14.The PAL analog signal conversion that image signal conversion device will offer input terminal 1 is SDI (serial digital interface) output signal and from lead-out terminal 8 outputs.
Herein, reproduced in synchronization circuit 12, burst control oscillation circuit 9, phase-shift circuit 13 and SC/H phase detecting circuit 14 have constituted color frame detection circuit.The frame information of the amount during 12 pairs one color framings of reproduced in synchronization circuit (4 frames, 8 frames) and 625 horizontal scanning line numberings (line number) are counted.Burst control oscillation circuit 9 outputs and the synchronous reproduction subcarrier signal of input color burst.Phase-shift circuit 13 is offset phase place according to scan line numbering and frame information from reproducing subcarrier signal at each horizontal cycle, and the modulating subcarrier signal of output gained.SC/H phase detecting circuit 14 input modulating subcarrier signal and horizontal synchronization pulses are judged the phase place between modulating subcarrier signal and the horizontal synchronization pulse then, and result of determination are fed back to reproduced in synchronization circuit 12.The SC/H testing circuit 14 of this spline structure use in every 1H will be offset in turn as the phase place of the reproduction carrier wave of continuous wave and modulated carrier signal and reproduce the PAL pulse and move, thereby obtain the SC/H testing result of all row, and just the particular row numbering is not detected.Reproduced in synchronization circuit 12 comes with respect to the phase pushing figure of controlling the modulation wave signal in the phase-shift circuit 13 based on the relative phase change in time of SC/H.The following work of the color frame detection circuit of Gou Chenging like this: by result average of majority decision, make to detect in the characteristic to have hysteresis to detecting, and output color framing information.
Such color frame detection circuit can be stablized from the received image signal of having sneaked into noise and detect color framing information apace.
Describe the each several part of Fig. 1 below in detail.
The PAL analog signal that is provided for input terminal 1 is converted into 10 parallel-by-bit digital signals in A/D converter 2, and is separated into luminance signal and carrier chrominance signal in y/c separation circuit 3.Decoding circuit 4 inputs will not comprise then that from the carrier chrominance signal of y/c separation circuit 3 outputs and the signal of exporting from burst control oscillation circuit 9 (having removed the carrier chrominance signal of Y composition from composite picture signal) component signal of subcarrier is exported to formatter 5.Formatter 5 input is from the luminance signal of y/c separation circuit 3 outputs with from the carrier chrominance signal (having removed the carrier chrominance signal of Y composition from composite picture signal) of decoding circuit 4 outputs, and the component parallel signal that will be converted to predetermined format such as appended synchronization signal is then exported to color framing adjunct circuit 6.Color framing adjunct circuit 6 input is from the signal of 8 sequences of expression of reproduced in synchronization circuit 12 outputs, and the form (for example, SMPTE RP 186) that is predetermined auxiliary signal is then exported to P/S circuit 7.P/S circuit 7 is exported to lead-out terminal 8 with the serial digital signal of 270Mbps.
In addition, the PAL analog signal that is provided for input terminal 1 also is provided for synchronizing separator circuit 10.Synchronizing separator circuit 10 will be additional to composite synchronizing signal (comprising horizontal synchronization and vertical synchronization) in the picture signal to be separated and exports to H-PLL circuit 11.H-PLL circuit 11 output is passed and taken advantage of is the clock of the 27MHz in cycle of 1/1728 of (1H) during the horizontal-drive signal, provide it to various piece, and,, also make the synchronizing information in frame period also as one man export to reproduced in synchronization circuit 12 except horizontal synchronization pulse (H pulse).
In addition, 10 parallel-by-bit digital signals from A/D converter 2 outputs also are provided for burst control oscillation circuit 9.Burst control oscillation circuit 9 will be reproduced subcarrier signal and export to decoding circuit 4 and phase-shift circuit 13, and the PAL pulse generating signal is exported to reproduced in synchronization circuit 12.Phase-shift circuit 13 input is from the phase control signal of reproduced in synchronization circuit 12 outputs, and will offer SC/H phase detecting circuit 14 based on the modulating subcarrier signal that this phase control signal has changed output phase.SC/H phase detecting circuit 14 input is from the modulating subcarrier signal of phase-shift circuit 13 outputs and relatively use horizontal synchronization pulse from 12 outputs of reproduced in synchronization circuit, and detect the relative phase of relatively using horizontal synchronization pulse and modulating subcarrier, when phasing back, signal is passed out in the reproduced in synchronization circuit 12 then.The signal that 12 inputs of reproduced in synchronization circuit are exported from H-PLL circuit 11, burst control oscillation circuit 19 and SC/H phase detecting circuit 14, and reproduce the synchronizing signal of 8 field duration.
Fig. 2 is the block diagram of burst control oscillation circuit 9.The frequency that generates employed clock in the circuit that reproduces subcarrier is to pass the 27MHz that takes advantage of (1728 times) and get on the basis of horizontal-drive signal (frequency 15.625KHz).As producing the method that does not have the subcarrier (4.43361875MHz) of simple ratio of integers with respect to 27MHz, the clock frequency conversion method among the patent documentation JP2000-92507A is for example arranged.
The clock that this burst control oscillation circuit 9 is used 27MHz generates the subcarrier signal of the wavy variation of sawtooth by the unit accumulated value is added up.Computing circuit 63 and latch 64 carry out 16 accumulating operation.Accessible value is 0 to 65535 scope.Make calculate corresponding of one-period 360 degree of sawtooth waveforms herein, with 65535.Owing to do not consider the carry of computing circuit 63, so when operation result is 65536 (360 degree), preferred 0 (0 degree).The carry of 16 bit arithmetic circuit 63 be we can say indication cycle's number, by the phase place of discontented 360 degree of 16 bit representations.In the PAL mode, 4,320,000 clock period of 27MHz and consistent during 709,379 cycles of subcarrier.The two shared cycle be picture signal a frame during.The accumulated value as target of one image duration is 709,379 cycle * 65,536=46,489,862,144.Therefore, the unit accumulated value is 10761.54216, owing to be included in the following value of decimal point that does not show in 16, uses approximation to carry out accumulating operation.The margin of error can be revised by Iterim Change unit's accumulated value, but if disposable carrying out then can produce shake, so disperse to carry out.If unit accumulated value 10762 is carried out add operation repeatedly, then can obtain frequency, but deviation be arranged with correct frequency near subcarrier frequency.The method of revising this deviation is to carry out 4 corrections herein.First correction is at 2 clocks the unit accumulated value to be carried out once-1; Second revise be carry out once at 24 clocks+1; The 3rd correction is to carry out 1 time+1 at 2015 clocks; The 4th to revise be 2,160,000 clock carries out once+and 1.By carrying out first to the 4th correction counter of revising 67,68,69,70 respectively, correction value generation circuit 65 produces the signal that the margin of error is disperseed, and exports to computing circuit 63.The 27MHz clock that 66 pairs of general cycle rate counters offer input terminal 52 carries out counting 4,320,000 time, and provides as the signal that correction counter 67,68,69,70 is resetted.Also provide 27MHz clock to revising counter 67,68,69,70.
By above such burst control oscillation circuit 9 that constitutes, can generate the wavy signal of sawtooth of the few subcarrier frequency of shake.But, just can't become the phase locked subcarrier signal of colored burst like this with input.In order to generate and the phase locked subcarrier signal of colored burst, the output of latch 64 is converted into the sinusoidal wave shape signal in SinROM 57, and is provided for multiplicative operator (MPY) 58.The parallel digital signal that is provided for input terminal 51 is provided for multiplicative operator (MPY) 58 via the band pass filter (BPF) 56 that colored burst composition is passed through.Multiplicative operator (MPY) 58 carries out the multiplying of the output signal of the output signal of SinROM 57 and band pass filter 56, and exports to low pass filter (LPF) 59.The output of low pass filter (LPF) 59 is the signals that change according to phase difference.In PAL, every 1H (1 horizontal cycle) differs 90 degree phase places, and is average as if carrying out 2H, then is steady state value.2H average circuit 61 is according to the mean value of the phase error of burst sign (pulse in 1H cycle) the output 2H that offers input terminal 71, and offers computing circuit 63 via switch 62 temporarily, thereby constitutes the ring structure that converges to predetermined phase.By such ring structure, can obtain and the reproduction subcarrier signal of importing that colored burst is phase locked, sawtooth is wavy from latch 64.
The signal that offers lead-out terminal 54 is 16 the signal that is used for the demodulation of carrier chrominance signal in decoding circuit 4.The signal that offers lead-out terminal 53 is the signal identical with the signal that offers phase-shift circuit 13.
On the other hand, the output signal of 60 pairs of low pass filters of amplitude limiter circuit (LPF) 59 is carried out the comparison with predetermined value, and during additional colored burst the signal in 2H cycle is exported to lead-out terminal 55.The PAL pulse generating signal that is equivalent to offer reproduced in synchronization circuit 12 from the signal of lead-out terminal 55 outputs.In addition, as the subcarrier signal of sawtooth waveforms, because 360 degree are carried out computing as 216, amplitude limiter circuit 60 adds fixed value for the subcarrier signal of sawtooth waveforms, if do not consider the carry of figure place, then can easily generate the corresponding fixed value of phase place and the signal that is offset.The skew phase place is relatively more difficult for analogue technique like this, but but is easy to for digital technology.
Fig. 3 is the block diagram of reproduced in synchronization circuit 12, phase-shift circuit 13, SC/H phase detecting circuit 14.As shown in Figure 3, the reproduced in synchronization circuit 12 of PALFF 38, comparison circuit 39,1Fr counting circuit 40, two frame enabling pulse circuit (2FrEN) 41,4Fr pulse counter 42 pie graphs 1.In addition, the phase-shift circuit 13 of adder operation circuit 43, selector 44, multiplying operational circuit 45, phase shift computing circuit 29 pie graphs 1.In addition, the SC/H phase detecting circuit 14 of SC/H center adjustment circuit 30, decoder (SCDEC) 32, circuit for reversing (inverter) 33, NG counter 34, OK counter 35 and OR circuit 36 pie graphs 1.
The H pulse that offers input terminal 23 from H-PLL circuit 11 is provided for 1Fr counting circuit 40 with the frame period pulse that offers input terminal 22.1Fr counting circuit 40 is that it exports to lead-out terminal 28 with pulse count value LN9～LN0 and 625 line periods, that represent interleaved odd field/even field to 0 to 624 10 the counter of counting suitable with the line number of a frame.
Next illustrate phase shift computing circuit 29 is controlled, thereby when the output by the H pulse observation decoder 32 that postponed, obtain the part of the modulating subcarrier of constant phase.45 pairs of expressions of multiplying operational circuit are carried out multiplying from the signal and the fixed value 105 of the line number (0～624) of 1Fr counting circuit 40 outputs, and export to phase shift computing circuit 29.At this moment, the output valve of multiplying operational circuit 45 is 0～65520.The output of multiplying operational circuit 45 is to make to reproduce about 0.58 degree of the every line displacement of subcarrier, the signal of a vertical shift 360 degree.In addition, multiplying operational circuit 45 is the circuit that carry out with the multiplying of 625 such fixed values, also can use the table among the ROM (read-only memory) to realize.
Two adder operation circuit 43 will be from signal LN0, the LN1 in 4H cycle of two of the lowest order of 1Fr counting circuit 40 output with another signal plus of two and export.So-called another signal is meant, makes from the signal of 4Fr pulse counter 42 outputs to be a high position, and making from the signal in two frame periods that comparison circuit 39 is exported is two signal of low level.Selector 44 expression by two is from the signal of four values of adder operation circuit 43 outputs, selection is spent with 270 degree, 180 degree, 90 respectively, 0 some values of spending in the corresponding value 0.75 * 216,0.5 * 216,0.25 * 216,0, and signal is exported to phase shift computing circuit 29.
29 inputs of phase shift computing circuit offer the wavy reproduction subcarrier signal of 16 sawtooth of input terminal 21 from the lead-out terminal 54 of Fig. 2.Then, by 16 phase-shifted control signals when 90 of selector 44 output is spent and 16 the phase-shifted control signal that changes through 1 frame from multiplying operational circuit 45 outputs are carried out add operation or subtraction, phase place is changed ground reproduction subcarrier signal be converted to the constant modulated carrier signal of phase place in every provisional capital, and export to SC/H center adjustment circuit 30.
30 pairs of modulating subcarrier signals from 29 outputs of phase shift computing circuit of SC/H center adjustment circuit apply predetermined stationary phase to be changed, thus the signal and the output of from 16 signal, extracting most-significant byte.From the signal of SC/H center adjustment circuit 30 outputs high two of 32 pairs of decoders decode, and 360 degree are divided into four parts, thereby the output average duty ratio is 1/4 signal.Be provided as the count enable signal of NG counter 34 from the signal of decoder 32 output, also be provided as the count enable signal of OK counter 35 via circuit for reversing 33.
On the other hand, the clock used as counter via delay circuit 46 of the H pulse that is provided for input terminal 23 and be provided for NG counter 34 and OK counter 35.In response to the H pulse of this delay, the count value that is in a certain counter of counting enabled state in NG counter 34 and the OK counter 35 increases.Be in a certain counter output carry when count value for example becomes maximum 15 of counting enabled state.The carry of being exported resets NG counter 34 and OK counter 35 via OR circuit 36.Here, when the phase place of modulating subcarrier signal has been reversed, before resetting, send the carry of NG counter 34 earlier.This carry signal is sent to 4Fr pulse counter 42, thereby makes output polarity (binary one and the 0) counter-rotating of 4Fr pulse counter 42.After the output polarity counter-rotating of 4Fr pulse counter 42, the output of adder operation circuit 43 adds 2, changes thereby 180 degree take place selector 44 selected phase places.Thus, phase shift computing circuit 29 makes phase deviation 180 degree that reproduce subcarrier signal by the output of selector 44 and multiplying operational circuit 45, thereby has only the action of the generation modulating subcarrier of OK counter 35 increases.
Fig. 4 a, Fig. 4 b are the schematic diagrames of the phase relation of modulating subcarrier and delay H pulse.The longitudinal axis is represented the amplitude (being equivalent to the output of SC/H center adjustment circuit 30) of modulating subcarrier, transverse axis express time.On transverse axis, show the position that postpones the H pulse.In addition, the relative phase with modulating subcarrier and delay H pulse shows the zone (OK) of OK counter 35 increases and the zone (NG) that NG counter 34 increases accordingly.Shown in Fig. 4 a, when delay H pulse is H1, have only OK counter 35 to carry out counting, NG counter 34 stops.If because reason such as noise and relative phase is changed to H2 from H1 then has only NG counter 34 to increase.If the phase state of H2 continues, then NG counter 34 produces carry, thus the output of 4Fr pulse counter 42 counter-rotating.The phasing back of modulating subcarrier thus, thus transition are the phase relation shown in Fig. 4 b.The zone of OK counter 35 (OK) is wideer than the zone (NG) of NG counter 34, the state before the phase state in the middle of H1 and the H2 keeps.That is, in two the zone in having determined four zones, remaining two is the zone of the state determined in the past, thereby becomes the action that has hysteresis.Here, not adopting to be divided into four parts of methods in zone of setting 1: 3 ratio, if be divided into for example two parts of detections of carrying out color framing of symmetry, then is the action that does not have hysteresis.At this moment, at the intermediate phase place, because small shake, unnecessary counter-rotating takes place in SC/H testing result again and again, thereby action is unstable.In addition, the dotted line among Fig. 4 is represented 360 degree are divided into four parts scale, is not the interval of 27MHz clock.With the clock number of 27MHz relative during one-period of subcarrier signal approximately is 6.09.Therefore, be expressed as the scale that is divided into four parts, but split position is along with 27MHz clock momentary variation.
But the periodicity of the subcarrier in during the 1H of PAL mode was 283.7516 cycles.If be conceived to the decimal point part, then in every 1H,, 270 degree spend the phase place of subcarrier if being offset about 0.58, and then consistent with the H cycle.Delay circuit 46 makes timing slip after 1Fr counting circuit 40 changes, thereby OK counter 35 and NG counter 34 are counted.
In addition, also above-mentioned adder operation circuit 43 and selector 44 can be replaced into the input figure place is four ROM.In addition, if detect SC/H at 2H in the cycle, then the signal that will be offset phase place of selector 44 outputs can be that 0 degree and 180 is spent two, and adder operation circuit 43 also can be one.Wherein, between the carry output and 4Fr pulse counter 42 of NG counter 34, need to add a circuit that makes the 2H broad pulse be reduced into the 1H broad pulse.In addition, the figure place of phase shift computing circuit 29 is 16, but if do not need precision, then also can significantly reduce figure place.For example, if 7, then 360 degree being divided into 128 parts, error is equivalent to 2.8 degree, but it is enough as the precision that SC/H detects.In addition, be suitable relation as long as reproduce subcarrier phase, there is not SC/H center adjustment circuit 30 passable yet.
The SC/H testing circuit of Fig. 3 regularly generates the always constant modulating subcarrier of phase place with H, and detection SC/H, but following method is arranged also, that is: adding with the signal from delay circuit 46 outputs before phase shift computing circuit 29 is the circuit that clock latchs the reproduction subcarrier, thereby slows down arithmetic speed.Can alleviate the treating capacity of after-stage by slowing down.
In addition, OK counter 35 and NG counter 34, can set as required to the count value that produces till the carry.To the count value that produces till the carry, both can for example be 8.If this count value is 8, then when input signal is switched to other color framing signal, wait for the time suitable at least with 8H.Even because the The noise that is subjected to sneaking in the input signal also will be waited for 8H, at least so reduced the flase drop survey.In addition, owing to be difficult to be subjected to The noise, so for to the count value that produces till the carry, can be that the NG counter is 31, the OK counter be 7 etc.By such setting count value, under situation about being counted with the frequency of half by a certain counter, the carry of OK counter produces earlier, thereby is difficult to the SC/H that reverses.Wherein, slack-off to the response of the switching of the SC/H that has reversed.The preferred count value that produces till the carry that is set to as required.
Monitor and the SC/H supervisory signal is exported to lead-out terminal 25 with latch 31.For example, to be connected to the input (input terminal 1 of Fig. 1) of device from the PAL signal that the correct signal source of SC/H provides, be offset phase place regularly by SC/H center adjustment circuit 30 then, and can regulate while monitoring, make the output signal of lead-out terminal 25 be predetermined value, be illustrated in figure 4 as near the value 96.In addition, at this moment, the signal of lead-out terminal 25 is signals of 8, but for example also can increase the comparison circuit of representing whether to enter 96 ± 4 scope with 10 systems, thereby makes and can access 1 signal as output.
Fig. 5 is the figure of value of signal of Fig. 3 each several part of 4 image durations of expression.Each row to Fig. 5 describe.The line number of (1) row is represented the difference carried out for figure is described, line number 8 and 9,16 and 17,24 and 25,32 and 1 separately between show the migration of picture frame.In addition, the information of the amount of 618 row is arranged respectively in the line number 6,14,22,30, but its explanation is omitted.The output signal of 4Fr pulse counter 42 is shown in (2) tabulation.The PAL pulse as the output of PALFF 38 is shown in (3) tabulation.The output of comparison circuit 39 is shown in (4) tabulation, promptly represents 2 frame pulses as the comparative result of PAL pulse and LN0.(5) row are represented 10 output signals of 1Fr counting circuit 40 with 10 systems.That is, represent line number LN with 0～624.LN1, LN0 that the low level that (6) tabulates shows 1Fr counting circuit 40 is two.Two outputs of adder operation circuit 43 are shown in (7) tabulation, promptly import with the control of 10 system presentation selectors 44.(8) row are with the output of the angle presentation selector 44 of the subcarrier of phase shift.Two at adder operation circuit 43 are output as at 0,1,2,3 o'clock, and subcarrier is 0,270,280,90 degree of phase shift accordingly respectively.(9) row are represented the output of multiplying operational circuit 45 with the angle of the subcarrier of phase shift.That is, represent (fixed value 105) * (line number LN) * 360/216 with angle.
In Fig. 5, be example with line number 11, the output signal of 4Fr step-by-step counting 42 is that 0, two frame pulse is 1, LN1=1, LN0=0, therefore, adder operation circuit 43 is output as 1+2=3.Corresponding with it, the angle of subcarrier phase shift is 90 degree.In addition, because line number is 2, so 105 * 2 * 360/216=1.15 degree, subcarrier is by phase shift, and the phase shift angle of its total is 91.15 degree.
In addition, in Fig. 5, when NG counter 34 has produced carry, the output of 4Fr pulse counter 42 counter-rotating.Because for example, the state of 1～8 row transition respectively is the state of 17～24 row, even line number is identical, the value of (8) row is also expressed skew 180 degree.
When regularly observing with H, color frame detection circuit always generates the constant modulating subcarrier signal of phase place.And divide two kinds to generate the modulating subcarrier signal, and a kind of is that unit changes with 90 degree, another kind changes through 625 row.With 90 degree is that the phase deviation of unit is a circulation with the 4H cycle, and the pass of 4H and 1 frame is 625/4=156.25.Only use two of low levels among 10 an of frame counter, and do not use high-order 8.At decimal point in the 0.25 later cycle, make after the pulse of two frame periods and the information combination in four frame periods through 4 frames, generate 90 degree and be unit continually varying signal.Like this, only use two of low levels among 10 an of frame counter.
As mentioned above, competition counting circuit the average processing of SC/H phase detecting circuit 14 by forming by OK counter 35 and NG counter 34.Then, this result is fed back to 4Fr pulse generating circuit 42, realize having sluggish structure by forming such closed-loop structure.
The color frame detection circuit that comprises the SC/H phase detecting circuit 14 of this spline structure only uses specific capable information, under the situation of not carrying out the SC/H detection, by all row being detected SC/H, make the border of phase-detection have lagging characteristics, using repeatedly testing result etc., make situation about mixing etc. for noise can more stably carry out work thus.
Claims (9)
1. a color frame detection circuit is characterized in that, comprising:
Burst control oscillation circuit is used for generating the reproduction subcarrier signal synchronous with the colored burst of received image signal;
The reproduced in synchronization circuit is used for the frame information and the horizontal scanning line numbering of the amount of four frames of described received image signal are counted;
Phase-shift circuit is used for being created on each horizontal scanning line has been offset phase place the cycle modulating subcarrier signal according to described horizontal scanning line numbering and described frame information from described reproduction subcarrier signal;
Subcarrier/horizontal synchronization testing circuit is used to detect the relative phase between the horizontal synchronization pulse signal of described modulating subcarrier signal and described received image signal;
Wherein, described reproduced in synchronization circuit is controlled the side-play amount with respect to the phase place of modulating subcarrier signal described in the described phase-shift circuit based on the change in time of described relative phase.
2. color frame detection circuit as claimed in claim 1 is characterized in that,
Change in time changes the counting sequence that described horizontal scanning line is numbered to described reproduced in synchronization circuit based on described relative phase, controls described side-play amount thus.
3. color frame detection circuit as claimed in claim 1 is characterized in that,
Described subcarrier/horizontal synchronization testing circuit comprises:
First counter is used in the predetermined phase scope in the one-period of described modulating subcarrier signal described horizontal synchronization pulse signal being counted; With
Second counter is used for outside the described predetermined phase scope in the one-period of described modulating subcarrier signal described horizontal synchronization pulse being counted;
Wherein, described reproduced in synchronization circuit is according to which count down to predetermined number earlier and controls described side-play amount in described first and second counters.
4. color frame detection circuit as claimed in claim 3 is characterized in that,
The size of described predetermined phase scope is set for less than the described predetermined outer size of phase range; When described reproduced in synchronization circuit count down to described predetermined number at described first counter earlier than described second counter, make phase deviation 180 degree of described modulating subcarrier signal.
5. as claim 3 or 4 described color frame detection circuits, it is characterized in that,
According to the value of the multidigit gained of the high position of described modulating subcarrier signal decoding when representing with digital value is determined described predetermined phase range.
6. color frame detection circuit as claimed in claim 1 is characterized in that,
Described reproduction subcarrier signal is the wavy signal of being represented by digital value of sawtooth;
Described phase-shift circuit adds or deducts respectively the corresponding value of frame information with the amount of described horizontal scanning line numbering and described four frames to the wavy signal of described sawtooth, and operation result is exported as described modulating subcarrier signal.
7. color frame detection circuit according to claim 1 is characterized in that,
Described reproduction subcarrier signal is the wavy signal of sawtooth,
Described burst control oscillation circuit comprises:
The cumulative integral computing circuit is used to produce the wavy signal of described sawtooth;
Regulating circuit is used for described colored burst and the wavy signal of described sawtooth are carried out multiplying, and regulates the generation cycle of the wavy signal of described sawtooth based on the low-frequency component of multiplication result.
8. as color frame detection circuit as described in the claim 7, it is characterized in that,
Described cumulative integral computing circuit comprises:
Computing circuit is used for adding predetermined value at each reference clock, generates the wavy signal of described sawtooth; With
A plurality of correction counters were used in the one-period of the wavy signal of described sawtooth, generated separately correction value at interval in separately predetermined clock;
Wherein, described computing circuit carries out the plus and minus calculation of described correction value in the generative process of the wavy signal of described sawtooth.
9. an image signal conversion device is characterized in that,
It has each described color frame detection circuit in the claim 1 to 8, and uses the frame information of the amount of described four frames that PAL analog composite picture signal is converted to the component serial digital signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005092653A JP2006279300A (en) | 2005-03-28 | 2005-03-28 | Circuit for detecting collar frame and video signal conversion apparatus |
| JP2005092653 | 2005-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1842167A true CN1842167A (en) | 2006-10-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610058480 Pending CN1842167A (en) | 2005-03-28 | 2006-03-28 | Color frame detection circuit and image signal conversion device |
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| Country | Link |
|---|---|
| JP (1) | JP2006279300A (en) |
| CN (1) | CN1842167A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102077104A (en) * | 2008-07-09 | 2011-05-25 | 爱德万测试株式会社 | Testing device and testing method |
| CN102821227A (en) * | 2011-06-10 | 2012-12-12 | 上海华虹集成电路有限责任公司 | Method for determining odd-even field of video signal |
-
2005
- 2005-03-28 JP JP2005092653A patent/JP2006279300A/en not_active Withdrawn
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2006
- 2006-03-28 CN CN 200610058480 patent/CN1842167A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102077104A (en) * | 2008-07-09 | 2011-05-25 | 爱德万测试株式会社 | Testing device and testing method |
| CN102821227A (en) * | 2011-06-10 | 2012-12-12 | 上海华虹集成电路有限责任公司 | Method for determining odd-even field of video signal |
| CN102821227B (en) * | 2011-06-10 | 2017-03-15 | 上海华虹集成电路有限责任公司 | A kind of decision method of video signal parity field |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006279300A (en) | 2006-10-12 |
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