JP2508435B2 - Video signal processing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video signal processing device suitable for memory applications.

[Outline of Invention]

According to the present invention, in the processing of a digital video signal with a subcarrier lock clock, when writing to or reading from the memory for time axis correction, the write or read address signal is reset by the horizontal synchronizing signal of the input video signal to change the memory. By functioning as a delay line,
According to the line lock, a digital video signal suitable for the same memory application can be obtained with a relatively simple structure.

[Conventional technology]

As is well known, in the current NTSC system, a pair of color difference signals RY, BY or color signals I, Q have a frequency fsc of, for example, 445.
It is transmitted in the form of a carrier color signal by quadrature two-phase modulation of a color subcarrier of f _H / 2 ≈3.58 MHz.

Therefore, when digitizing a color video signal, A
-Set the sampling clock frequency of the D converter to 4fsc =
If a so-called sub-carrier lock system for selecting the phase for each of the above-mentioned modulation axes is adopted for 910f _H , the digital data becomes, for example, ± (R−Y) or ± (B−Y) as it is, and the color difference signal or the color signal is obtained. Can be easily demodulated.

[Problems to be solved by the invention]

However, when the color video signal reproduced from the VTR or the like by the subcarrier lock system is digitized, there are the following problems.

That is, since a reproduced signal such as a VTR has jitter due to uneven rotation of a driving mechanism, the reproduced signal has jitter, and when sampling with a clock locked to a color subcarrier, one horizontal period is Becomes

As a result, the sample points of the A / D converter are not aligned vertically on the screen but are randomly arranged.
Moreover, the arrangement of sample points is different for each field.

Therefore, even if an image data processing using a memory (referred to as memory application in the present application) is performed, such as inter-field interpolation or inter-field interpolation in double-speed progressive scanning, if the sampling points are irregular, processing is performed. The inconvenience arises that the image data to be present does not exist at the desired position.

In order to solve the above-mentioned problems, the video signal data after color demodulation is once converted into an analog signal and re-digitized with a so-called line-lock sampling clock having a frequency N times the horizontal frequency f _H. It is proposed to use a sampling rate converter (SRC) or a digital SRC that converts digital data as is to a line-locked sampling clock, and perform image data processing in memory with each converted line-locked clock. Has been done.

Also, in the "television receiver" of the double speed progressive scanning type proposed by the applicant in Japanese Patent Laid-Open No. 60-180290, a subcarrier is used for AD conversion of an input video signal and writing to a memory circuit for double speed conversion. A lock type clock is used, and when reading from the double speed conversion memory circuit,
A clock that is separated from an input video signal and locked to a horizontal synchronizing signal from which a jitter component has been removed by a frequency selection circuit such as a PLL is used.

Each of the above-described systems uses two types of clocks in combination and is associated with each other to support a memory application. Therefore, the system becomes complicated and the circuit becomes large in scale. .

In view of such a point, an object of the present invention is to provide a video signal which has a simple configuration, is easy to perform color demodulation, and is capable of removing a jitter of an input video signal, thereby obtaining a digital signal suitable for memory application. A processor is provided.

[Means for solving problems]

A first aspect of the present invention is a video signal processing apparatus for converting a color video signal into a digital video signal by a clock formed on the basis of a color burst signal and processing the digital video signal. Memory is provided, and at least the luminance signal in the digital video signal is written into the memory and read out from the memory by using the clock formed based on the color burst signal, and the horizontal in the luminance signal written in the memory is performed. It is a video signal processing device that resets a write address signal or a read address signal of a memory by a signal obtained by temporally averaging synchronization signals.

A second aspect of the present invention is a video signal processing apparatus for converting a color video signal into a digital video signal by a clock formed on the basis of a color burst signal and processing the digital video signal. Memory is provided, and at least the luminance signal in the digital video signal is written into the memory and read out from the memory by using the clock formed based on the color burst signal, and the horizontal in the luminance signal written in the memory is performed. The write address signal or the read address signal of the memory is reset according to the average value of the synchronization signal, the phase error within one sampling period with respect to the reference value of the horizontal synchronization signal read from the memory is detected, and based on this detection output It is a video signal processing device adapted to correct the phase of a luminance signal.

[Operation] According to the present invention, the position of the first data is constant for each line, and the data digitized by the clock of the subcarrier lock system is line-locked on the screen, as in the case where the data is line-locked. It is vertically aligned and suitable for memory applications.

〔Example〕

An embodiment of a video signal processing device according to the present invention will be described below with reference to the drawings.

 FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, a color video signal from a VTR (not shown) is supplied from an input terminal IN to an AD converter (1), and a digital output of this AD converter (1) uses a frame memory. The Y / C separation circuit (2) is supplied to separate the digital luminance signal Y and the digital carrier color signal C.

(3Y) and (3C) are time axis correction circuits, and (4) is a phase data interpolation circuit, the detailed configuration of which will be described later. The separated luminance signal Y is supplied to the time axis correction circuit (3Y), and the output of this correction circuit (3Y) is supplied to the gradation / sharpness control circuit (5) via the interpolation circuit (4). The separated carrier color signal C is supplied to the hue adjustment circuit (7) via the ACC / color killer circuit (6), adjusted to an appropriate phase, and supplied to the color demodulation circuit (8). From the color demodulation circuit (8), the red color difference signal RY and the blue color difference signal BY are supplied to the time axis complementary circuit (3C) and the color burst signal is supplied to the clock oscillator (9). From this oscillator (9), a fixed clock with a frequency of 4f _SC is sent to the AD converter (1), Y /
It is supplied to the C separation circuit (2), both time axis correction circuits (3Y) and (3C), and the phase data interpolation circuit (4).

(11) is a frame memory for image processing,
Digital luminance signal Y from the control circuit (5) and digital color difference signals RY and BY from the time axis correction circuit (3C)
And are written. The luminance signal Y, the color difference signals RY and BY read from the frame memory (11) are D-
The analog signal is converted in the A converter (12), the luminance signal Y is supplied to the matrix circuit (14) through the luminance control circuit (13), and both color difference signals RY and B- are supplied.
Y is directly supplied to the matrix circuit (14) and converted into three primary color signals R, G, B.

The frame memory (11) and the DA converter (12)
Is supplied with a subcarrier lock clock from an oscillator (9).

FIG. 2 shows the basic configuration of the time axis correction circuits (3Y) and (3C).

In FIG. 2, (31) is a memory, and its capacity is set to be slightly larger than the data for one line, that is, 910 samples.

Luminance signal data from the input terminal (30 in) is stored in the memory (3
It is also supplied to the horizontal sync detection circuit (33) through the reduction filter (32). (34) and (35) are address counters for writing and reading, respectively, and (36) is a counter for input terminal (30c
Clocks with a frequency of 4f _SC are supplied from k),
The write address signal and the read address signal are supplied to the memory (31) from the counters (34) and (35), respectively. The output of the horizontal sync detection circuit (33) is supplied as a reset signal for the write address counter (34) and the counter (36). The output of the counter (36) is latched (3
Is supplied to the n-stage shift register (38) via
The output of the shift register (38) is supplied to an average value circuit (39) consisting of an adder and a coefficient multiplier, and the average value circuit (3
The output of 9) is supplied as a reset signal of the read address counter (35).

The reset signals of both address counters (34) and (35) can be exchanged. In this case, the output of the horizontal sync detection circuit (33) is supplied to the address counter (35) via a delay circuit (not shown) having a delay time corresponding to the memory (31).

Further, when the time axis correction of the carrier color signal C is performed, the correction circuit for the luminance signal Y is appropriately changed, such as receiving a horizontal synchronization detection signal.

 The structure of the phase data interpolation circuit (4) is shown in FIG.

In FIG. 3, (41a) ... (41d) are unit delay circuits, which are composed of, for example, D-type flip-flops, and the delay time t is 70 nS which is the cycle of the clock supplied from the terminal (40ck). The delay circuits (41a) to (41d) are connected in cascade, and the first delay circuit (41a) is connected to the input terminal (40i).
n) digital luminance signal Y is supplied to each delay circuit (41
The outputs of a) to (41d) are supplied to coefficient multipliers (42a) to (42d), respectively. Reference numeral (43) is a horizontal synchronization phase detection circuit, which is supplied with a digital luminance signal, and whose output is commonly supplied to coefficient multipliers (42a) to (42d). The outputs of the coefficient multipliers (42a) to (42d) are added by the adder (4
4) and the output of the adder (44) is led to the output terminal (40out) via the delay circuit (latch) (45).

Next, the operation of the time axis correction circuit (30) shown in FIG. 2 will be described with reference to FIG.

Digital luminance signal Y supplied to the input terminal (30in)
The noise component is removed by the reduction filter (32) and is supplied to the horizontal synchronization detection circuit (33). In this detection circuit (33), as shown in FIG. 4, the sample S ₀ of the peak of the horizontal synchronizing pulse is detected, and the threshold level L _th set to 1/2 of this peak value [p], Sample S ₁ before and after the intersection Q with the trailing edge of the horizontal sync pulse
And the sample points of S ₂ (time) t ₁ and t ₂ is detected, the detection output is supplied to the write address counter (34) and the counter (36) (t ₁ in the drawing) sample points preceding the intersection Q It

The detection output of the detection circuit (33) is reset, the address counter (34) starts operating, and supplies a write address signal to the memory (31) at each clock. As a result, the luminance signal data is sequentially written in the memory (31).

On the other hand, the counter (36) is reset for each horizontal synchronizing pulse, and its output is synchronized with each line. The output of the counter (36) is latched by the latch (37) and the shift register (38) for every n lines (n = 10, 20, etc.) and is supplied to the average value circuit (39). 39), the average of horizontal periods of n lines is calculated, and the average is reset at every average horizontal synchronization, and the address counter (3
5) starts operation and supplies a read address signal to the memory (31) at each clock. This allows the memory (3
The luminance signal data is sequentially read from 1).

The above-described operation is repeated for each line of the input signal, the digital video signal with the sampling frequency of 4f _SC is written in the memory (31) starting from the horizontal synchronizing signal, and the memory ( 31), so this memory (31) functions as a variable delay line,
The jitter of the input signal is removed, and a digital video signal equivalent to that obtained by the line lock system is obtained. On the screen, the left end of each line is 1 sampling cycle (1 / 4f _SC ≈ 70
It will be aligned in nS) units, which is suitable for various memory applications.

By averaging the input horizontal periods in this manner, the horizontal frequency is fixed, fluctuations in the deflection system are removed, and the capacity of the memory (31) can be reduced.

For deflection, the horizontal synchronization signal is kept constant (91
0 / 4f _SC ), and the horizontal sync signal before time base correction can also be used.

Further, when the reset signals of both the adrel counters (34) and (35) are exchanged, the digital video signal is written in the memory at each average horizontal cycle, but in this case, as described above, the horizontal sync detection circuit ( The detection output of 33) is supplied to the read address counter (35) through the delay circuit corresponding to the memory (31), so that the reading is performed starting from the horizontal synchronizing signal for each line, and the same digital signal as described above is used. A video signal is obtained.

Next, the operation of the phase data interpolation circuit (40) shown in FIG. 3 will be described with reference to FIG.

When the output of the time axis correction circuit (30) is supplied from the input terminal (40 in), the horizontal sync phase detection circuit (43) causes the falling edge of the horizontal sync pulse to fall, as shown in FIG. Is constant, the phase of the midpoint Q (distance from the sample point) T _X is the value [a] and [b] of the samples S ₁ and S ₂ before and after the midpoint Q. Then, it is obtained by the following equation (1).

T _X = T _S · a / (a + b) (1) Here, T _S = 1 / 4f _SC Here, with respect to the phase T _{X of the} Q point obtained by the equation (1),
Ideal reducing characteristic of the filter interpolation in accordance with (sinT _X) / T _X is made.

In the case of the interpolation by the samples S _{0 to} S ₃ at each of the two points before and after the point Q in FIG. 4, at the reference time t ₁ , the reference sample S ₁ is at the output side of the unit delay circuit (41c) in FIG. In addition, the preceding sample S ₀ is present at the output side of the unit delay circuit (41d), and the subsequent samples S ₂ and S ₃ are respectively present at the output sides of the unit delay circuits (41b) and (41a). Exists. As is clear from FIG. 4, the midpoint Q of the falling edge of the horizontal synchronizing pulse and the preceding and succeeding samples S ₀ , S ₂ and S ₃
The intervals between and are T _S + T _X , T _S −T _X and 2T _S −T _X , respectively.
Depending on this interval, the coefficient K _a ~K _d of each coefficient multiplier for the above-described interpolation (42a) ~ (42d) is as the following equation (2).

By this interpolation processing, the luminance signal data itself at the timing of the subcarrier lock clock is rewritten so as to be line locked, and the position of each data is detected in the memory by the phase detection circuit (43) detection accuracy (for example, several nS). ) Will be lined up.

Since the carrier color signal is transmitted in a narrow band, 70 nS of jitter does not appear on the screen and the above-described interpolation processing is not necessary.

〔The invention's effect〕

As described above in detail, according to the present invention, when a digital video signal based on a single subcarrier lock clock is written to or read from a memory for time axis correction, writing or reading is performed by a horizontal synchronization signal of an input video signal. Since the address signal is reset and the memory is made to function as a variable delay line, a video signal processing device capable of obtaining a digital video signal suitable for the same memory application as in the case of the line lock clock with a relatively simple structure is provided. can get.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a video signal processing apparatus according to the present invention, FIGS. 2 and 3 are block diagrams showing the configuration of the essential parts of an embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram for explaining an operation of a main part of one embodiment of FIGS. 2 and 3. (3Y), (3C), (30) are time axis correction circuits, (4),
(40) is a phase data interpolation circuit, (31) is a memory, (33)
Is a horizontal sync detection circuit, (34) and (35) are address counters, and (43) is a horizontal sync phase detection circuit.

Claims (2)

(57) [Claims] 1. A video signal processing device for converting a color video signal into a digital video signal by a clock formed on the basis of a color burst signal and processing the digital video signal. And writing at least a luminance signal in the digital video signal to the memory and reading from the memory using a clock formed based on the color burst signal, and the luminance signal written to the memory. A video signal processing device, wherein a write address signal or a read address signal of the memory is reset by a signal obtained by temporally averaging the horizontal synchronizing signals in the inside. 2. A video signal processing apparatus for converting a color video signal into a digital video signal by a clock formed on the basis of a color burst signal, and processing the digital video signal. And writing at least a luminance signal in the digital video signal to the memory and reading from the memory using a clock formed based on the color burst signal, and the luminance signal written to the memory. The write address signal or the read address signal of the memory is reset according to the average value of the horizontal sync signal in the memory, and 1 is set to the reference value of the horizontal sync signal read from the memory.
A video signal processing device characterized by detecting a phase error within a sampling period and correcting the phase of the luminance signal based on the detected output.