JPH09205656A - Video signal sampling rate converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high image quality video image even from a non-standard signal at VTR reproduction in which various signal processing is conducted with an optimum clock signal even when a standard or a non-standard signal is received. SOLUTION: An analog composite video signal inputted to a video signal input terminal 1 is inputted to A/D converters 2, 3. An output signal from the A/D converter 2 is sampled by a burst lock clock signal generated by a burst clock generating circuit 5, and an analog video signal is converted into a digital signal. The output signal of the A/D converter 3 is sampled by a line lock clock signal generated by a line lock generating circuit 7 and an analog video signal is converted into a digital signal. The signals are wide-converted by a wide conversion processing circuit 19 and a video signal output processing circuit 20 conducts image quality adjustment and matrix transformation, the result is converted into an analog signal at a D/A converter 21 and outputted at video signal output terminals 22, 23, 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal sampling rate conversion device for a television receiver or the like, and more particularly to a VTR for a digital television receiver (hereinafter referred to as a digital TV) for performing digital signal processing. The present invention relates to a video signal sampling rate conversion device for suitably processing a nonstandard signal such as a reproduction signal.

[0002]

2. Description of the Related Art Conventionally, in a digital TV, a burst lock clock signal locked to a color burst signal or a line lock clock signal locked to a horizontal sync signal is used as a synchronous system clock signal for signal processing for high image quality reproduction. Different types of system clock signals are considered. For that purpose, the synchronous reproduction circuit reproduces a stable synchronous reproduction signal based on the burst lock clock signal or the line lock clock signal, and the clock signal is input on the signal processing circuit to obtain a video signal for high image quality. It was being processed.

As described above, two types of system clock signals are considered in the case of a standard signal such as a broadcast wave and a non-standard signal such as a reproduction signal of a VTR.
This is because the optimum clock signal to be supplied for signal processing is different. For example, it is desirable that the luminance signal and the chrominance signal be separated and that the system clock of the color demodulation unit be synchronized with the color subcarrier. Therefore, in this case, a burst lock clock signal having high stability may be used for both standard and non-standard input video signals.

On the other hand, the system clock for signal processing including line interpolation processing such as wide conversion and progressive scanning line conversion is preferably synchronized with the horizontal synchronizing signal and the vertical synchronizing signal. Therefore, in this case, the line lock clock signal is used especially in the non-standard signal mode in which there is a lot of jitter in the horizontal direction like the VTR reproduction signal.

When the above technique is applied to an actual digital TV, in the signal processing from the A / D converter to the D / A converter, all system clock signals are converted to burst lock clock signals at the time of standard signal, When a non-standard signal is used, the reproduced image is processed by switching to the line lock clock signal and used, or by selectively using the above two system clock signals depending on the type of signal processing.

Incidentally, as a conventional system of a synchronization processing circuit for a non-standard signal in a digital TV, for example, there is JP-A-64-89791 (name: "television receiver"). To be

[0007]

By the way, in the above-mentioned prior art, the sampling lock signal of the A / D converter for the signal processing of the television receiver is generated by the Y / C separation circuit and the color demodulation circuit succeeding to the next stage. A burst lock clock signal is typically used to match the system clock signal used.

Therefore, even if the data sampled by the burst lock clock signal is supplied to the wide conversion processing circuit including the scanning line processing in the subsequent stage, the data is basically synchronized with the line clock signal. Therefore, the reproduced image has a phase shift, and horizontal vibration occurs in the horizontal direction of the screen. This effect becomes remarkable when the burst lock clock signal and the line clock signal have a nonstandard signal in which a frequency difference is generated, which causes image deterioration.

An object of the present invention is to solve the above problems and perform various signal processing with an optimum clock signal suitable for both standard and non-standard signal input, thereby achieving VTR.
It is an object of the present invention to realize a video signal sampling rate conversion device for a television receiver that can obtain a high quality image even with a non-standard signal at the time of reproduction.

[0010]

To achieve the above object, a video signal sampling rate conversion apparatus according to the present invention comprises means for separating and extracting a horizontal synchronizing signal and a color burst signal included in an input video signal, and a color burst signal. Means for generating a first clock signal having a predetermined frequency synchronized with the horizontal synchronizing signal and a second clock signal having a predetermined frequency synchronized with the horizontal synchronizing signal; and a means for sampling the input video signal with each of the first and second clock signals. It is provided with first and second video signal sampling means. In addition, the video signal sampled by the first video signal sampling means is converted into the second video signal.
And a horizontal axis included in the video data from the first video signal sampling means, the time axis conversion adjusting means for converting the clock signal to the time axis rate based on the clock signal and adjusting the sending timing of the video signal data for each sample unit. A means for detecting a phase error based on the time axis fluctuation of the synchronization signal, a means for controlling the time axis conversion adjusting means based on the information from the phase error signal, and a linear interpolation based on the phase error signal data. The sampling rate conversion means is comprised of a means for generating the interpolation coefficient and a means for performing linear interpolation using the video data and the interpolation coefficient from the time axis conversion adjustment means.

Then, the sampling rate conversion means converts the video data sampled with the first clock signal into a time base rate based on the second clock signal and performs phase correction to convert the input video signal. Sampling rate conversion from the first clock signal to the second clock signal is performed. Further, the burst signal extraction means extracts the signal from the first video signal sampling means based on a first clock signal. Further, the horizontal synchronizing signal separation means performs separation processing based on the signal from the second video signal sampling means or direct separation processing from the input video signal.

[0012]

Embodiments of the present invention will be described below. FIG. 1 is a schematic configuration diagram of a digital video signal processing device to which a video signal sampling rate conversion device according to an embodiment of the present invention is applied. In the figure, 1 is a video signal input terminal, 2 and 3 are A / D converters, 4 is a burst signal extraction circuit, 5 is a burst lock clock signal generation circuit, 6 is a horizontal synchronization signal separation circuit, and 7 is a line lock clock. A signal generation circuit, 8 is a three-dimensional Y / C separation circuit, 9 is a color demodulation circuit, and 10 is a sampling rate conversion circuit which is a feature of the present invention. In the sampling rate conversion circuit 10, 11, 12, 13 are time axis conversion adjustment circuits, 14 is a phase error signal detection circuit, 15 is an interpolation coefficient generation circuit, 16, 17, 18 are linear interpolation circuits, and 54 is a control signal. It is a generation circuit. Further, 19 is a wide conversion processing circuit,
20 is a video signal output processing circuit, 21 is a D / A converter, 2
2, 23 and 24 are video signal output terminals, and 25 is a synchronizing signal reproducing circuit.

Next, the operation of the apparatus according to this embodiment shown in FIG. 1 will be described. The analog composite video signal input to the video signal input terminal 1 is input to the A / D converters 2 and 3. The A / D converter 2 samples a burst lock clock signal (hereinafter abbreviated as burst clock) described later to convert the analog video signal into a digital signal. The A / D converter 3 samples an analog video signal into a digital signal by sampling with a line lock clock signal (hereinafter abbreviated as line clock) described later.

The digital video signal from the A / D converter 2 is input to the burst signal extraction circuit 4 and the three-dimensional Y / C separation circuit 8, and the burst signal extraction circuit 4 bursts from the video signal in synchronization with the burst clock. Extract the signal, 3
The dimension Y / C separation circuit 8 separates and outputs the composite video signal into a Y signal and a C signal. The three-dimensional Y / C separation circuit 8 performs three-dimensional filter processing using, for example, a frame comb filter to perform Y / C separation. The burst signal from the burst signal extraction circuit 4 is input to the burst clock generation circuit 5, where the first system clock (burst clock BCK) synchronized with the burst signal is generated.

The digital video signal from the A / D converter 3 is input to the horizontal synchronizing signal separation circuit 6, where the horizontal synchronizing signal is separated and output in synchronization with the line clock. Since the output of the A / D converter 3 is used for separating the horizontal synchronizing signal in this way, the sampling clock is a line clock synchronized with the horizontal synchronizing signal as described above. The horizontal sync signal from the horizontal sync signal separation circuit 6 is input to the line clock generation circuit 7, where the second system clock (line clock LCK) synchronized with the horizontal sync signal is generated.

The frequency of the burst clock BCK is
Usually, a frequency 4fs that is four times the subcarrier frequency fsc
c. Also, the frequency of the line clock LCK is 4f, which is the same as the burst clock BCK in the standard signal mode.
Although it is sc, it is slightly deviated in a non-standard signal mode such as VTR.

Next, the Y signal from the three-dimensional Y / C separation circuit 8 is input to the time axis conversion adjustment circuit 11 of the sampling rate conversion circuit 10. The C signal from the three-dimensional Y / C separation circuit 8 is input to the color demodulation circuit 9, where the color difference signal B-
Y and RY are demodulated, and the color difference signals BY and RY are
It is input to the time axis conversion adjustment circuits 12 and 13 of the sampling rate conversion circuit 10, respectively. Time axis conversion adjustment circuit 1
1, 12 and 13 are composed of a memory circuit or the like, and basically, input data are written by the burst clock BCK,
It has a function of reading with the line clock LCK.

Each time axis conversion adjusting circuit 11, 12, 1
The roles of 3 are the following 3 points. Burst clock sampling data is converted into line clock sampling data on the time axis. The video signal data is delayed by 1H. The data read timing is adjusted to match the later-described interpolation coefficient generation timing.

A control signal for this purpose is input from the control signal generating circuit 54 to each time axis conversion adjusting circuit 11, 12, 13. The control signal generation circuit 54 generates a control signal based on the signal from the phase error signal detection circuit 14. The detailed configuration and operation of these will be described later.

In the phase error signal detection circuit 14, A
From the burst clock sampling video signal from the / D converter 2, the cycle and phase error of each cycle of the horizontal synchronizing signal are detected. The interpolation coefficient generation circuit 15 generates interpolation coefficients k and 1-k for linear interpolation, which will be described later, based on the phase error signal from the phase error signal detection circuit 14. The interpolation coefficient generation circuit 15 uses, for example, a ROM (Read Only Memory) that receives a phase error signal as an address input. The interpolation coefficients k, 1-k from the interpolation coefficient generation circuit 15 are input to the linear interpolation circuits 16,17,18, where the Y signal and the color difference signal B from the time axis conversion adjustment circuits 11,12,13.
Linear interpolation is performed using -Y and RY. The Y, BY and RY signals from the linear interpolation circuits 16, 17 and 18 are
These signals have a sampling rate converted from the burst clock to the line clock, and these signals are next input to the wide conversion processing circuit 19.

In the wide conversion processing circuit 19, for example, processing such as wide conversion of an image including processing in scanning line units is performed based on the line clock LCK. The reproduction horizontal synchronization signal HD and the reproduction vertical synchronization signal VD, which are the synchronization signals necessary for the wide conversion processing, are reproduced by the synchronization signal reproduction circuit 25 based on the horizontal synchronization separation signal Hsy from the horizontal synchronization signal separation circuit 6, and widened. It is supplied to the conversion processing circuit 19. The Y, BY and RY signals after wide conversion are subjected to image quality adjustment, matrix conversion and other processing in the video signal output processing circuit 20. The output video signals R, G, B signals from the video signal output processing circuit 20 are converted into analog signals by the D / A converter 21 based on the system clock (line clock) LCK, and the video signal output terminals 22, Output to 23 and 24 respectively.

FIG. 2 is a diagram for explaining a video signal waveform (shown by an analog waveform) input to the sampling rate conversion circuit 10 of the present example shown in FIG. 1 and each operation signal timing. In the figure, H1, H2 and H3 represent continuous horizontal synchronizing signals, and D1 and D2 respectively represent Y signal data for one horizontal period. h1 and h2 indicate the periods of one horizontal period from the horizontal synchronizing signals H1 to H2 and H2 to H3, respectively, and measure the period from the trailing edge to the trailing edge of the horizontal synchronizing signal. This is performed by the phase error signal detection circuit 14 of FIG. Since the phase correction process in the sampling rate conversion circuit 10 is performed using one horizontal period error, for example,
The phase correction of the Y signal data D1 is performed at the timing R1 after detecting one horizontal period h1. Therefore, the data D1 needs to be delayed for about 1H period. The delay processing for that purpose is performed by the time axis conversion adjustment circuit 11 in FIG.

FIG. 3 shows horizontal synchronizing signals (H1, H2) necessary for converting and correcting the video signal data sampled by the burst clock BCK into the phase sampled by the line clock LCK in the phase error signal detection circuit 14. , ...) for detecting the phase error signal due to the fluctuation of the time axis.

In FIG. 3, continuous horizontal synchronizing signal H
Level differences L1, L2, L3, and L4 are measured with respect to continuous burst clock sample points (black circles in the figure) that sandwich a predetermined fixed threshold level L at the trailing edges of 1 and H2. As a result, the phase change Xl- of the horizontal synchronizing signal
1 and Xl can be calculated by Xl-1 = Tc * L1 / L2 Xl = Tc * L3 / L4, respectively. Here, Tc is 1 sampling period, 1
/ 4 fsc (sec), that is, about 70 nsec. The values of the phase changes Xl-1, Xl represent the phase difference within one clock of one cycle of the horizontal synchronizing signal.

Further, Y1 in FIG. 3 is the count value of the burst clock in one horizontal period, and for the phase difference of 1 clock or more, the clock count value is 910 in one horizontal cycle period of the standard signal. , Y1-910. Therefore, the total phase difference is (Y1-910 + X1-).
Xl-1), and the average phase difference per sample is
(Y1-910 + X1-X1-1) / 910.

Therefore, the phase correction amount for each unit sample (1 clock) of the video signal relating to the horizontal cycle period is z =
It becomes n (Y1-910 + X1-X1-1) / 910. Here, n increases to 1, 2, 3, ... For each sample (clock). Based on the average phase difference data per sample, the data sampled by the burst clock BCK is phase-corrected by the sampling rate conversion circuit 10.

FIG. 4 is a diagram showing an example of the phase error signal detection circuit 14 in the sampling rate conversion circuit 10 according to the phase difference detection method shown in FIG. In the figure,
26 is an input terminal for the burst clock BCK sampling video signal, 27 is an input terminal for the burst clock BCK,
28 is an output terminal of the signal S1 indicating an error in clock units, 29 is a phase variation detection circuit, 41 is an average phase difference data calculation circuit, 30 is an input terminal of a horizontal synchronization signal synchronized with the line clock LCK, and 31 is a line It is an input terminal of the clock LCK. Further, 32 is a cumulative adder and 33 is an OR
The circuit, 34 is a decoding circuit, 36 is an output terminal for a decode signal, and 35 is an output terminal for the above-mentioned average phase difference data z for each sample.

Next, the operation will be described. As described above, the phase fluctuation amount detection circuit 29 detects the frequency / phase shift of the horizontal synchronizing signal in one cycle period, and the average phase difference data calculation circuit 41 uses it to calculate the average phase difference data for each sample. To calculate. Phase fluctuation amount detection circuit 2 described above
In 9, the control signal S1 for adjusting the time axis in the time axis conversion adjusting circuits 11, 12, 13 is output to the output terminal 28. The average phase difference data z from the average phase difference data calculation circuit 41 is input to the cumulative adder 32, where the average phase difference data z is cumulatively added for each sample (line clock LCK unit). The maximum value of this cumulative addition value is
It is when the coefficient value for linear interpolation, which will be described later, becomes 1, and the decoding circuit 34 detects it.

Then, according to the maximum value decode detection signal output from the decoding circuit 34 and the horizontal synchronizing signal,
The cumulative adder 32 is reset via the OR circuit 33.
When the cumulative adder 32 is reset by the horizontal synchronizing signal, cumulative addition is restarted based on the next new phase difference data. When the cumulative adder 32 is reset by the maximum value decode detection signal from the decoding circuit 34,
The cumulative addition is continued again based on the previous phase difference data.

The cumulative addition data from the cumulative adder 32 is output to the output terminal 35 and input to the above-mentioned interpolation coefficient generating circuit 15. Further, the decode detection signal S2 from the decode circuit 34 is output to the output terminal 36 and used for adjusting the data transmission timing of the video signal in the time axis conversion adjusting circuit.

FIG. 5 is a diagram showing an example of the time axis conversion adjusting circuits 11, 12, 13 and the control signal generating circuit 54 in the sampling rate converting circuit 10 (here, for simplification of explanation). , Only the time axis conversion adjustment circuit 11 is shown as a representative). In this example shown in FIG.
A line memory is used as the time axis conversion adjustment circuit 11,
As the control signal generation circuit 54, the address control circuit of the line memory 11 is used.

In FIG. 5, reference numeral 37 is an input terminal for the burst clock sampling Y signal, 38 is an output terminal for the Y signal from the line memory 11 whose time axis conversion has been adjusted, 39 is an address counter for controlling write addresses, and 40 is a latch. A circuit, 42 is an input terminal of the burst clock BCK,
43 is an input terminal for the horizontal synchronizing signal Hsy. Also, 4
5 is an address counter for controlling read addresses, 46
Is a control circuit for outputting the counter 45, 47 is a delay adjustment circuit, 48 is an input terminal of the line clock LCK, and 49, 5
Reference numeral 0 is an input terminal for a control signal to the control circuit 46 and the delay adjustment circuit 47, respectively.

Next, the operation will be described. Input terminal 37
Burst clock sampling Y signal input from
It is written in the line memory 11 according to the address input value from the address counter 39 for controlling the write address. Here, the address counter 39 has an input terminal 42.
Since the counting operation is performed with the burst clock BCK from
The above input data is written in the line memory 11 in synchronization with the burst clock BCK. The horizontal synchronizing signal Hsy from the input terminal 43 is synchronized by the burst clock BCK in the latch circuit 40, and the synchronizing signal from the latch circuit 40 resets the address counter 39. With this reset timing, the line memory 11 starts writing data from the address 0.
That is, new Y signal data is written in the line memory 11 every horizontal period.

The data written in the line memory 11 as described above is then read according to the address input value from the read address control address counter 45. Here, the address counter 45 has an input terminal 48.
Since the counting operation is performed with the line clock LCK from, the data is read from the line memory 11 in synchronization with the line clock LCK. The read start timing is performed when the address counter 45 is reset. The reset signal is timing-adjusted by the delay adjustment circuit 47 by the control signal (S1 signal) from the input terminal 49 and input to the address counter 45. This read reset signal is one horizontal cycle (1
H) Delay more than this. Here, since it is necessary to match the multiplication timing with the predetermined interpolation count data in the later-described linear interpolation processing, the delay adjustment circuit 47 is provided as described above.

FIG. 6 shows the timing of each signal in the time axis conversion adjusting circuit (line memory) 11 described above. In the figure, (a) is a write Y to the line memory 11.
Signal data (H1 and H2 are horizontal synchronization signals), (b) is a write reset pulse, (c) is a read reset pulse, (d) is read Y signal data, and (e) is an interpolation coefficient (k) corresponding to read data. , 1-k) data generation timing, and (f) shows the output timing of the result obtained by multiplying the above-mentioned read data and coefficient data.

As described above, in order to match the multiplication timing of the read data (d) and the coefficient data (e),
Read reset pulse (c) in the delay adjustment circuit 47
Timing (Δt1, Δt2 in the figure) is adjusted. Also, the write data (D1, D2) shown in (a) is constant for one horizontal period 910 samples (at a sampling frequency of 4 fsc) at the time of the standard signal because of the burst clock sampling, but is shown at the time of the non-standard signal such as VTR , 911, 909, etc. are not constant. However, since the read data at the line clock rate is constant for 910 samples in one horizontal period, excess or deficiency of the read data occurs. The control circuit 46 in the control signal generation circuit 54 in FIG. 5 functions to compensate for it. That is, by holding or jumping the output value of the address counter 45 for several clocks, the deviation from the above-mentioned excess / deficiency data is eliminated, and the correspondence with the interpolation coefficient data in the subsequent stage can be taken. The control signal (the S2 signal) to the control circuit 46 is based on the sample number information obtained by the phase fluctuation amount detection circuit 29 described in FIG. 4 via the input terminal 50.

FIG. 7 is a diagram showing another example of the time axis conversion adjustment circuits 11, 12, 13 and the control signal generation circuit 54 in the sampling rate conversion circuit 10 (note that the explanation is also simplified here). Therefore, only the time axis conversion adjustment circuit 11 is shown as a representative). In the present example shown in FIG. 7, the line memory 36 is used as the time axis conversion adjustment circuit 11.
And the data holding / interlacing control circuit 62. Also,
The control signal generation circuit 54 includes the latch circuit 40, the delay adjustment circuit 47, and the timing control circuit 63. Hereinafter, the schematic operation of the present example will be described, focusing on the points different from the configuration example shown in FIG.

The line memory 36 has a built-in address counter and directly inputs the write clock BCK and the read clock LCK. Further, the write reset signal (WR) serving as a write start reference is input from the latch circuit 40 described above with reference to FIG. Next, the read data generation timing is adjusted by directly adjusting the read reset (RR) of the line memory 36 with the signal from the delay adjustment circuit 47 described above with reference to FIG. Hold read data corresponding to write / read sample number mismatch in clock units,
The interlace control is performed by the data holding / interlacing control circuit 62. The data holding / interlacing control circuit 62 is provided in the subsequent stage of the line memory 36.

By the time axis conversion adjusting circuit 11 and the control signal generating circuit 54 having the above-described configurations, it is possible to obtain the same effects as those of the configuration example of FIG. 5 as described in the signal timing diagram of FIG.

5 and 7, the time axis conversion adjusting circuit 11 used for the Y signal is shown as the time axis conversion adjusting circuit, but it is used for the color difference signals BY and RY. The circuits 12 and 13 have exactly the same configuration and operation.

FIG. 8 is a diagram showing an example of the linear interpolation circuits 16, 17 and 18 in the sampling rate conversion circuit 10 (here, for the sake of simplification of description, the linear interpolation circuit 1 is omitted). One of them is shown as a representative, but each linear interpolation circuit has exactly the same configuration and operation).

In FIG. 8, 64 is an input terminal for video signal data from the time axis conversion adjusting circuit 11 (or 12 or 13), 65 is a 1-sample delay circuit, 66 and 67 are multipliers, and 68 and 69 are FIG. The input terminals of the coefficient data k and 1-k from the interpolation coefficient generation circuit 15 shown in (1), 70 is an adder, and 71 is an output terminal.

Line clock LC from the input terminal 64
The video signal data sampled in K is multiplied by the multiplier 66.
Is multiplied by the coefficient data k. In addition, the delay circuit 65
The sampling data by the line clock LCK delayed by the sample is multiplied by the coefficient data 1-k in the multiplier 67. Then, the multiplication outputs from these two multipliers 66 and 67 are added by the adder 70 and input to the wide conversion processing circuit 19 shown in FIG. 1 via the output terminal 71.

FIG. 9 shows a state of the linear interpolation operation described above. That is, in FIG. 9, from two consecutive video signals {In, In + 1}, {In + 1, In + 2}, ... Which are burst clock sample points indicated by black circles, a clock BCK and a clock LCK are generated. By using the linear interpolation coefficients k and 1-k corresponding to the phase difference, line clock sample points On, On + 1 and On newly indicated by white circles are newly added.
Interpolate +2, ... Here, On = k × (In + 1)
It becomes + (1-k) * In.

10 and 11 are diagrams for supplementarily explaining the effect of the video signal phase correction processing by the sampling rate conversion device of the present invention. For example, when the input is a non-standard signal, when the data is directly read by the burst clock without performing the sampling rate conversion of the present invention, the number of read samples increases or decreases from the standard value of 910, and the phase is synchronized with the line clock. Absent. Therefore, as shown in FIG. 10, the image sample points are shifted obliquely with respect to the horizontal direction of the screen.

In order to eliminate such a problem, the sampling rate conversion device of the present invention performs the sampling rate conversion processing as described above. That is,
In the sampling rate conversion device of the present invention, re-sampling is performed with the line clock LCK for the reproduced horizontal synchronizing signal,
In addition, by performing the phase correction, the image data in which the number of samples is fixed to 910 in one horizontal period and the phase is uniform is reproduced. FIG. 11 shows a reproduced image after the conversion of the sampling rate, which is an image in which the phases are aligned in the horizontal direction.

In the description of the digital video signal processing device of FIG. 1, the horizontal sync signal separation circuit 6 and the line clock generation circuit 7 have a digital circuit configuration, and therefore the digital composite video input to the horizontal sync signal separation circuit 6 is input. The signal must be sampled with the line clock LCK. Therefore, in addition to the A / D converter 2 for sampling the video signal data, the A / D converter 3 dedicated to the sync separation processing is provided. However, in addition to this configuration example, if an analog signal format is adopted as the horizontal synchronizing signal separation circuit 72 and the line clock generating circuit 73 as shown in FIG. 12, for example, the horizontal synchronizing signal separation circuit 72 from the video signal input terminal 1 is adopted. Even if the analog composite video signal is directly input to, the line clock LCK synchronized with the horizontal synchronizing signal can be reproduced at the terminal 74.

[0048]

Since the present invention is configured as described above, it is possible to perform signal processing with an optimum clock in a television receiver regardless of whether the input video signal is a standard or non-standard signal. You can For example, a burst lock clock signal required for Y / C separation and color demodulation, and a line lock clock signal required for signal processing including scanning line processing such as wide processing can be used to perform the respective processing, which is not standard as in VTR reproduction. It is possible to realize a video signal sampling rate conversion device capable of reproducing high quality video even when a signal is input.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a digital video signal processing device to which a video signal sampling rate conversion device according to an embodiment of the present invention is applied.

FIG. 2 is an explanatory diagram showing input video signal waveforms and operation signal timings in FIG.

FIG. 3 is an explanatory diagram showing a phase error detection method in the sampling rate conversion circuit in FIG.

4 is a configuration diagram showing an example of a phase error signal detection circuit in the sampling rate conversion circuit in FIG.

5 is a configuration diagram showing an example of a time axis conversion adjustment circuit and a control signal generation circuit in the sampling rate conversion circuit in FIG.

6 is an explanatory diagram showing signal timings and operations in time-axis conversion adjustment according to the configuration example of FIG.

7 is a configuration diagram showing another example of a time axis conversion adjustment circuit and a control signal generation circuit in the sampling rate conversion circuit in FIG.

8 is a configuration diagram showing an example of a linear interpolation circuit in the sampling rate conversion circuit in FIG.

9 is an explanatory diagram showing a linear interpolation operation according to the configuration example of FIG.

FIG. 10 is an explanatory diagram showing a reproduced image when sampling rate conversion is not performed for a non-standard signal.

FIG. 11 is an explanatory diagram showing a reproduced image when sampling rate conversion is performed for a non-standard signal.

12 is a configuration diagram showing another example of a horizontal synchronizing signal separation circuit and a line lock clock signal generation circuit in the digital video signal processing device of FIG.

[Explanation of symbols]

 1 Video signal input terminal 2, 3 A / D converter 4 Burst signal extraction circuit 5 Burst lock clock signal generation circuit 6 Horizontal synchronization signal separation circuit 7 Line lock clock signal generation circuit 8 3D Y / C separation circuit 9 Color demodulation circuit 10 Sampling rate conversion circuit 11, 12, 13 Time axis conversion adjustment circuit 14 Phase error signal detection circuit 15 Interpolation coefficient generation circuit 16, 17, 18 Linear interpolation circuit 19 Wide conversion processing circuit 20 Video signal output processing circuit 21 D / A conversion Device 22, 23, 24 Video signal output terminal 25 Synchronous signal reproduction circuit 29 Phase fluctuation amount detection circuit 32 Cumulative adder 33 OR circuit 34 Decode circuit 36 Line memory 39, 45 Address counter 40 Latch circuit 41 Average phase difference data calculation circuit 46 Control circuit 47 Delay adjustment circuit 54 Control signal generation times 62 Data retention / interlace control circuit 63 timing control circuit 65 one-sample delay circuits 66 and 67 multiplier 70 adder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yumi Saeki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Hitachi, Ltd., Multimedia Systems Development Division (72) Inventor Ichio Nakagawa Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshida-cho Hitachi, Ltd. Multimedia system development headquarters

Claims (5)

[Claims] 1. A means for separating a horizontal synchronizing signal included in an input video signal, a means for extracting a color burst signal, and a means for generating a first clock signal of a predetermined frequency synchronized with the color burst signal. Means for generating a second clock signal of a predetermined frequency synchronized with the horizontal synchronizing signal, video signal sampling means for sampling the input video signal with the first clock signal, and sampling by the video signal sampling means Time axis conversion adjusting means for converting the video signal into a time axis rate based on the second clock signal and adjusting the sending timing of the video signal data in sample units, and an image from the video signal sampling means. Separately output the phase error from the standard value based on the time base fluctuation of the horizontal sync signal included in the signal. Means for detecting with reference to the phase of the horizontal synchronizing signal, control signal generating means for adjusting the data transmission timing in the time axis conversion adjusting means in sample units based on the phase error signal, and the phase error signal. A video signal comprising means for generating an interpolation coefficient for linear interpolation based on the above, and means for linearly interpolating using the video signal data from the time axis conversion adjusting means and the interpolation coefficient. Sampling rate converter. 2. The horizontal synchronizing signal separating means according to claim 1, further comprising means for sampling the input video signal with the second clock signal, and separating and outputting the horizontal synchronizing signal included in the sampling video signal. A video signal sampling rate conversion device characterized by: 3. The color burst signal extracting means according to claim 1, wherein the color burst signal extracting means uses a video signal from the input video signal sampling means based on the first clock signal, and based on the first clock signal. A video signal sampling rate conversion device characterized by extraction. 4. The time axis conversion adjusting means according to claim 1, further comprising a memory means having a delay function of 1H (1 horizontal scanning period) or more, and the first clock from the control signal generating means. Based on a write address control signal synchronized with a signal and a read address control signal synchronized with the second clock signal, write video signal data is read with a delay of 1H or more and the data transmission timing is controlled for each sample unit. A video signal sampling rate conversion device characterized by the above. 5. The phase error detection means according to claim 1, wherein a phase variation amount of a horizontal synchronizing signal based on the first clock signal sampling with respect to a standard signal time period is synchronized with the second clock signal. 1
Phase fluctuation amount detecting means for detecting each horizontal period, means for calculating an average phase difference for each sample based on the detected phase fluctuation amount, and the calculated average phase difference is accumulated for each second clock signal. And a means for adding, wherein the interpolation coefficient generation means is synchronized with the second clock signal based on the cumulative addition data, and generates an interpolation coefficient for each clock signal. Signal sampling rate converter.