JP3430156B2 - Sampling frequency conversion device, sampling frequency conversion method, video signal processing device, and video signal processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for separating a television signal into Y (luminance) / C (color) signals and outputting them as digital video signals, and more particularly to rate conversion and rate conversion of digital video signals. It relates to generation of a clock used for conversion.

[0002]

2. Description of the Related Art A conventional video signal processing apparatus for separating an analog television signal into a Y (luminance) / C (color) signal, converting it into a digital video signal and outputting the same will be described below with reference to the drawings. To do.

FIG. 9 is a block diagram of a conventional video signal processing device. FIG. 10 is a waveform diagram of a video signal, where (a) is a video signal, (b) is a synchronization signal, and (c) is a burst signal. FIG. 11 is an explanatory diagram of Y / C separation. (A) is a video signal, (b) is a Y (luminance) signal, and (c) is a C (color).
It is a signal.

As shown in FIG. 9, a conventional video signal processing device has an analog television signal input terminal 101, a first digital video signal output terminal 102, and a first A / A terminal.
D conversion circuit 103 and sync separation / burst detection circuit 10
4, a burst lock clock generation circuit 105, Y /
C separation circuit 106, color decoding circuit 107, TBC
The circuit 108, the frequency dividing circuit 112, the vertical / horizontal signal generation circuit 113, the multiplexing circuit 114, and the D / A conversion circuit 11
5, the second A / D conversion circuit 116, and the sync separation circuit 1
17, a horizontal synchronization clock generation circuit 118, a second digital video signal output terminal 201, a DVC preprocessing circuit 202, and a frame synchronization clock generation circuit 205.

The operation of the video signal processing device configured as described above will be described below. The analog television signal input terminal 101 is connected to the analog television signal S1.
This is an input terminal for inputting 01. Among analog television signals, there are standard television signals stipulated in standards such as broadcasting, and, for example, television signals reproduced on a VCR, the frequency of the synchronizing signal is shifted or jitter is included. Some television signals may be out of order, and some non-standard television signals are not standard television signals.

First digital video signal output terminal 102
Is a digital interface standard ITU-R recommendation BT. Y (luminance) signal, Cr (color difference-red) signal at a bit rate of 27 MHz, which is a transmission format of 656,
The first digital video signal S102 in which the Cb (color difference-blue) signal and the synchronization signal are multiplexed is output to a device or equipment connected to this video signal processing device.

The first A / D conversion circuit 103 samples the analog television signal S101 with a burst lock clock S105 of 14.3 MHz, which will be described later, and converts it into a digital television signal S103.
Further, the first A / D conversion circuit 103 samples the analog television signal S101 by, for example, 28.6 MH.
It is also possible to use the z burst lock clock.

The sync separation / burst detection circuit 104 includes a digital television signal S103 shown in FIG.
Therefore, the synchronization signal S104a shown in FIG. 10B is separated by a certain threshold value. A burst signal S104b of 3.58 MHz multiplexed as a reference signal for color reproduction shown in FIG. 10C is extracted from the separated sync signal.

Burst lock clock generation circuit 105
Is a burst lock clock S105 of 14.3 MHz obtained by multiplying the burst signal S104b of 3.58 MHz by 4.
To generate.

The Y / C separation circuit 106 outputs the digital television signal S103 shown in FIG. 11A, in which the Y (luminance) signal and the C (color) signal are frequency-multiplexed, as shown in FIG.
Y signal S106a shown in FIG. 11 and C signal S shown in FIG.
Convert to 106b. Here, when the input analog television signal is a standard television signal, the still image portion uses the frame memory to perform three-dimensional processing by utilizing the fact that the color phase is inverted in frames / lines, and The unit performs two-dimensional processing using a line filter.

The color decoding circuit 107 includes a Cr signal and a Cb signal.
Since the signals are out of phase with each other by 90 °, the digital C signal S106b is replaced with the digital Cr signal S107a.
And a digital Cb signal S107b.

TBC (Time Base Corrector) circuit 1
08 detects the time of the horizontal synchronizing signal of the synchronizing signal S104a, converts the Y signal S106a, the Cr signal S107a, and the Cb signal S107b according to the length of the horizontal synchronizing signal of the synchronizing signal S104a, and outputs the Y signal S108a and the Cr signal. S1
08b and Cb signal S108c is output.

The D / A conversion circuit 115 is the TBC circuit 10.
Y signal S10 which is a digital signal and is output from 8
8a, Cr signal S108b, Cb signal S108c, Y signal S115a and Cr signal S115 which are analog signals.
b, Cb signal S115c is converted.

The second A / D conversion circuit 116 has a Y signal S
115a, Cr signal S115b, and Cb signal S115c are sampled at a 13.5 MHz clock S112 described later, and a Y signal S1 that is a digital signal is sampled.
16a, Cr signal S116b, Cb signal S116c. The Cr signal and the Cb signal are multiplexed before being input to the second D / A conversion circuit 115, and the D / A conversion circuit 11
5 and the second A / D conversion circuit 116, the Y signal and C
The signal may be converted. Also, the second A / D
The conversion circuit can also perform sampling with a clock of 27 MHz, for example.

The sync separation circuit 117 has a Y signal S116a.
To horizontal sync signal S117a and vertical sync signal S117b
And are separated and output.

The horizontal synchronizing clock generating circuit 118 outputs the 27 MHz horizontal synchronizing clock S118 synchronized with the horizontal synchronizing signal S117a to the frequency dividing circuit 112 and the multiplexing circuit 114. The horizontal synchronization clock generation circuit 118 is generally composed of an analog PLL circuit.

The frequency dividing circuit 112 divides the horizontal synchronizing clock S118 of 27 MHz into 13.5 MHz. This one
The 3.5 MHz clock S112 is the second A /
The sampling clock is input to the D conversion circuit 116.

The vertical / horizontal signal generation circuit 113 outputs the horizontal sync signal S117a and the vertical sync signal S117b from the BT.
Sync signal S113 corresponding to the transmission format of 656
Is generated and output.

The multiplexing circuit 114 outputs the Y signals S116a, C.
The r signal S116b, the Cb signal S116c, and the synchronization signal S113 are multiplexed with the horizontal synchronization clock S118 of 27 MHz and output as the first digital video signal S102. The first digital video signal S102 is output from the first digital video signal output terminal 102 to a device or a device connected to the video signal processing device.

Second digital video signal output terminal 201
Is an output terminal for outputting a second digital video signal S201 in which a Y signal, a Cr signal, and a Cb signal are multiplexed at 18 MHz. The second digital video signal S201 is a DCT (Discrete Cosine Tr) that performs compression / expansion within a frame.
ansform) block, is processed at 18 MHz, and then recorded / reproduced in a block for recording / reproducing on a tape.

The DVC preprocessing circuit 202 includes a second A / D
The 13.5 MHz Y signal S116a, Cr signal S116b, and Cb signal S1 output from the conversion circuit 116.
16c is multiplexed based on an 18 MHz clock S205 synchronized with one frame described later and output as a second digital video signal S201. At this time, the DVC preprocessing circuit 202 expands the Y signal S116a into a Y signal of 18 MHz, and the Cr signal S116b and the Cb signal S116c.
Is thinned to 9 MHz, and then multiplexed.

The frame synchronization clock generation circuit 205
Vertical sync signal S11 output from sync separation circuit 117
18MHz synchronized with one frame, which is twice as much as 7b
The clock S205 is generated and output. The frame synchronization clock generation circuit 203 is generally an analog PL.
It is composed of L circuits.

[0023]

However, in the above-mentioned conventional video signal processing apparatus, the digital Y signal of 14.3 MHz, the digital Cr signal and the digital Cb signal are converted to the digital Y signal of 13.5 MHz and the digital C signal.
To convert the rate of r signal to digital Cb signal, 2
It is necessary to externally provide an analog PLL circuit such as the horizontal synchronization clock generation circuit 118 that generates the 7 MHz horizontal synchronization clock S118. In addition, 13.5 MHz digital Y signal, digital Cr signal, digital Cb
Signal is 18MHz digital Y signal, digital Cr
An analog PLL such as a frame synchronization clock generation circuit 205 which generates a clock S205 of 18 MHz even in the case of rate conversion into a signal and a digital Cb signal for multiplexing.
A circuit is needed.

As described above, in the above-mentioned conventional video signal processing apparatus, it is necessary to externally provide an analog PLL circuit in order to perform rate conversion of a digital video signal, and therefore the circuit (component) scale is increased and the LSI is increased. However, there is a problem that it is difficult to integrate. Therefore, it is an object of the present invention to provide a video signal processing device and a video signal processing method that have a small circuit scale and that facilitate LSI integration.

A sampling frequency conversion device according to claim 1 of the present invention receives a first digital video signal sampled by a first clock signal having a first frequency as an input, and 1 digital video signal is interpolated to calculate a second digital video signal in which the effective pixel period in one horizontal period is N times (N> 0) while the length and sampling frequency of one horizontal period remain unchanged. Then, the first digital video signal is converted into the second digital video signal, and is output based on the first clock signal.
Clock signal generating means for generating a second clock signal having a second frequency that is 1 / N times that of the clock signal, and storing the second digital video signal, and storing the stored second digital video signal. Is read by the second clock signal and is output as a third digital video signal.

The video signal processing apparatus according to claim 2 of the present invention is an A / D for sampling an analog video signal with a first clock signal having a first frequency and converting it into a first digital video signal. A conversion circuit; a sync signal separation means for separating a first sync signal from the analog video signal; a first clock generation means for generating the first clock signal from the first sync signal; And a sampling frequency conversion device for converting the second digital video signal into a second digital video signal and outputting the second digital video signal based on a second clock signal having a second frequency. The sampling frequency conversion device interpolates the first digital video signal, and the length of one horizontal period and the sampling frequency remain unchanged. The effective pixel period during the period is N times (N>
0) the second digital video signal is calculated, the first digital video signal is converted into the second digital video signal, and the first digital digital signal is output based on the first clock signal. Converting means, second clock generating means for generating a second clock signal having a second frequency that is 1 / N times the first clock signal, and storing the second digital video signal Storage means for reading the stored second digital video signal with the second clock signal and outputting it as a third digital video signal.

A video signal processing apparatus according to a third aspect of the present invention is the video signal processing apparatus according to the second aspect, wherein the second clock signal is multiplied to obtain a third clock signal having a third frequency. And a frequency dividing means for dividing the third clock signal to generate a fourth clock signal having a fourth frequency, and the third digital video signal for the fourth digital signal. Second digital-to-digital conversion means for converting into a fourth digital video signal based on the clock signal of.

A video signal processing device according to a fourth aspect of the present invention is a synchronization comparison for comparing a phase of the first synchronization signal with a phase of a second synchronization signal generated from the second clock signal. Means for storing the second means,
And storing the stored second digital video signal in the second unit.
Read in frame units based on the clock signal of
First frame storing means for outputting as the digital video signal of the above, and the second digital video signal for each frame, and the stored second digital video signal for the frame based on the second clock signal. Second frame storage means for reading out in units and outputting as a fifth digital video signal, the fourth digital video signal and the fifth digital video signal as inputs,
Switching means for alternately switching the fourth digital video signal and the fifth digital video signal and outputting the third digital video signal as the third digital video signal. When it is detected that the phase has passed the phase of the second synchronization signal, the fourth digital video signal or the fifth digital video signal is repeatedly output twice as the third digital video signal. When it is detected that the phase of the second synchronizing signal has passed the phase of the first synchronizing signal, the switching signal instructing to the fourth digital video signal or the fifth digital video signal is detected. A switching signal instructing deletion of one frame is output to the switching means, and the switching means outputs the fourth digital video signal based on the switching signal. Or and outputs a digital video signal of the fifth as the third digital video signal.

A sampling frequency conversion method according to a fifth aspect of the present invention receives as input a first digital video signal sampled with a first clock signal having a first frequency, After the interpolation process, the length of one horizontal period and the sampling frequency remain unchanged, and the effective pixel period in one horizontal period is N times (N> 0).
A digital-to-digital conversion step of calculating the second digital video signal, converting the first digital video signal into the second digital video signal, and outputting the second digital video signal based on the first clock signal. A clock generating step of generating a second clock signal having a second frequency which is 1 / N times the first clock signal;
And storing the digital video signal, and storing the second digital video signal with the second clock signal to output the second digital video signal as a third digital video signal.

A video signal processing method according to a sixth aspect of the present invention is an A / D conversion step for sampling an analog video signal with a first clock signal having a first frequency and converting it into a first digital video signal. A sync signal separation step of separating a first sync signal from the analog video signal; a first clock generation step of generating the first clock signal from the first sync signal; The video signal is interpolated to calculate a second digital video signal in which the length of one horizontal period and the sampling frequency remain unchanged and the effective pixel period in one horizontal period is N times (N> 0). A first digital-digital conversion step of converting a first digital video signal into the second digital video signal and outputting the second digital video signal based on the first clock signal; A second clock generating step of generating a second clock signal having a second frequency which is 1 / N times the first clock signal; storing the second digital video signal, and storing the second digital video signal. A storage step of reading the second digital video signal with the second clock signal and outputting it as a third digital video signal.

The video signal processing method according to claim 7 of the present invention is the video signal processing method according to claim 6, wherein the second clock signal is multiplied to obtain a third clock signal having a third frequency. A multiplying step for generating
Divides the clock signal of to obtain a fourth frequency having a fourth frequency.
And a second digital-to-digital conversion step of converting the third digital video signal into a fourth digital video signal based on the fourth clock signal. It is characterized by including.

The video signal processing method according to claim 8 of the present invention is the video signal processing method according to claim 6, wherein the phase is generated from the phase of the first synchronization signal and the second clock signal. A synchronization comparing step of comparing the phase of the second synchronizing signal with the phase of the second synchronizing signal;
And storing the stored second digital video signal in the second unit.
Read in frame units based on the clock signal of
A first frame storing step of outputting the second digital video signal as a digital video signal, storing the second digital video signal in a frame unit, and storing the stored second digital video signal in a frame unit based on the second clock signal. The second frame storing step of reading out by the above and outputting as the fifth digital video signal, and the fourth digital video signal and the fifth digital video signal as inputs, and the fourth digital video signal and the fourth digital video signal. And a switching step of alternately switching the digital video signal of No. 5 and outputting as the third digital video signal. In the synchronous comparing step, the phase of the first synchronous signal is
When it is detected that the phase of the second synchronization signal is overtaken, the fourth digital video signal or the fifth digital video signal is detected.
It is detected that the phase of the second synchronization signal has passed the phase of the first synchronization signal of the switching signal instructing to repeatedly output the digital video signal of 2 as the third digital video signal. When it does, a switching signal instructing to delete the fourth digital video signal or the fifth digital video signal for one frame is output, and the switching step is based on the switching signal, and the fourth digital video signal is output. A video signal or the fifth digital video signal is output as the third digital video signal.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a video signal processing device 100 according to the first embodiment. FIG. 2 is a block diagram of the DD conversion circuit. Figure 3 is D
It is operation | movement explanatory drawing of a D conversion circuit.

As shown in FIG. 1, the video signal processing device 10
Reference numeral 0 denotes an analog television signal input terminal 101, a first digital video signal output terminal 102, an A / D conversion circuit 103, a sync separation / burst detection circuit 104,
Burst lock clock generation circuit 105, Y / C separation circuit 106, color decoding circuit 107, TBC circuit 1
08, a DD (Digital-Digital) conversion circuit 109,
It has a first frame memory circuit 110, a free-run clock generating circuit 111, a frequency dividing circuit 112, a vertical / horizontal signal generating circuit 113, and a multiplexing circuit 114. In addition, in the video signal processing device 100 shown in FIG.
The same components as those of the conventional video signal processing device shown in FIG.

The first embodiment is the D / A conversion circuit 115 and the second A / D conversion circuit 1 of the conventional video signal processing device.
16, a sampling frequency conversion circuit 1000 having a DD conversion circuit 109, a first frame memory circuit 110, and a free-run clock generation circuit 111 is newly provided instead of the horizontal synchronization clock generation circuit 118. To do.

The DD conversion circuit 109 outputs the Y signal S108.
a, Cr signal S108b, Cb signal S108c are interpolated, and DD conversion Y signal S109a, DD conversion Cr signal S109c, and DD conversion Cb signal S109e are output.
At the same time, the DD conversion circuit 109 also outputs a DD conversion Y signal enable signal S109b, a DD conversion Cr signal enable signal S109d, and a DD conversion Cb signal enable signal S109f. At this time, the DD conversion circuit 109
Of the sampling data of the Y signal S108a, the Cr signal S108b, and the Cb signal S108c locked to the burst clock S105 of 14.3 MHz is 13.5 M.
Converted to sampling data locked to the Hz free-run clock S112. That is, the effective pixel period in one horizontal period of the video signal of 14.3 MHz is 764 samples, while the effective pixel period in one horizontal period of the video signal of 13.5 MHz is 720 samples. The DD conversion circuit 109 converts the effective pixel period in one horizontal period of the Y signal S108a, Cr signal S108b, and Cb signal S108c from 764 samples to 720 samples.

As shown in FIG. 2, the DD conversion circuit 109
Is an interpolation position detection circuit 1091 and a coefficient selection circuit 109
2 and a DD interpolation filter 1093. The synchronization signal S104a is input to the interpolation position detection circuit 1091, and the Y signal S108a is input to the DD interpolation filter 1093.

The DD conversion circuit 10 configured as described above
9, the operation will be described with reference to FIG. 3. In FIG. 3, (a) and (b) are data waveform diagrams, and (c) is a Y signal S10.
8a and (d) are addition outputs, (e) is a DD conversion Y signal enable signal S109b, and (f) is a DD conversion Y signal S1.
It is 09a.

14.3 input to the DD conversion circuit 109
The sampling data of the Y signal S108a of MHz is shown by ● (Din *) in FIG.
Sampling data when converting to 3.5MHz △
(Dout *). The interpolation position detection circuit 1091
When the Y signal S108a is 13.5 MHz, the number of samples in one horizontal period is 910, and when the Y signal S108a is 14.3 MHz, the number of samples in one horizontal period is 85.
Since there are 8 samples, the counter is composed of 910, the constant is set to 858, the constant 858 and the value one clock before are counted at the clock of 14.3 MHz, and the addition result is added output S1091 as shown in FIG. Output as shown by ○. It should be noted that the value one clock before is the addition output S1 output one clock before from the counter.
It refers to 091. Further, when the addition result overflows 910, the counter outputs the DD conversion Y signal enable signal S109b as shown in FIG. 3 (e). Here, assuming that the data of Din0 is 0, Din
0, Din1, Din2, Din3, Din4, Din
5 ,. ． , Din909, Din910 corresponding to the addition output S1091 of the interpolation position detection circuit 1091 is 0, 8
58,806,754,702,650 ,. ． , 52,
It becomes 0. Similarly, enable signal S1 for DD conversion Y signal
09b is 1,0,1,1,1,1 ,. ． , 1,1. Further, the counter is reset by the synchronization signal S104a.

The coefficient selection circuit 1092 is, for example, 910.
Is divided into 64, it is calculated which value of 0 to 63 the output S1091 of the interpolation position detection circuit 1091 is,
Corresponding interpolation filter coefficients α, β, γ, δ are selected and output. Here, the Y signal S108 of 14.3 MHz
The sampling data of a is 69,84 nsec interval,
For example, when divided into 64, it becomes 1.09 nsec. Generally, in the case of a television signal, an error of about 1 nsec is set as the detection limit. The interpolation filter 1093 uses the Y signal S108a.
Is calculated with the coefficients α, β, γ and δ of the interpolation filter, and a DD converted Y signal S109a is output. For example, Dout3 of the DD conversion Y signal S109a is
As shown in the data waveform diagram in (b), α * Din2 + β *
It is calculated as Din3 + γ * Din4 + δ * Din5.

Similarly, the DD conversion circuit 109 converts the input Cr signal S108b to the DD conversion Cr signal S109c and the DD conversion Cr signal enable signal S109d from the input Cb signal S108c to the DD conversion Cb signal S.
109e and enable signal S109 for DD conversion Cb signal
f and are generated.

The frame memory circuit 110 uses the DD conversion Y
The signal S109a, the DD conversion Cr signal S109c, the DD conversion Cb signal S109e, the DD conversion Y signal enable S109b, and the DD conversion Cr signal enable signal S10.
9d, when the DD conversion Cb signal enable signal S109f is enabled (Hi), it is written by the 14.3 MHz burst lock clock S105, and each written signal is 13.5 MHz which is the output of the frequency dividing circuit 112 described later.
Free run clock S112 for reading and Y signal S1
10a, Cr signal S110b, and Cb signal S110c.

Hereinafter, the Y signal 108a is the DD conversion Y signal S.
109a, the DD conversion Y signal S109a is changed to the Y signal S11.
The state of conversion into 0a will be described with reference to FIG.

Y signal S input to the DD conversion circuit 109
As shown in FIG. 4A, 910 of 108a are sampled by the burst lock clock of 14.3 MHz, and the effective pixel period is 764 samples in one horizontal period.
The blanking period is 146 samples. Y signal S1
The DD conversion circuit 109 converts the effective pixel period 08a into 720 samples and the blanking period 190 samples in one horizontal period, as shown in FIG.
It is output as a D conversion Y signal S109a. At this time,
The number of samples in one horizontal period is not converted.

Further, the DD conversion Y signal S109a is written in the frame memory circuit 110 at a burst clock of 14.3 MHz and then read at a free-run clock of 13.5 MHz, as shown in FIG. 4 (c). In the Y signal S110a, the number of horizontal periods is 858 samples, the effective pixel number period is 720 samples, and the blanking period is 138 samples.

Similarly, the Cr signals S108b, C
The b signal S108c is a DD conversion Cr signal 109b, DD
The converted Cb signal 109c is added to the DD converted Cr signal 109b,
The DD-converted Cb signal 109c is the Cr signals S110b, Cb.
It is converted into the signal S110c.

As described above, the DD conversion circuit 109 and the frame memory circuit 110 convert the 14.3 MHz digital Y signal, digital Cr signal, and digital Cb signal into
It is converted into a 13.5 MHz digital Y signal, digital Cr signal, and digital Cb signal.

Further, the write / read clocks of the frame memory circuit are the same, a small capacity memory is provided in the subsequent stage, and the write clock for this small capacity memory is set to 1
4.3MHz, read clock 13.5MHz
Then, the rates of the digital Y signal, the digital Cr signal, and the digital Cb signal can be converted.

The free-run clock generating circuit 111 generates a free-run clock S111 of 27 MHz by a crystal oscillator, for example. Here, it is necessary to secure the accuracy of the crystal in order to generate a stable free-run clock.

The frequency dividing circuit 112 divides the 27 MHz free-run clock S111 by two to generate a 13.5 MHz free-run clock S112.

The vertical / horizontal synchronization signal generation circuit 113 includes a horizontal counter (858 counter) and a frame counter.
It has a (525 counter), and the 858 counter generates the horizontal synchronizing signal S113a based on the 13.5 MHz free-run clock S112, and the 525 counter generates the vertical synchronizing signal S113b based on this horizontal synchronizing signal.

The multiplexing circuit 114 is the frame memory circuit 1.
Y signal S110a and Cr signal S11 output from 10
0b, Cb signal S110c and horizontal synchronization signal S113a,
And the vertical synchronization signal S113b are multiplexed with the free-run clock S111 of 27 MHz, and the first digital video signal output terminal 102 is provided as the first digital video signal S102.
Output to.

As described above, according to the video signal processing device of the first embodiment, the sampling frequency conversion circuit including the DD conversion circuit 109, the first frame memory circuit 110, and the free-run clock generation circuit 111. Since 1000 is provided, a digital Y signal, a digital Cr signal, and a digital Cb signal of 14.3 MHz can be transmitted at 13.5 MHz without an external analog PLL circuit that generates a horizontal synchronization clock synchronized with the horizontal synchronization signal. Digital Y signal, digital Cr signal, digital Cb
It can be converted into a signal.

(Second Embodiment) FIG. 5 is a block diagram of a video signal processing device 200 according to the second embodiment. In the video signal processing device 200 shown in FIG. 5, the same components as those of the video signal processing device 100 shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In addition, the video signal processing device 2
Since the block 120 of 00 has the same constituent elements as the block 120 of the video signal processing device 100,
The description is omitted.

The video signal processing device 200 is different from the video signal processing device 100 in that a DVC preprocessing circuit 202, a multiplication circuit 203, and a frequency dividing circuit 204 are newly provided. Hereinafter, the DVC preprocessing circuit 202 and the multiplication circuit 20
3 and the frequency dividing circuit 204 will be described.

The multiplication circuit 203 multiplies the 27 MHz clock output from the free-run clock generation circuit 111 by 2, for example, and outputs a 54 MHz clock S113.
The frequency divider circuit 204 outputs 54M which is the output of the frequency multiplier circuit 203.
For example, the frequency of the clock S203 of Hz is divided by 3 to obtain 18 MHz.
The z clock S204 is generated.

The DVC preprocessing circuit 202 is 13.5 MHz.
The Y signal S110a, the Cr signal S110b, and the Cb signal S110c of z are multiplexed by the clock S204 of 18 MHz,
The second digital video signal S201 is output to the second digital video signal output terminal 201. At this time, the DVC pre-processing circuit 202 outputs the Y signal S110a to Y of 18 MHz.
Signal, expanded to Cr signal S110b and Cb signal S1
10c is thinned out to 9 MHz and multiplexed.

Further, the second digital video signal S201
Is a DCT (Discrete Cosine Tr) for performing compression / expansion within a frame from the second digital video signal output terminal 201.
ansform) block, is processed at 18 MHz, and then recorded / reproduced in a block for recording / reproducing on a tape.

As described above, according to the video signal processing device of the second embodiment, the free-run clock generation circuit 111 is used.
Since the multiplication circuit 203 for multiplying the 27 MHz clock generated by the frequency division circuit by 2 and the frequency division circuit 112 for dividing the 54 MHz clock generated by the multiplication circuit 203 by 3 are provided,
A digital Y signal of 13.5 MHz, a digital Cr signal, and a digital Cb signal can be converted into an 18 MHz digital Y signal, a digital Cr signal, and a digital C signal without an external analog PLL circuit synchronized with one frame.
b signal.

(Third Embodiment) FIG. 6 is a block diagram of a video signal processing device 300 according to the third embodiment. In the video signal processing device 300 shown in FIG. 6, the same components as those of the video signal processing device 100 shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In addition, the video signal processing device 3
Since the block 120 of 00 has the same constituent elements as the block 120 of the video signal processing device 100, the description thereof will be omitted.

The video signal processing device 300 is different from the video signal processing device 100 in that the second frame memory circuit 30 is used.
1, a switching circuit 302, and a synchronous comparison circuit 303.

The second frame memory circuit 301 is a DD
DD conversion Y signal S109 output from the conversion circuit 109
a, DD conversion Cr signal S109b, DD conversion Cb signal S
109c is a burst clock S10 of 14.3 MHz
After writing in 5, the signal is read out with the 13.5 MHz free-run clock S112 and output as the Y signal S301a, the Cr signal S301b, and the Cb signal S301c.

The switching circuit 302 outputs the Y signal S110a, the Cr signal S110b, and the Cb signal S110c output from the first frame memory circuit 110, and the Y signals S301a and Cr output from the second frame memory circuit 301.
The signal S301b and the Cb signal S301c are alternately switched and output to the multiplexing circuit 114 for each frame.

The synchronization comparison circuit 303 compares the phase of the synchronization signal S104a output from the synchronization separation / burst detection circuit 104 with the phase of the synchronization signal S113 output from the vertical / horizontal signal generation circuit 113, and outputs the synchronization signal. S104
When it is detected that the phase of a has passed the phase of the synchronization signal S113, the switching circuit 302 outputs a switching signal instructing to output the same frame twice in succession.

The operation of the first frame memory circuit 110, the second frame memory circuit 301, the switching circuit 302, and the sync comparison circuit 303 when the phase of the sync signal S104a exceeds the phase of the sync signal S113 will be described below. This will be described using 7.

FIG. 7A is a conceptual diagram of write / read lines for the frame memory circuit. Note that FIG.
In (a), the write line is the synchronization signal 104a.
In addition, the read line corresponds to the sync signal 113.
Writing each signal to the frame memory circuit 110 is shown in FIG.
As shown in (b), frame A, frame C, frame E. ． As described above, it is performed for each frame. Similarly, the writing of each signal to the second frame memory circuit 301 is also performed for each frame such as frame B and frame D .. Another frame is alternately written in the second frame memory circuit 301. The reading of each signal of the first frame memory circuit 110 or 5 is performed for each frame as shown in FIG. 7D, such as frame A, frame A, frame X, frame C, frame C .. Read out. The frame X is a frame read from the first frame memory circuit 110 when the write line overtakes the read line, as shown in the write / read conceptual diagram of FIG. 7A. At this time, the read frame is switched. Occurs. That is, in this case, the frame A is read first, and the frame C is read halfway. Each signal is read from the second frame memory circuit 301 for each frame as shown in FIG. 7E, and is read as frame B, frame B, frame D, frame D .. The synchronous comparison circuit 303 normally outputs a switching signal S303 that alternately selects the output of the first frame memory circuit 110 and the output of the second frame memory circuit 301, but the write line has overtaken the read line. 7f, a switching signal S303 for instructing to output the frame B twice in succession is output as shown in FIG. 7F, and the switching circuit 302 outputs the switching signal S303 based on the switching signal S303 in FIG.
Y signal 302a, Cr signal 302b, Cb as shown in
The signal 302c is output.

As described above, when the write line passes the read line, the switching circuit 302 outputs the same frame twice, so that the switching of the read frame does not occur during the reading of the frame.

On the other hand, the synchronization comparison circuit 303 outputs the synchronization signal S
When it is detected that the phase of 113 has passed the phase of the synchronization signal S104a, a switching signal instructing to delete the image for one frame is output. Hereinafter, the synchronization signal S1
The operation of the first frame memory circuit 110, the second frame memory circuit 301, the switching circuit 302, and the synchronization comparison circuit 303 when the phase of 13 exceeds the phase of the synchronization signal S104a will be described with reference to FIG. . Figure 8
(A) is a conceptual diagram of a write / read line to a frame memory circuit. In FIG. 8A, the write line corresponds to the synchronization signal 104a and the read line corresponds to the synchronization signal 113. Writing to the first frame memory circuit 110 is performed for each frame, such as frame A, frame C, frame E, as shown in FIG. 8B. Similarly, writing to the second frame memory circuit 301 is also performed for each frame such as frame B and frame D as shown in FIG. 8C, and the first frame memory circuit 110 and the second frame memory Another frame is alternately written to the circuit 301.
The reading of the first frame memory circuit 110 is performed in FIG.
As shown in (d), it is performed for each frame, and frame A,
The frame A, the frame C, the frame E .. The reading of the second frame memory circuit 301 is performed for each frame as shown in FIG. 8E, and is read as frame B, frame X, frame D .. The frame X is a frame read from the second frame memory circuit 301 when the read line overtakes the write line, as shown in the write / read conceptual diagram of FIG. 8A. At this time, the read frame is switched. Occurs. That is, the frame B is first read from the second frame memory circuit 301,
The frame D is read during the reading of the frame. The synchronous comparison circuit 303 normally outputs a switching signal for alternately selecting the output of the first frame memory circuit 110 and the output of the second frame memory circuit 301, but it is detected that the read line has overtaken the write line. When it is detected, the switching signal S303 instructing not to output the frame B is output as shown in FIG. 8 (f).
The switching circuit 302 is based on the switching signal S303 in FIG.
Y signal 302a and Cr signal 302 as shown in (g)
b, Cb signal 302c is output.

As described above, according to the video signal processing device of the third embodiment, when the synchronous comparison circuit 303 detects that the write line has overtaken the read line, the same frame is output twice. And a switching signal S303 for instructing to delete an image for one frame when it is detected that the reading line has overtaken the writing line.
Since the signal is output to the switching circuit 302, switching of the frame to be read does not occur during reading of the frame, and noise can be prevented from being generated on the screen even when a non-standard television signal is input. .

[0070]

As described above, according to the video signal processing apparatus of the present invention, the rate conversion of a digital video signal can be performed without providing an external analog PLL circuit for generating a clock synchronized with a horizontal synchronizing signal. The circuit scale is small and the LSI can be easily integrated.

Further, according to the video signal processing apparatus of the present invention, the rate of a digital video signal can be converted without providing an external analog PLL circuit for generating a clock synchronized with one frame, and the circuit scale is small. LS
I can be easily integrated.

Further, according to the video signal processing apparatus of the present invention, it is possible to prevent noise from being generated on the screen even when a non-standard television signal is input.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a video signal processing device according to a first embodiment.

FIG. 2 is a configuration diagram of a DD conversion circuit 109.

FIG. 3 is a diagram for explaining the operation of the DD conversion circuit 109.

FIG. 4 is a diagram showing the number of effective pixels in one horizontal period of a video signal and the number of effective pixels in a blanking period,
(A) is Y signal 108a, (b) is DD conversion Y signal 10
9a and (c) are Y signals 110a.

FIG. 5 is a configuration diagram of a video signal processing device according to a second embodiment.

FIG. 6 is a configuration diagram of a video signal processing device according to a third embodiment.

FIG. 7 is a diagram for explaining the operation of the video signal processing device according to the third embodiment.

FIG. 8 is a diagram for explaining the operation of the video signal processing device according to the third embodiment.

FIG. 9 is a block diagram of a conventional video signal processing device.

FIG. 10 is a waveform diagram of a video signal, where (a) is the video signal,
(B) is a synchronization signal, (c) is a burst signal.

FIG. 11 is a diagram for explaining Y / C separation, where (a) is a video signal, (b) is a luminance signal, and (c) is a chrominance signal.

[Explanation of symbols]

100, 200, 300 Video signal processing device 101 Analog television signal input terminal 102 first digital video signal output terminal 103 A / D conversion circuit 104 Synchronous separation / burst detection circuit 105 Burst lock clock generation circuit 106 Y / C separation circuit 107 color decoding circuit 108 TBC circuit 109 DD conversion circuit 110 First Frame Memory Circuit 111 Free-run clock generation circuit 112 frequency divider 113 Vertical / horizontal signal generation circuit 114 multiple circuits 115 D / A conversion circuit 116 Second A / D conversion circuit 117 Sync separation circuit 118 Horizontal sync clock generation circuit 201 Second digital video signal output terminal 202 DVC preprocessing circuit 203 Multiplier circuit 204 frequency divider 205 frame synchronization clock generation circuit 301 Second frame memory circuit 302 switching circuit 303 Synchronous comparison circuit 1000 sampling frequency conversion circuit 1091 interpolation position detection circuit 1092 coefficient selection circuit 1093 DD interpolation filter

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 2000-333127 (JP, A) JP 11-68516 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 11/00-11/22 H04N 9/00-9/78

Claims (8)

(57) [Claims] 1. A first digital video signal sampled with a first clock signal having a first frequency is input, and the first digital video signal is interpolated to obtain a length of one horizontal period and The sampling frequency remains unchanged, and the effective pixel period in one horizontal period is N times (N> 0)
A digital-to-digital conversion means for calculating a second digital video signal, converting the first digital video signal into the second digital video signal, and outputting the second digital video signal based on the first clock signal. Clock generating means for generating a second clock signal having a second frequency that is 1 / N times the first clock signal; and storing the second digital video signal, and storing the stored second signal. Storage means for reading a digital video signal with the second clock signal and outputting it as a third digital video signal. 2. An A / D conversion circuit for sampling an analog video signal with a first clock signal having a first frequency and converting the analog video signal into a first digital video signal; and a first synchronization signal from the analog video signal. A sync signal separating means for separating the first clock signal, a first clock generating means for generating the first clock signal from the first sync signal, and a second digital video signal obtained by interpolating the first digital video signal. A sampling frequency conversion device for converting the signal into a signal and outputting the second digital video signal based on a second clock signal having a second frequency, wherein the sampling frequency conversion device comprises the first digital video signal. The signal is interpolated, and the length of one horizontal period and the sampling frequency remain unchanged.
Second, in which the effective pixel period in the horizontal period is N times (N> 0)
First digital-digital converting means for calculating the first digital video signal, converting the first digital video signal into the second digital video signal, and outputting the second digital video signal based on the first clock signal; Second clock generating means for generating a second clock signal having a second frequency that is 1 / N times the first clock signal; and storing the second digital video signal, and storing the second clock signal. And a storage unit which reads out the digital video signal according to the second clock signal and outputs the digital video signal as a third digital video signal. 3. The video signal processing device according to claim 2, wherein the multiplying means is configured to multiply the second clock signal to generate a third clock signal having a third frequency, and the third clock. Frequency dividing means for dividing the signal to generate a fourth clock signal having a fourth frequency; and a fourth digital video signal based on the fourth clock signal for dividing the third digital video signal. Second to convert to
And a digital-to-digital conversion means of the above. 4. The video signal processing device according to claim 2, wherein the phase comparison of the first synchronization signal and the phase of a second synchronization signal generated from the second clock signal are performed for synchronization comparison. The storage means further comprises means for storing the second digital video signal in frame units, and reading the stored second digital video signal in frame units based on the second clock signal. No. 4 digital video signal is output as a digital video signal, the second digital video signal is stored in frame units, and the stored second digital video signal is based on the second clock signal. Second frame storage means for reading out in frame units and outputting as a fifth digital video signal; the fourth digital video signal; And a switching means for alternately switching the fourth digital video signal and the fifth digital video signal and outputting the third digital video signal as the third digital video signal. When the circuit detects that the phase of the first synchronization signal has passed the phase of the second synchronization signal, the circuit outputs the fourth digital video signal or the fifth digital video signal to the third digital video signal. A switching signal for instructing to repeatedly output twice as a digital video signal,
When it is detected that the phase of the second synchronization signal has passed the phase of the first synchronization signal, the fourth digital video signal or the fifth digital video signal is deleted by one frame. Outputting a switching signal to instruct to the switching means, and the switching means outputs the fourth digital video signal or the fifth digital video signal as the third digital video signal based on the switching signal. A video signal processing device characterized by. 5. A first digital video signal sampled with a first clock signal having a first frequency is input, the first digital video signal is interpolated, and the length of one horizontal period and The sampling frequency remains unchanged, and the effective pixel period in one horizontal period is N times (N> 0)
A digital-to-digital conversion step of calculating the second digital video signal, converting the first digital video signal into the second digital video signal, and outputting the second digital video signal based on the first clock signal. A clock generating step of generating a second clock signal having a second frequency that is 1 / N times the first clock signal; storing the second digital video signal, and storing the second digital video signal. A storage step of reading the digital video signal with the second clock signal and outputting it as a third digital video signal. 6. An A / D conversion step of sampling an analog video signal with a first clock signal having a first frequency to convert the analog video signal into a first digital video signal, and the analog video signal to a first synchronization signal. A sync signal separating step for separating the first clock signal, a first clock generating step for generating the first clock signal from the first sync signal, an interpolation process for the first digital video signal, Length and sampling frequency are unchanged, 1
Second, in which the effective pixel period in the horizontal period is N times (N> 0)
Calculating a digital video signal of, converting the first digital video signal into the second digital video signal,
A first digital-to-digital conversion step of outputting based on the first clock signal, and a second step of generating a second clock signal having a second frequency which is 1 / N times the first clock signal And a step of storing the second digital video signal and reading the stored second digital video signal with the second clock signal to output as a third digital video signal. A video signal processing method comprising: 7. The video signal processing method according to claim 6, wherein the step of multiplying the second clock signal to generate a third clock signal having a third frequency, the third clock. A frequency dividing step of dividing a signal to generate a fourth clock signal having a fourth frequency; and a fourth digital video signal based on the fourth clock signal, the third digital video signal Second to convert to
And a digital-to-digital conversion step of. 8. The video signal processing method according to claim 6, wherein the phase of the first synchronization signal is compared with the phase of a second synchronization signal generated from the second clock signal. The method further comprises a step of storing the second digital video signal in frame units, and reading the stored second digital video signal in frame units based on the second clock signal. A first frame storing step of outputting as a digital video signal of No. 4, storing the second digital video signal in frame units, and storing the stored second digital video signal in a frame based on the second clock signal. A second frame storing step of reading out in units and outputting as a fifth digital video signal; A switching step of inputting an image signal and the fifth digital video signal and alternately switching between the fourth digital video signal and the fifth digital video signal and outputting the third digital video signal. Including the fourth digital video signal or the fifth digital video signal when the synchronization comparison step detects that the phase of the first synchronization signal has passed the phase of the second synchronization signal. When it is detected that the phase of the second synchronization signal has passed the phase of the first synchronization signal, the switching signal for instructing to output twice as the third digital video signal is detected. Fourth
A switching signal instructing to delete one frame of the digital video signal or the fifth digital video signal, and the switching step is based on the switching signal, and the fourth digital video signal or the fifth digital video signal. And outputting the digital video signal as the third digital video signal.