JPS60180290A - Television receiver - Google Patents

Abstract

PURPOSE:To eliminate the generation of jitters in a video signal by controlling the reading from a memory circuit by means of a read clock signal, which synchronizes with a synchronizing signal through a frequency selecting circuit for removing jitter components. CONSTITUTION:A signal of a frequency 2fH, synchronizing with a synchronizing signal SSYNC of a horizontal frequency fH can be obtained from a voltage control oscillator 17 and supplied to a phase comparator 19. Although jitters always occurs in the signal SSYNC, jitters will not occur in the signal supplied to the comparator 19 by means of the oscillator 17 owing to a function of a PLL circuit 15 constituting a frequency selecting circuit for removing jitters. Thus a read clock signal CLKR obtained by a voltage control oscillator 13 synchronizes with the signal SSYNC and never has jitters. As a result jitters never occur in a luminance signal Y', color difference signals (R-Y)' and (B-Y)' obtained from a memory circuit 8, and an excellent video signal can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention converts, for example, an interlaced input video signal through a memory circuit into a signal with twice the horizontal frequency, which is supplied to a picture tube to increase the horizontal frequency. The present invention relates to a television receiver suitable for application to a television receiver that performs non-interlaced display in which the number of pixels is doubled.

BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, in order to eliminate the roughness of scanning lines, the horizontal frequency is
Television receivers have been proposed that display multiplied non-interlaced images. This television receiver is configured such that, for example, an interlaced input video signal is converted into a signal with twice the horizontal frequency via a memory circuit, and this signal is supplied to a picture tube. Here, the control of writing to the memory circuit and directing is as follows:
Conventionally, writing and reading clock signals are generated in synchronization with a color burst signal extracted from an input video signal. In this case, if there is no jitter in the input video signal, there is no problem, but if the input video signal is, for example, a playback signal from a VTR (video tape recorder) with jitter, the memory circuit There is also the disadvantage that similar jitter occurs in the converted signal from the converter.

OBJECTS OF THE INVENTION In view of the above, the present invention is designed to prevent jitter from occurring in a video signal passed through a memory circuit even if the input video signal is accompanied by jitter.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention performs readout from a memory circuit using a readout clock that is separated from an input video signal and formed in synchronization with a synchronization signal that is passed through a frequency selection circuit for removing jitter components. It is controlled by signals.

Therefore, even if the input video signal is accompanied by jitter, the synchronization signal passed through the frequency selection circuit no longer has jitter, and therefore the readout clock signal formed in synchronization with this signal also has no jitter. , the video signal passed through the memory circuit has no jitter and is of good quality.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG. In this example, as shown in FIGS. 2A and 2B, the present invention is applied to a television receiver that displays a non-interlaced display in which the horizontal frequency is doubled. Figure 2 A, B
For the sake of simplicity, the case where there are five scanning lines is shown, where A is an odd field and B is an even field. in this case,
Two scanning lines with the same signal are successively formed.

In addition, in FIGS. 2A and 2B, the broken lines indicate the case of interlaced display.

In FIG. 1, (1) is an antenna terminal, and an RF modulation signal SRF is supplied to this terminal (1) from, for example, a VTR. This RF modulation signal SRF is then supplied to the tuner (2), and the intermediate frequency signal obtained from this is supplied to the video detection circuit (4) via the intermediate frequency amplifier (3), from which the color video signal Sv is supplied. can get.

This video signal Sv is converted into a digital signal by an A/D converter (5) and supplied to a subsequent V color separation circuit (6), where it is separated into a luminance signal Y and a color signal C. The color signal C is supplied to a color signal processing circuit (7) and processed, for example, a red difference signal R-Y and a blue difference signal B-Y are obtained and sent to a memory circuit (8) K.
Supplied. On the other hand, the luminance signal Y is supplied to the memory circuit (8)K via a delay circuit (9) for time adjustment.

In the memory circuit (8), reading speed is controlled to be twice as fast as writing speed. Then, from this memory circuit (8), for example, the same scanning line signal is transmitted twice in one horizontal period, that is, a luminance signal Y whose horizontal frequency is doubled, a red difference signal (R-Y), and a blue difference signal. A signal (B-Y) is obtained.

That is, the color burst signal (frequency fsc) extracted from the video signal Sv from the separation circuit (6) is supplied to the APC circuit (II), from which a continuous wave signal of frequency fsc synchronized with the color burst signal is obtained. This is supplied to the multiplier (IIIK). Then, a signal with a frequency of 4 fsc, for example, is obtained from the multiplier (III), which causes ~
Φ converter (51), separation circuit (61) are controlled,
This signal with a frequency of 4fsc is the omitted clock signal CL.
It is supplied to the addressing circuit (121) as Kw.

Then, the omitted addresses of the memory circuit (8) are sequentially designated by this address designation circuit (121) at the timing of the clock signal CLKw, and the luminance signal Y and the color difference signal rTl are sequentially designated.
l-Y)' and (RY) are respectively omitted.

On the other hand, a signal with a frequency of 8fsc is supplied from the voltage controlled oscillator (131) to the addressing circuit (121) as a read clock signal CLKR. The read addresses are sequentially specified so that, for example, the same scanning line signal is read out twice in a row in two horizontal periods.

In this case, a signal with a frequency of 8fac obtained from the oscillator a3 is synchronized with a synchronization signal separated from the video signal Sv. That is, the video signal Sv obtained from the video detection circuit (4) is supplied to the synchronization separation circuit 04), where a synchronization signal 8sync of horizontal frequency (fu) is separated, and this synchronization signal 5sync is used to select the frequency for jitter'-removal. The signal is supplied to the phase comparator of the PLL circuit 05) which constitutes the circuit. In addition, (171 is a voltage controlled oscillator, whose output is upper divided by the 1 frequency divider a& and then supplied to the 2nd phase comparator (6) for phase comparison, and the comparison error signal is output from the oscillator output. η as a control signal.

Therefore, a signal with a frequency of 2fH synchronized with the synchronization signal 5sync is obtained from the oscillator a9, and this is transmitted to the phase comparator al.
supplied to In this case, even if the video signal Sv is accompanied by jitter and therefore the synchronization signal 5sync is accompanied by jitter, the jitter is removed from the signal of frequency 2jH from the oscillator un by the action of the PLL circuit a51. Become something. The phase comparator a9 also receives a synchronization signal 5s with a frequency of 2fH separated by a synchronization separation circuit (2i) from the luminance signal Y obtained at the output side of the memory circuit (8).
ync is supplied, the phase is compared, and the comparison error signal is supplied as a control signal to the oscillator Q31 via the low-pass filter (211). Therefore, the oscillator (I3)→addressing circuit (121→memory circuit (8)→ Synchronous pre-circuit (20) → Phase comparator [9 → Low-pass filter c!
A loop of 11 → oscillator + 1.31 is formed, and a signal with a frequency of 2fH supplied from the oscillator (171 that constitutes the PI and L circuits) to the phase comparator a!J is a synchronized signal separated from the video signal Sv. Since it is synchronized with the signal 5sync, the frequency 8 obtained from the oscillator (13)
The fsc signal is synchronized with the synchronization signal 5sync. Furthermore, even if the synchronization signal 5sync is accompanied by jitter, the signal with a frequency of 2fH from the oscillator 131 has the jitter removed, so there is no jitter in the signal with a frequency of 8fsc obtained from the oscillator (131). .

As mentioned above, the luminance D/ obtained from the memory circuit (8)
After being converted into an analog signal via the A converters (22+, (23i) and CJ41), it is supplied to the matrix circuit (c).

Horizontal frequency waves B' are obtained from the matrix circuit (25) and supplied to the corresponding cathodes KR, KG and KB of the picture tube (two forces) via the respective drive circuits (c).

Further, in FIG. 1, a synchronization signal 5sync with a frequency of 2fH separated from the luminance signal Y by the synchronization separation circuit is supplied to a phase comparator (c). Further, (c) is a horizontal oscillator, from which a signal with a frequency of 2fH is supplied to a horizontal deflection scanning group, and a deflection signal from this is supplied to a deflection coil Gυ and also to a phase comparator. The comparison error signal is then supplied to the oscillator (21) as a control signal. Therefore, the picture tube (27) uses the synchronizing signal 5sync.
In synchronization with ', horizontal deflection scanning is performed at twice the normal speed.

Incidentally, although not shown, vertical deflection scanning is performed as usual.

This example is constructed as described above, and the picture tube screen η receives red, green, and blue signals R1G' and B' whose horizontal frequencies are doubled.
is supplied and horizontal deflection scanning is performed at twice the normal speed, so that a non-interlaced display with twice the horizontal frequency is displayed on the picture tube (27) as shown by the solid lines in Figure 2 A and B. Ru.

According to this example, even if the video signal Sv is accompanied by jitter and therefore the synchronization signal 8sync is accompanied by jitter, the phase comparator (11 Therefore, the read clock signal CLKR obtained from the oscillator u3 is synchronized with the synchronization signal 5sync and has no jitter.

Therefore, even if the video signal Sv is accompanied by jitter,
The luminance signal Y', color difference signals (RY), and (B-Y) obtained from the memory circuit (8) have no jitter and are good.

In the above embodiment, a PLL circuit (151) is used as a frequency selection circuit for removing jitter, but the circuit is not limited to this. In short, any circuit that can remove jitter components may be used. In the embodiment, the invention is applied to a television receiver that displays non-interlaced display with twice the horizontal frequency, but the present invention is applicable to a television receiver in which an input video signal is supplied to a picture tube via a memory circuit. It can be similarly applied to television receivers.

Effects of the Invention As is clear from the embodiments described above, according to the present invention, even if the input video signal is accompanied by jitter, there is no jitter in the read clock signal, and therefore the video transmitted through the memory circuit is The signal will be good with no jitter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram for explaining the same. (4) is a video detection circuit, (6) is a bright V color separation circuit, (8
) is a memory circuit, 001 is an APC circuit, (Ill is a multiplier, (121 is an addressing circuit, α3 is a voltage controlled oscillator, Q41 and (201 are respectively synchronous separation circuits, (15
1 is a PLL circuit, a9 is a phase comparator, and (27) is a picture tube.

Claims (1)

[Claims] In a television receiver in which an input video signal is supplied to a picture tube via a memory circuit, writing to the memory circuit is formed in synchronization with a color burst signal extracted from the video signal. In addition to being controlled by a write clock signal, reading from the memory circuit is controlled by a read clock signal that is separated from the video signal and is formed in synchronization with a synchronization signal that is passed through a frequency selection circuit for removing jitter components. A television receiver characterized by: