JPS62254590A - Signal processing circuit for television receiver - Google Patents

Abstract

PURPOSE:To obtain a stable sampling clock by performing a PLL operation by an A/D converted burst signal during the burst signal period of a receiving signal. CONSTITUTION:During the burst signal period, a switch circuit 6 selects the output of an A/D converter 2 by a control signal from a burst extracting pulse generating circuit 13, gives this output to B.P.F 7 to remove a direct current component and limit a band. The sampled value of the obtained burst signal is extracted in a burst extracting circuit 8 based on the control signal of the burst extracting pulse generating circuit 13 and the phase difference between the burst signal of the receiving signal and the sampling clock is obtained in a PLL circuit 9. Thereby, when the phase synchronization of the sampling clock such as at the time of energizing the power source of the device or at the time of the fluctuation in a source voltage, the sampling clock phase rapidly synchronizes with a burst signal phase to attain the high quality of the picture of a video signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal processing circuit for a television receiver, and is particularly suitable for receiving high-definition television signals that are compatible with current broadcasting systems. The present invention relates to a signal processing circuit for a suitable television receiver.

[Conventional technology]

A high-definition television signal system that is fully compatible with the current broadcasting system, NTSC, has been proposed and is attracting attention. (
"Proposal of a high-definition TV system with complete communication capability" IEICE Technical Report C5&l-61 (1983), pp. 47 to 54 (8) This is to achieve high definition by converting the frequency within the transmission band and multiplexing it with the luminance signal within the transmission band.

FIG. 3 is a diagram showing the phase of a modulating carrier wave for a high frequency component of a multiplexed luminance signal.

In the prior art described in the above-mentioned document, the phase of the carrier wave for performing the frequency conversion is inverted between frames, as shown in FIG. It is assigned so that it is the same as the phase of the scan line located immediately above the previous field, that is, the phase of the carrier wave ψ, ψ+π falls from field to field.

As is well known, the phase of the color subcarrier in the NTSC system is inverted between frames, and the phase of the carrier wave increases from field to field.

Therefore, in order to separate the three signals of the luminance signal, one color signal, and the high frequency component of the luminance signal, the inter-frame calculation and inter-field calculation shown in FIG. 3 are used.

FIG. 4 is a block diagram for explaining an example of a conventional circuit for separating luminance and color signals, in which 1 is a received signal input terminal;
2 is an A/D converter, 3 is 525 H (H is 1 horizontal scanning period), 4 is an adder, 5 is a subtracter, 7 is a band pass filter (E, P, F,), 10 is a luminance signal output 31 is a 262H delay circuit, 32 is a subtracter, 0 is an adder, 3 is a luminance signal high frequency component output terminal, and 35 is a chrominance signal output terminal.

In the figure, first, a luminance signal is extracted from the output of the adder 4 by interframe addition, and a high frequency component of the luminance signal and a color signal are extracted from the output of the subtracter 5 by interframe subtraction. 262 more
The high frequency component YE of the luminance signal and the color signal C are separately extracted by addition and subtraction with the signal delayed by 2621 in the H delay circuit 31.

In order to achieve high image quality, scanning line interpolation is performed and non-interlace display is performed to improve image quality.

Such conventional devices include ``completely compatible E
There is a device described in the Journal of Television Engineers, Vol. 39, No. 10, pp. 891-897 entitled "DTV Signal System - Part 2 Prototype of Principle Model Having Motion Adaptive Characteristics." The above document does not specifically disclose the method of generating the sampling clock of the A/D converter 2, which affects the luminance/chrominance signal separation performance and the color demodulation performance, but it is usually disclosed in TV Technical Magazine Vol. A, November As described on pages 119 and 120 of the issue, in order to synchronize the sampling clock with the burst signal phase in the received signal after the luminance/chrominance signal separation circuit, PLL (Phase Locked Loop) is used.
) operation to obtain a predetermined sampling clock. Therefore, when applied to a device using the EDTV signal system, the PLL operation will be performed using the burst signal superimposed on the color signal after inter-frame arithmetic processing.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not give particular consideration to the method of generating a sampling clock, which influences the luminance/chrominance signal separation performance and color demodulation performance of the device.

This point will be explained in detail below with reference to the burst waveform diagram in FIG.

FIG. 5 is a waveform diagram showing burst signal sampling in the prior art.

In the figure, consider an arbitrary time T immediately after the conventional device is powered on. The burst signal waveform in the received signal at this time corresponds to the waveform shown in FIG. 5 (α), and the burst signal is converted into A,
Assume that sampling is performed at points B, C, and D. Next, exactly one frame after time 1, the burst signal waveform (b)
A', B' shown in .

If each point CI, D' is sampled, the burst signal obtained from the subtracter 5 in FIG. 4 by the interframe arithmetic processing of the conventional device will be A', B'', The device composed of points C" and D" differs from the original burst signal waveform.

Here, the sampling point A is a point corresponding to A' and A'' on the address of the frame memory 3, and the same applies to B, C, and D below.The waveform processed in this way between frames If (1) is extracted with a burst extraction pulse and applied to a PLL, the PLL may become out of synchronization because it is different from the original burst signal.Therefore, after the power is turned on, the sampling clock phase will match the burst signal phase. Not only will synchronization be lost and luminance/chrominance signal separation performance will not be obtained, but in some cases, the device may oscillate.Also, the above is about when the power is turned on, but if PLL synchronization is applied, the power supply voltage Even if the circuit changes or the element constants of the circuit undergo temperature changes,
PLL synchronization is lost, and the same problem as when the power is turned on occurs in that a stable sampling clock cannot be obtained.

As described above, the conventional example has a problem in that a stable sampling clock cannot be obtained.

An object of the present invention is to provide a signal processing circuit for a television receiver that includes a clock generation circuit that stably generates the sampling clock.

[Means for solving problems]

The above problem is that after the received signal is A/R) converted, the A/D conversion output is converted into the A/D conversion output during the burst signal period of the received signal, and the A/D conversion output is further converted into the luminance/chrominance signal during the other periods. The color signal output obtained through the separation circuit is applied to a selection circuit that selects the output, and the output of the selection circuit is passed through a band-limiting filter and added to the burst extraction circuit.
This problem is solved by extracting the digitized burst signal obtained from the selection circuit and operating a PLL circuit that generates a sampling clock for the A/D converter using the extracted burst signal.

[Effect]

The selection circuit selects an A/D signal during a burst signal period of the received signal.
The burst signal thus obtained passes through a band-limiting filter and is extracted by a burst extraction circuit, and the PLL circuit is operated so that the phase is synchronized with the extracted burst signal. As a result, the PLL operation is quickly performed immediately after the power is turned on, and a stable sampling clock can be obtained from the PLL circuit. This allows the PL to change when the power is turned on or due to temperature changes, etc.
Even if the L circuit deviates from the locked state, it is quickly followed up and the PLL operation is stabilized, so that the luminance-chrominance signal separation and color demodulation performance of the device can be fully utilized.

〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal processing circuit of a television receiver according to the present invention, in which 1 is an input terminal for inputting a received signal, and 2 is an A/D conversion circuit for digitizing the received signal. 3 receives the VD converted received signal at 525
Frame memory delayed by H (H is one horizontal survey period), 4
is an adder for obtaining the inter-frame sum, 5 is a subtracter for obtaining the inter-frame difference, 6 is a switch that is switched every burst signal period of the received signal, and 7 is a band passph for band limitation. DDu
L Joko Town 1 6 Iko: Ko
, ・Burst extraction circuit for extracting the digitized burst signal from the color signal 9 is an A/D converter that calculates the phase error from the digitized burst signal and synchronizes with the burst signal phase in the received signal. is a PLL circuit that generates a sampling clock of
．． 7 is an output terminal for the high-frequency components of the color signal and luminance signal, 12 is a horizontal sync separation circuit that separates a horizontal sync signal, and 13 is a horizontal sync signal output terminal for a burst signal period from the horizontal sync signal obtained by the horizontal sync separation circuit 12. This is a burst extraction pulse generation circuit that generates a burst extraction pulse for extracting a signal.

In the figure, an input signal from an input terminal 1 is digitized by an A/D converter 2. When this output is input to the adder 4, the frame memory 3 adds seven signals of the previous l frame delayed by 525H to obtain a luminance signal. Does this mean that the phase of the color subcarrier and the modulation carrier for the local components of the luminance signal vary between frames? roν18o0zuhτ
Therefore, when the inter-frame sum is calculated for a still image, the high-frequency components of the color signal and luminance are canceled, and only the luminance signal is obtained. On the other hand, if the difference between frames is taken by the subtracter 5, the luminance signal is canceled and a signal containing a color signal and a high-frequency component of luminance is obtained.

These signals are extracted at B, P, F, and 7, and are separated into color signals and high-frequency components of luminance in the next stage, although not shown in FIG.

The above explanation refers to the video signal period of 13M, and at this time the switch circuit 6 selects the frame difference output of the subtracter 5. During the burst signal period, the switching circuit 6 is switched to A by the open signal from the burst extraction pulse generation circuit 13.
Select the output of ρ converter 2 and convert this output into B, P, F, 7
DC component is removed and the band is limited. The sample value of the burst signal obtained in this way is extracted by the burst extraction circuit 8 based on the control signal of the burst extraction pulse generation circuit 13, and the phase difference between the burst signal of the received signal and the sampling clock is calculated by the PLL circuit 9. By determining this, the excavation frequency and phase of the sampler clock can be stably controlled.

Therefore, according to the embodiment of FIG. 1, the burst period is not the frame difference signal from the luminance/chrominance signal separation circuit;
By selecting the output from the A/D converter 2, the sampling clock phase can be quickly synchronized with the burst signal phase when the sampling clock phase cannot be synchronized, such as when the device is powered on or when the power supply voltage fluctuates. It is possible to improve the image quality of the signal.

In the embodiment shown in Fig. 1, a so-called frame comb circuit using a frame memory is used as the luminance/chrominance signal separation circuit, but the same effect can be obtained by using a line comb circuit using a line memory. Of course, it can be done.

In addition, in the embodiment shown in FIG. 1, the received signal is a high-definition signal that is compatible with the conventional method, but the conventional method uses the conventional NTSC method as the received signal and uses a comb circuit as the luminance/chrominance signal separation circuit. Even if the present invention is applied to a television receiver, exactly the same effect can be obtained.

FIG. 2 is a block diagram showing another embodiment of the signal processing circuit for a television receiver according to the present invention, in which 41 is a switch circuit that switches every burst signal period, and is similar to the switch circuit 6 shown in FIG. Perform the same action. Also, 42 is a multiplier, C is a burst width detection circuit that detects the amplitude of the burst signal, and according to the output of the burst width detection circuit,
A gain control circuit 45 changes the multiplier given to the multiplier 42, and 45 is an output terminal that outputs a color signal whose amplitude is controlled by the multiplier 42.
The same reference numerals as in the figure indicate the same functions.

Portions in FIG. 2 having the same reference numerals as those in FIGS. 1 and 4 perform exactly the same operations. That is, during the burst signal period of the received signal, the switch circuit 6 selects the output of the A/D converter 2, and outside of the above period, selects the color signal and high-frequency component output of luminance obtained by frame comb filter processing. do. The output of the switch circuit 6 obtained in this way passes through B, P, F, 7, and then passes through field memo 1J31. A spatio-temporal filter circuit comprising a subtracter 32 and an adder 32 separates the signal into a color signal and a high frequency component of luminance. Next, the output of the adder and the outputs of B, P, F, and 7 are input to the switch circuit 41. This switch circuit 41 operates to select the outputs of B, P, and 1.7 during the burst signal period of the received signal, and select the output of the adder section during other periods. In other words, during the burst signal period, the switch circuit 41 has B,
A burst signal with P, F, and P is output, and at other times, a color signal separated from two luminance color signals is output. The burst signal thus obtained is sent to the multiplier 42, the burst extraction circuit w58, the burst amplitude product circuit 1!2143. A consisting of a weak gain control circuit
CC (Automatic Co1or Con-t)
rol ) is input to the circuit. 'Here, to briefly explain the ACC circuit, the input burst signal is extracted by the burst extraction circuit 8, and the burst signal is extracted by the burst width detection circuit 43.
It is detected whether or not the amplitude is at a predetermined level. If the amplitude is not at a predetermined level, the coefficient of the multiplier 42 outputted from the gain control circuit 44 is operated to reach a predetermined level. In this way, the amplitude of the color signal is kept constant.

Here, if the burst extraction circuit 8 of the ACC circuit is also used as the PLL circuit 9 for clock generation, it is possible to generate a stable sampling clock in exactly the same way as in the embodiment shown in FIG.

With this configuration, the same effects as in FIG. 1 can be obtained.

As explained above, according to the present invention, conventional digital TV aiming at high image quality, so-called IDTV (Impr
. vtdTV) and EDTV (E
tion T V ) to obtain a stable sampling clock.

〔effect〕

According to the present invention, the burst signal period of the received signal is
PLL operation is performed directly using A/D converted burst signals without using a color signal separation circuit, so even when the device is turned on, the power supply voltage fluctuates, or the circuit element constants change due to temperature changes. , since the sampling clock phase follows the burst signal phase, good brightness and
Color signal separation performance and color demodulation performance are obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional circuit for separating power and color signals, and FIG. The figure is a waveform diagram showing the state of burst signal sampling in the prior art. [Explanation of symbols] 2... Aμ converter 3... Frame memory 4
．． 33...Adder 5, 32...Subtractor 3
1...Field memory 6.41...Switch circuit 7...B, P, F, 8...Burst extraction circuit 9...
・PLL circuit 13...burst extraction pulse generation circuit') ・Patent attorney Masao Ogawa -/Representative patent attorney Nod Monthly 1 n, 3rd figure scanning line for men 1 piece of porridge

Claims (1)

[Claims] 1. In a signal processing circuit of a television receiver that separates a luminance signal and a chrominance signal from a received signal, an A/D conversion circuit that converts the received signal from analog to digital, and the luminance signal and chrominance signal. of the A/D conversion circuit output and the separation circuit output, the burst signal period included in each horizontal period is connected to the output side of the A/D conversion circuit, and the output side of the A/D conversion circuit is a selection circuit for selecting the output side of the separation circuit; a band-limiting filter circuit for band-limiting the output of the selection circuit; a burst extraction circuit for extracting only the burst signal obtained from the filter circuit; A signal processing circuit for a television receiver, comprising a PLL circuit that controls the oscillation frequency and phase of a sampling clock of an A/D converter and oscillates the clock in synchronization with a burst signal in the received signal. . 2. A signal processing circuit for a television receiver according to claim 1, characterized in that an NTSC signal, which is a current system, is used as a reception signal of the television receiver. 3. In the signal processing circuit for a television receiver according to claim 1, as a received signal of the television receiver,
It is characterized by using a television signal that is transmitted by selecting a carrier signal for frequency converting the high frequency component of the luminance signal such that the phase thereof is inverted every frame, and multiplexing the high frequency component of the luminance signal within the transmission band. signal processing circuit for a television receiver.