JPH0832075B2 - Signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing of television signals, and more particularly to a signal processing circuit suitable for creating a signal for controlling a motion adaptive circuit.

[Conventional technology]

When signal processing is performed on a television signal to improve the image quality, for example, for an interlaced signal, a method is adopted in which the interlaced signal is sequentially converted into a scanning signal and displayed to prevent screen flicker. There is. The above method, that is, the method of converting an interlaced signal into a progressive scanning signal requires a scanning line interpolation circuit.

The scanning line interpolation circuit performs inter-field interpolation when the image is a still image, a method of obtaining an image with good resolution without flicker, and an intra-field interpolation when the image is a moving image. There is a method of obtaining an image without interference such as a double image.

That is, the inter-field interpolation circuit is suitable for still images, and the intra-field interpolation circuit is suitable for moving images. If the intra-field interpolation circuit is mistakenly used for a still image, flicker may occur or the resolution may be deteriorated. On the other hand, if the inter-field interpolation circuit is used for a moving image, a double image may occur. Cause deterioration.

So, if the image is moving from the inter-frame difference signal,
Alternatively, a motion adaptive process using an intra-field interpolating circuit for moving images and an inter-field interpolating circuit for still images has been considered.

For example, in Japanese Patent Laid-Open No. 58-205377, the movement of an image is detected based on the inter-frame difference signal, and the characteristic of an interpolation filter as an interpolation circuit is changed according to the amount of movement. However, since the motion of the image is obtained based on the inter-frame difference signal, accurate motion detection cannot be performed for fast motion. Therefore, the amount of motion detected
LPF (low-pass filter) processing is applied to prevent motion detection errors. For example, FIG. 2 (a)
When the object moves as shown in FIG. 2, the amount of movement between A and A ′ detected by the inter-frame difference signal is calculated in the (M + 1) th field and the (M−1) th field,
As shown in FIG. 4B, in this case, since there is a range in which the amount of motion is zero, erroneous detection is performed. Therefore, correction processing is performed and the amount of motion shown in FIG. As a result, erroneous interpolation is prevented.

[Problems to be solved by the invention]

In the motion amount correction method as in the above example, a motion amount of a similar pattern is generated depending on the design, and since moving image processing is performed on a still image, there is a possibility that reflicker with reduced resolution may occur. was there.

For example, when the two frames W ₁ and W ₂ as shown in FIG. 3 (a) move slowly, the detected motion amount is the same as that in FIG. 2 (b), and therefore the corrected motion amount is also the first. Since it is the same as in FIG. 2 (c), the signal S between the frames is processed as a moving image even though it is a still image.

In addition, how fast the movement can be prevented from being detected incorrectly is preset by the constant of the circuit. Therefore, it has no effect on motions exceeding this speed.

Therefore, by delaying the currently obtained motion amount using the field memory, the motion amount and the still image process are controlled by using the current motion amount and the motion amount of one field before to prevent a motion detection error. Therefore, it is possible that
Already filed as 2. An example of this is shown in FIG. “In FIG. 4 (a), 1 is an input terminal of a digitized video signal, 2 is an output terminal of a control signal for controlling a motion adaptive circuit, and 3 is an output terminal of a signal from the motion adaptive circuit. Reference numeral 4 is a frame memory for delaying the digitized video signal by one frame. Reference numeral 5 is a motion detection circuit for detecting the motion of an image from the input signal and the output signal of the frame memory 4. Reference numeral 6 is a motion for correcting the motion amount. Quantity processing circuit, 7
And 8 are a field memory of about 1 field capacity and a line memory of about 1 line capacity used in the motion amount processing circuit 6, 9
Is a system clock generator, 10 is a signal processing circuit for processing a still image of a video signal, 11 is a signal processing circuit for processing a moving image, 12 is a motion amount processing of an output signal from the still image processing circuit 10 and the moving image processing circuit 11. It is a mixer for mixing in accordance with a control signal from the circuit 6.

An example of the motion detection circuit 5 is shown in FIG. In FIG. 4 (b), 20 is an output terminal of the motion amount obtained by the motion detection circuit 5, 21 is a subtractor for obtaining the difference between the input signal and the output signal of the frame memory 3, 22 is a low-pass filter, and 23 is absolute. The value circuit and others are the same as in FIG. 4 (a). The above-mentioned motion detection circuit, that is, the circuit shown in FIG. 4 (b) is a system for detecting motion based on the frame difference. The motion detection circuit is not limited to the above example, and as shown in FIG. 4C, for example, there is a method of using another frame memory 24 and based on the difference between two frames.

From the motion amount obtained by the above method and the motion amount delayed by the field memory 7 and the line memory 8, the motion amount processing circuit 6 creates a signal for controlling the motion adaptive circuit. An example of a specific circuit of the motion amount processing circuit 6 is shown in FIGS. 5 (a) and (b)
In the figure, 25 is an input terminal for the motion amount from the motion detection circuit 5, 26 is an attenuator for doubling the input signal, 27 is a maximum value circuit, and the others are the same as in FIG. By using the motion amount processing circuit 6 having the above-described structure, the motion amount of the scanning line about one field before and the motion amount of the current scanning line can be referred to at the same time as the motion amount, so that the motion adaptive circuit can be correctly controlled. Become.
However, since a memory having a capacity of about 1 field is required, the circuit scale has increased.

An object of the present invention is to provide a signal processing circuit which correctly controls a motion adaptive circuit and has a small memory capacity.

[Means for solving problems]

The above-mentioned object is provided with a representative value calculation circuit for inputting the motion amount of a plurality of picture elements detected by the motion detection circuit and calculating a representative value of the motion amount, and using this representative value as a new motion amount, the motion amount processing circuit. This is achieved by storing the representative value for one field in the motion amount processing circuit.

[Action]

The motion amount obtained by inputting the inter-frame difference signal to the motion detection circuit 5 becomes a signal having a 1/4 fsc cycle if the system operates at a frequency four times as high as the color subcarrier fsc. However, the motion of the image does not occur that only one certain point is the motion part except the contour part of the image.
Therefore, the representative value calculation circuit calculates the representative value of the motion amount in the signal period such as 1/2 fsc cycle or 1 / fsc cycle,
There is no problem even if the motion adaptive circuit operating at a frequency such as 4fsc is controlled using the representative value of this motion amount. However, if the sample points of the motion amount are simply reduced, an erroneous motion amount may occur due to the influence of noise or the like.

Therefore, it is possible to prevent the generation of an incorrect motion amount by reducing the sampling points of the motion amount after filtering the motion amount by the representative value calculation circuit. Also,
By changing the sampling points of the motion amount for each line, it is possible to eliminate the bias of the sampling points of the motion amount and reduce the influence of reducing the sampling points.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1 (a), 14 is a representative value calculation circuit, 15 is a previous value hold circuit for holding the value of a certain sampling point for m clocks, and the others are the same as in FIG.

A video signal digitized at a clock frequency of f ₀ (normally sampled at a clock frequency of 4fsc or 3fsc, where fsc is a color subcarrier frequency) is input from the input terminal 1 and guided to the frame memory 4. The input signal and the output signal of the frame memory 4 are the motion detection circuit 5
Is input to and converted into a motion amount. Everything up to this point
Based on the clock frequency of f ₀ , the obtained motion amount becomes a signal of 1 / f ₀ cycle as shown in FIG. 1 (b).

Here, the previous value hold circuit 15 divides the motion amount into signals for every m clocks, and the motion amount of the section is represented by the first motion amount of the section, so that the frequency of the motion amount is f.
The capacity of the field memory 7 and the line memory 8 for correcting the amount of movement can be reduced to ₀ / m. Fig. 1 (c)
Shows the control signal when m = 2.

FIG. 6 shows another embodiment of the present invention. In FIG. 6, 16 is a circuit for obtaining the maximum value of n consecutive sample points of the motion amount of 1 / f ₀ cycle obtained from the motion detection circuit 5,
Others are the same as FIG. According to the present embodiment, the capacities of the field memory 7 and the line memory 8 can be reduced because the signals are thinned out to 1 / m by the hold circuit 15, and the thinned-out data can be stored in the surrounding area n. Since it is the maximum value of the points, it is possible to prevent the value from becoming an incorrect value due to the influence of noise or the like. A specific description of this embodiment will be given with reference to FIG.

FIG. 7 shows an example when n = 3 and m = 2. FIG. 7A shows the output of the motion detection circuit 5, which is a signal of 1 / f ₀ cycle. Since the maximum value circuit 16 sets n = 3, the maximum value of a certain sample point and the three pixels on the left and right of the sample point is output. Therefore, the value shown in FIG. 7B is obtained in the 1 / f ₀ cycle. In the hold circuit 15, since m = 2, the maximum value circuit
The 16 outputs are held for 2 clocks and become a signal of 2 / f ₀ cycle.

Therefore, as shown in FIG. 7 (c), a signal of 2 / f ₀ cycle is obtained, and the signal is a representative value of three surrounding points, and the capacity of the field memory 7 and the line memory 8 is reduced, In addition, an error-free control signal of the motion adaptive circuit can be obtained.

FIG. 8 shows still another embodiment of the present invention. In FIG. 8, reference numeral 17 designates a filter circuit for calculating n consecutive samples of the output of the motion detection circuit 5, and the other parts are the same as those in the embodiment of FIG. In this embodiment, the maximum value circuit 15 of the embodiment of FIG. 6 is replaced with a filter circuit 17.

The filter circuit 17 may be, for example, an average value circuit or the like, and has a motion amount representative of n consecutive sample points. The capacity of the field memory 7 and the line memory 8 is 1 / m when this is sampled by the hold circuit 15 every m.
Further, there is an effect that what is suitable as the control signal of the motion adaptive circuit is stored as the representative value.

FIG. 9 shows still another embodiment of the present invention. Ninth
In the figure, 18 is an input terminal for the horizontal synchronizing signal, 19 is a switch circuit for switching the phase of the clock frequency for controlling the hold circuit 15 and the like for each line, and others are the same as those in the embodiment of FIG. In the present embodiment, the hold circuit 15 (the ninth circuit) for thinning out the output from the filter circuit 17 every m
In the figure, the phase of the signal for controlling m = 2) is inverted for each line. For example, considering the case of m = 2, two types of clocks having 180 ° different phases are prepared as shown in FIG. 10 (a), and the output signal of the filter circuit 17 shown in FIG. By holding at the rising portion of the clock that is different for each line, the amount of movement at the position offset for each line can be stored in the memory as shown in FIG. 10 (c). According to this method, the position of the thinned motion amount (FIG. 10 (c)) does not align with the vertical direction of the screen, and therefore the effect of thinning the motion amount can be reduced.

〔The invention's effect〕

According to the present invention, the motion adaptive circuit can be controlled without error, and the capacity of the memory used for the motion amount processing circuit can be reduced, which is economical.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention and its operation, FIGS. 2 and 3 are explanatory diagrams showing a motion amount detected by an inter-frame difference signal, and FIG. 4 is a motion detection circuit, a motion amount. 5 is an explanatory diagram of the processing circuit, FIG. 5 is an explanatory diagram of the motion amount processing circuit, and FIG.
FIG. 7 is a block diagram showing another embodiment of the present invention, FIG. 7 is an operation explanatory diagram thereof, FIG. 8 is a block diagram showing another embodiment of the present invention, and FIG. 9 is still another embodiment of the present invention. FIG. 10 is a block diagram showing an example, and FIG. 10 is an explanatory diagram of its operation. 1 ... Video signal input terminal, 4 ... Frame memory, 5 ...
… Motion detection circuit, 6 …… Motion amount processing circuit, 7 …… Field memory, 8 …… Line memory, 9 …… Clock generation circuit, 10
...... Still image processing circuit, 11 …… Video processing circuit, 12 …… Mixer, 14 …… Representative value calculation circuit, 15 …… Previous value hold circuit, 16
...... Maximum value circuit, 17 ...... Filter circuit, 19 ...... Switch circuit, 21 ...... Subtractor, 22 ...... Low pass filter, 23 ...... Absolute value circuit, 26 ...... Attenuator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeru Hirahata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Ichio Nakagawa Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Home Office, Home Appliance Research Laboratory, Hitachi, Ltd. 292 (72) Inventor Nao Suzuki 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture

Claims (5)

[Claims] 1. A frame memory for inputting a digitized television signal pixel by pixel and delaying and outputting for one frame period, a television signal before being input to the frame memory and an output from the frame memory. 1
A television signal delayed by the frame period is input and a motion detection circuit for detecting the amount of motion of an image from both signals, and a motion amount output from the motion detection circuit is input, and then about one field is input. A motion amount processing circuit that creates and outputs a motion control signal for motion adaptive circuit control by processing the motion amount using a motion memory capable of performing signal delay of A representative value calculation circuit for calculating a representative value representing a plurality of signals representing the motion amount from the motion detection circuit is provided before inputting the motion amount output from the detection circuit to the motion amount processing circuit. A signal processing circuit, wherein the representative value is input to the motion amount processing circuit, so that the memory capacity of the motion memory can be reduced. 2. The signal processing circuit according to claim 1, wherein the representative value calculation circuit comprises a previous value hold circuit for holding a motion amount detected by the motion detection circuit for a certain period. Characteristic signal processing circuit. 3. The signal processing circuit according to claim 1, wherein the representative value calculation circuit is a circuit for obtaining the maximum value of the continuous n motion amounts detected by the motion detection circuit, and And a pre-value hold circuit for holding the signal. 4. The signal processing circuit according to claim 1, wherein the representative value calculation circuit holds a filter circuit for averaging consecutive n motion amounts detected by the motion detection circuit, and the filter circuit. A signal processing circuit comprising a pre-value hold circuit. 5. A signal processing circuit according to any one of claims 2 to 4, further comprising a switch circuit for switching a signal for controlling the preceding value hold circuit for each line, A signal processing circuit, wherein a position for thinning out a signal in the previous value hold circuit is offset for each line.