JPS62140557A - Signal separating circuit in video signal reproducing device - Google Patents

Abstract

PURPOSE:To stably and exactly separate and extract a control signal and a synchronizing signal, even when the synchronization is unstable, by setting the first and the second reference levels, based on a pedestal level and the minimum value level, when the synchronization is stable, and setting the first and the second reference levels, based on only the minimum value level, when the synchronization is unstable. CONSTITUTION:In a pedestal level detecting circuit 13, a pedestal level of a digitized video signal is detected, and in the minimum value detecting circuit 20, the minimum value level in a prescribed period of the digitized video signal is detected. When a synchronization formation discriminating signal has been supplied from a system controller 18, namely, when the synchronization is stable, a selector 144 selects the first and the second reference levels VTH1, TTH2 which has been generated by reference level generating circuits 140, 141, and in other case, namely, when the synchronization is unstable, the first and the second reference levels VTH1, VTH2 which have been generated by reference level generating circuits 142, 143 are selected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal separation circuit in a video signal reproducing device, and more particularly to a signal separation circuit that separates and extracts a control signal and a synchronization signal contained in a video signal.

In recorded information reproducing devices such as video disc players, control signals and synchronization signals contained in video signals are separated, and various signal processing is performed based on the separated and extracted control signals and synchronization signals. It is done. This signal separation is
Conventionally, this has been done by setting a reference level based on the pedestal level and using this level as the reference.

However, in the case of a disc player, for example, when the synchronization is unstable, such as when the spindle motor is rising or when a CLV disc is being served or scanned, the pedestal level detection position is not determined and its value is not determined. A problem arises in that a reference level cannot be set based on the level, and synchronous separation cannot be performed.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a signal separation circuit that can perform signal separation stably and reliably not only when synchronization is stable but also when synchronization is unstable. .

The signal separation circuit according to the present invention sets a first reference level for separating the control signal based on the pedestal level when synchronization is stable, and sets a first reference level for separating the synchronization signal based on the pedestal level and the minimum level. 2 reference levels are set, and when synchronization is unstable, the first and second reference levels are set based only on the minimum level.

Point - Jul Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In Fig. 1 (△>), an FM video signal read from a recording medium such as a video disk is passed through an input terminal 1, an analog LPF (low pass filter) 2, and an A/D converter.
(analog/digital) converter 4. The LPF 2 removes aliasing distortion in A/D conversion, but the LPF 2 removes aliasing distortion in A/D conversion.
ωS is the sampling frequency at the time of A/D conversion) or above), the LPF 2 may be omitted if there are very few components.

The digitized FM video signal output from the A/D converter 4 is supplied to a digital BPF (band pass filter) 6. This digital BPF 6 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM audio signal, and supplies the extracted components to the FM detection circuit 7 at the next stage.

As shown in FIG. 2, the digital BPF 6 includes, for example, delay circuits 60+ to 60n connected in series to delay one clock, the input signal of the delay circuit 60+, and each output signal of the delay circuits 60+ to 60n. An FIR filter (acyclic digital filter) is used, which is composed of multipliers 610 to 61n that multiply by a multiplication coefficient kq-kn, an adder 62 that adds the outputs of each multiplication, and a latch circuit 63 that latches the added output. multiplier 610
By appropriately selecting □-kn for each multiplication coefficient of .about.61n, desired amplitude characteristics and group delay characteristics can be obtained. Therefore, when group delay distortion occurs due to the analog LPF 2, by making the group delay characteristics of the digital BPF 6 inverse to those of the analog LPF 2, the digital F
M video signals can be supplied. Also, analog L
If the group delay distortion of PF2 is small and can be ignored, or if analog LPF2 is deleted, use digital BPF.
By using a phase linear filter for 6, a signal without group delay distortion can be obtained. In Figure 2,
The coefficient Ko-Kn of the digital BPF 6 is symmetrical about n (Ko = Kn).

K+-Koze...), it becomes an ideal phase linear filter.

The FM detection circuit 7, for example, as shown in FIG. 1(A),
A Hilbert transformer 70 performs Hilbert transform on a digitized FM video signal, a delay circuit 71 delays the digitized FM video signal by n sample periods, and each output signal of the Hilbert transformer 70 and delay circuit 71 is squared. A sum-of-squares circuit 72 for adding, a delay circuit 73 for delaying the output signal of the delay circuit 71 by one sample period, a multiplier 74 for multiplying each output signal of the delay circuit 71.7.3, and this multiplier 74. and a divider 75 that divides the output signal of the square sum circuit 72 by the output signal of the square sum circuit 72. The Hilbert transformer 70 is composed of a transversal filter and the like.

Furthermore, the delay time of the delay circuit 71 is determined by the Hilbert transformer 70.
This corresponds to the delay time of The FM detection circuit 7 having such a configuration is disclosed in Japanese Patent Application No. 59-2624 by the applicant of the present application.
Proposed in No. 81.

In FIG. 1(B), in the video L P F 10 to which the detection output of the FM detection circuit 7 is supplied, only the baseband component of the video signal is extracted from the detection output. The cutoff frequency of the video PFIO is set to, for example, 4.2 MHz in the case of the NTSC system. FIG. 3 shows the configuration of an example of the video PFIO.
PFIO operates at a clock frequency of 4Nfsc (N is an integer of 2 or more) and removes the carrier wave component contained in the FM-detected digital video signal and extracts only the baseband component. Filter (FIR filter) 100 and this FIR filter 1
a downsampling circuit 101 that downsamples the output of 00 to a clock frequency of 4fsc;
and a subsequent cyclic digital filter (IIR filter) 102 which operates at a clock frequency of 1 and compensates the phase characteristics of the digitized video signal.

In Fig. 4 (A) to (C), each part (A) in Fig. 3 is shown.
-(C) spectra are shown.

The FM detection output (Δ) includes not only the baseband video signal but also its second harmonic component, and the FIR filter 10
By passing through 0, only the baseband video signal (B) is derived at the output end. This baseband video signal (B) is transmitted to the downsampling circuit 101
The clock frequency is downscaled from the clock frequency of 4Nfsc to the clock frequency of 4fsc. The spectrum after downsampling is the same as that in Figure (B).

By lowering the sampling frequency in this way, it is possible to save time and reduce the amount of hardware.

Note that since the band of the digitized video signal is narrowed to approximately 4.2 MH2 by passing through the FIR filter 100, there is no problem even if the sampling frequency is lowered. After downsampling, the baseband video signal (B) is compensated for its phase characteristics by an IIR filter 102. The spectrum (C) after phase compensation is also the same as that in Figure (B).

In the case of video discs, etc., the signal processing system for the playback signal has conventionally been analog-based, so it is assumed that the phase of the analog-designed video and PF will rotate when recording information. Information is recorded by distorting the phase in the opposite direction by inversely compensating for the phase distortion. Therefore, when playing back a video disc with such a recording format and digitally processing the playback signal, it is necessary to further compensate for the inverse compensation valve for phase distortion during recording, and compensation for this phase characteristic is necessary. is IIR filter 10
It is done in 2. FIG. 5 shows the phase characteristics of the IIR filter 102.

6 to 8 show examples of specific configurations of the FIR filter 1001, the downsampling circuit 101, and the IIR filter 102. First, in Figure 6,
The FIR filter 100 includes delay circuits 1031 to 103n that are connected in series to delay one clock, and the input signal of the delay circuit 103i and the delay circuits 1031 to 103n.
A latch circuit consisting of multipliers 1040 to 104n that multiply each output signal of 103n by a multiplication coefficient k(, -kn, an adder 105 that adds each multiplier output, and a D-type flip-flop etc. that latches this addition output. Consisting of 106,
The clock frequency of the delay circuits 1031 to 103n and the latch circuit 106 is set to 4Nfsc. As shown in FIG. 7, the downsampling circuit 101 is constituted by a latch circuit 107 consisting of a D-type flip-flop or the like, and its clock frequency is set to 4 fsc.

As a result, the data input to the latch circuit 107 is N
- Output every other item.

Moreover, as shown in FIG. 8, the IIR filter 102
A multiplier 108o that multiplies an input signal by a multiplication coefficient kO, an adder 109 that uses this multiplication output as one addition input, a latch circuit 110 consisting of a D-type flip-flop or the like that latches this addition output, and an adder 109 Delay circuits 1111 to 111n connected in series to each other sequentially delay the addition output by one clock, and these delay circuits 1111 to 1.
Multiplier 1 that multiplies each output of 11n by ~kn.
The clock frequency of the device circuit 110 and the delay circuits 1111 to 111n consisting of 081 to 108n is 4fs.
c1. : Set. In this circuit configuration, by appropriately setting )-kn in each multiplication coefficient of the multipliers 108o to 108n, a phase characteristic as shown in FIG. 5 can be obtained.

In the video LPF 10 described above, the phase straight line FI
By using the R filter 100 at the front stage, all phase compensation can be determined only by the IIR filter 102 at the rear stage, and the amplitude characteristics can be adjusted without changing the phase characteristics.

Note that the downsampling is performed using the L I R filter 102.
This is done in front of the IIR filter 102.
This is because all operations must be completed within one clock period. Downsampling with IIR filter 10
In order to carry out the process after 2, for the above-mentioned reasons, Vibration processing is impossible, and the number of operations must be reduced or high-speed elements must be used, but there are limits to this. On the other hand, if downsampling is performed before the IIR filter 102, the clock cycle will naturally become longer, and if the number of operations increases accordingly, more accurate characteristics will be obtained and stability will also increase.

In the video LPF 10 configured as described above, the front stage F
The IR filter 100 is operated with a 4Nfsc clock, and its output is processed by a downsampling circuit 101 at 4fsc.
However, as shown in FIG. 9, downsampling is performed before the arithmetic circuit in the FIR filter 100', and the clock after the arithmetic circuit is downsampled at 4fs.
It is also possible to configure it to operate with the clock of c. At this time, the downsampling circuit 101 is not necessary.

That is, in FIG. 9, the FIR filter 100' includes delay circuits 1121 to 112n connected in series that delay one clock, and input signal and delay circuit 1.
latch circuits 1130 to 113n consisting of D-type flip-flops that latch each output signal of 121 to 112n;
Multipliers 1140 to 114n multiply each latch output of these latch circuits 1130 to 113n by a multiplication coefficient of □-kn.
, an adder 115 that adds these multiplication outputs, and a latch circuit 116 consisting of 70 D-type flips that latches this addition output, and delay circuits 1121 to 112n.
The operation of the latch circuits 1130 to 113n in the next stage is performed with the clock of 4Nfsc, and the operation of the final stage arithmetic circuits (multipliers 1140 to 114n,
The operation of the adder 115 and latch circuit 116) is 4 fsc.
The configuration is such that the operation is performed using the same clock.

In the iR filter 00- with such a configuration, the calculation time is 4 fs.
C clock, unnecessary calculations are omitted, and since the clock period is longer, the number of calculations can be increased, and relatively, compared to the FIR filter 00 with the above-mentioned configuration.
This means that the circuit scale can be further reduced.

In addition, in order for the FIR filter to have a phase linear characteristic in FIGS. 6 and 9, the coefficients Ko to Kn must be symmetrical about the center (Ko = l(n,
K+ = Kr+-+,--).

Again in FIG. 1(B), the digitized video signal that has passed through the video LPF 10 is sent to the de-emphasis circuit 11.
an adder 12 through which the pedestal clamping means is constituted;
, pedestal level detection circuit 13 and signal separation circuit 14
supplied to

By the way, when performing digital signal processing, it is clear that a smaller number of quantization bits per word n (bit/word) is advantageous in designing a circuit.

However, when considering the FM detection output, the output level is constant in the steady state of the disc player, but it is unsteady due to the rise of rotation of the spindle motor 24, search and scan during CLV (constant linear velocity) disc playback, etc. In this state, the DC component of the video signal changes significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle servo circuit 23 cannot be locked, and the clock generation circuit 21 cannot be synchronized, so the steady state cannot be achieved forever, so the synchronization signal can be detected even in the unsteady state. You need to be able to do it. For this purpose, the number of bits n must be set based on the unsteady state.

Therefore, at least the number n of bits from the input of the signal separation circuit 14 to the output of the de-emphasis circuit 11 is set to a number of bits with a wide dynamic range that is sufficient even if the pedestal level changes significantly based on the unsteady state. n
, (bit/word). As a result, not only in a steady state but also in an unsteady state, the signal separation circuit 14
This means that the synchronization signal can be reliably detected.

The pedestal level detection circuit 13 detects the pedestal level V
po is detected and the pedestal level Vp is determined from the reference voltage VRF.
The video signal is digitally pedestally clamped by generating an output (VRF - VP D ) obtained by subtracting o and adding it to the digitized video signal in an adder 12 to cancel the variation in the pedestal level. The pedestal-clamped n 1 (bit/word) data is n 2 (bit/w) at the output of the adder 12.
bits are reduced to the data of (nl<nl >
. nl is determined by the dynamic range and resolution required for a video signal in a steady state. This bit reduction facilitates the circuit design of the adder 2 and subsequent parts. In addition, by performing pedestal clamping, the signal level of the digitized video signal will be within the dynamic range of n 2 (bit/word) not only in steady state but also in unsteady state, so when scanning CLV. This means that images can be viewed even in unsteady conditions such as.

In the above configuration, regarding the dynamic range of each circuit constituting the digital signal processing system, the dynamic range up to the input of the signal separation circuit 14 is set to nl (bit/word), and regarding video processing, a pedestal clamp is used digitally. After that, n z (bit/w
However, as shown in Figure 10, the digital frequency
It is also possible to separate the output of the M detection circuit 7 into two systems, a video processing system and a signal separation system, and make the number of bits n for each prefecture different.

In other words, in FIG. 10, the number of bits in the signal separation system is n
(bit/*ord). Konon, (
bit/vord) is supplied to the signal separation circuit 14 via the LPF16. The LPF16 may be any filter that has characteristics that allow the synchronization signal to be detected from its output, and therefore the configuration can be simplified by using simplified filter coefficients. On the other hand, regarding the video processing system, the number of bits n 2 (bit/w
ord) dynamic range. nl is determined by the dynamic range and resolution required for a video signal in a steady state.

In this way, the digital FM detection output is nl.

By separating into two systems (bit/vord), the circuits after the video LPF 10 can be designed by considering only the steady state case, which simplifies the circuit configuration. This means that the synchronization signal can be reliably detected even in an unsteady state such as the rise of the signal.

In addition, in such a circuit configuration, in an unsteady state, there may be cases where the image cannot be seen due to changes in the pedestal level, but this is only possible if the image can be seen in the steady state, and the synchronization signal can be reliably detected in the unsteady state. It is based on ideas. However, in the CLV scan, since the clock generation circuit 21 is synchronized to some extent, changes in the pedestal level are often small, and in this case, the image can also be viewed.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit 13. In this figure, LPFl
The digitized video signal (a) from which the color burst has been removed in step 17 is supplied to a pedestal sampling circuit 118 and a sync separation circuit 119, respectively. Synchronous separation circuit 1
At step 19, the synchronization signal (b) included in the digital video signal (a) is separated and extracted, and the synchronization signal (b) is supplied to a rise detection circuit 121 and a fall detection circuit 120, respectively. The falling detection circuit 120 receives the first gate signal (
The rising detection circuit 121 detects the falling of the synchronizing signal (b) during the period in which the second gate signal (d) is generated, and the rising of the synchronizing signal (b) during the period in which the second gate signal (d) is generated.

The timing signal generation circuit 122 generates a first gate signal (C) based on a clock signal during a period in which a dropout detection signal (0) from a dropout detection circuit 17 (see FIG. 1(A)), which will be described later, is not generated. is generated, and then a dropout detection signal (a
) is not generated, a second gate signal (d>) is generated.

The sample period signal generation circuit 123 generates a sample period signal (e) of a certain period in response to the detection output of the rising edge detection circuit 121, and supplies it to the pulse generation control circuit 124.

The pulse generation control circuit 124 is, for example, a three-man power AN that receives the sample period signal (e) from the sample period signal generation circuit 123 and the detection signals (Q) from the dropper 1 to
Set the detection outputs of the D gate 125 and the rising edge detection circuit 121 (S), set the output of the AND gate 125 as the reset (R) input, set the clock signal as the clock (CK) input, and set the Q output of the AND gate 125. It consists of a single SR flip-flop 126, and supplies the output pulse of the AND gate 125 to the pedestal sampling circuit 118 as a sampling pulse (f). The pedestal sampling circuit 118 is composed of a D-type flip-flop or the like, and latches the pedestal level Vpo of the digitized video signal in response to the sampling pulse (f). The sampled pedestal level Vpo is
In the arithmetic circuit 127, it is subtracted from the reference level VRF and averaged among a plurality of H's to obtain (VRF-Vpo).

This is the bell detection output.

Figure 12 shows the operating waveforms of the circuit in Figure 11, and Figures (a) to (g) show the waveforms of each part (a) to (a) in Figure 11, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the fall of the horizontal synchronization signal included in the synchronization signal (b) is detected by the first gate signal (C), and the horizontal synchronization signal is detected using this fall as a reference. After a time corresponding to the width, a second gate signal (d) is generated to detect the rise of the horizontal synchronization signal (b), and the sample period signal (
e), it is possible to reliably capture the horizontal synchronizing signal and sample the pedestal level on the back porch during the horizontal blanking period. Further, since the color burst is removed from the digitized video signal (a) by the LPF 17, it is possible to generate a sample period signal (e) having a wide period including the portion where the color burst was present.

The sampling pulse (f) is the sampling period signal (
It is generated during the generation period of e) and during the non-occurrence period of the dropout detection signal 1), and has a pulse width corresponding to one clock of the clock signal. Therefore, if there is a dropout shorter than the sample period, as shown in Figure 12 (f >
As shown by the two-dot chain line, sampling for one clock can be reliably performed in 1H without the influence of dropout. Also, 1st. Second gate signal (C).

(d) is generated excluding the part where dropout occurs, so even if a false horizontal synchronization signal is generated due to dropout, a sample period signal will not be generated erroneously based on this horizontal synchronization signal. It is.

Output of pedestal level detection circuit 13 (VRF-Vpo
) is added to the video signal by the adder 12 in FIG. 1(B), thereby performing pedestal clamping. The pedestal level Vpo is also supplied to the signal separation circuit 14 in FIG. 1(8), and in this circuit 14, synchronization signals and control signals are separated using the pedestal level Vpo as a reference level.

Note that in the above configuration, the LPF 117 in the input section can be omitted, but if it is omitted, it is necessary to generate the sampling period signal in a period other than the color burst section. Furthermore, the configuration of the pulse generation control circuit 124 is not limited to the circuit configuration described above, and various configurations are possible, such as using a microprocessor, for example. Also,
The LPF 117 and the synchronization separation circuit 119 can be respectively replaced with an LPF 145a and a signal detection circuit 145C in FIG. 21, which will be described later, and these circuits may be used in common.

FIG. 13 shows the falling detection circuit 12 in FIG.
0, an example of a specific circuit configuration of a rising edge detection circuit 121, a timing signal generation circuit 122, and a sample period signal generation circuit 123 is shown. In this figure, the fall detection circuit 120 includes a D-type flip-flop 128 that uses the synchronization signal (b) as a data (D) input and an O-clock signal as a clock input, and an inverter that receives the synchronization signal (b) as an input. 129A, and a three-man power NAND gate 129B that uses the Q output of the flip-flop 128, the first gate signal (C) from the timing signal generation circuit 122, and the output from the inverter 129A. The Q output is the synchronization signal (b) delayed by one clock, and is output from the NAND gate 129B.
Then, when the synchronization signal (b) falls while the first gate signal (C) is at a high level, that is, the horizontal synchronization signal falls, all three signals become high level at the moment of the fall. A low level detection output is generated.

The timing signal generation circuit 122 includes the falling detection circuit 1
A 1H counter 13'O takes the detection output of 20 as a load (L) input and a clock signal as a clock input, and the output of this counter 130 is decoded and the first
．． The gate circuit 131 generates second gate signals (c) and (d). The 1H counter 130 counts the 1H period clock in synchronization with the falling edge of the horizontal synchronization signal, and when the video signal is NTSC, the clock is 14.3MH2-4fsc=910fH (f
+ is the horizontal scanning frequency) and becomes a 910 progress counter. Furthermore, the gate signals (C) and l) are not generated during the period when dropout occurs.

Although not shown in the figure, if the 1H counter 130 is not loaded several times in succession, the first gate signal (C) is forced to a high level and the horizontal synchronizing signal is raised. Detect the drop. This is to prevent the 1H counter 130 from being a-coded with a 1/2H shift due to the equalization pulse, which will no longer be loaded by the horizontal synchronizing signal, making it impossible to detect the pedestal level. It is.

The rising edge detection circuit 121 is the timing signal generation circuit 1
22 as a data (D) input and a synchronization signal (b) as a clock input, the second gate signal (d)
When the signal (b) rises, that is, the horizontal synchronizing signal rises while the signal (b) is at a high level, a high level detection output is generated from the Q output terminal. Sample period signal generation circuit 1
23 loads the detection output of the rising edge detection circuit 121 (
L) Consists of a 7-bit counter 133 that serves as an input and an enable (EN) input, and is loaded with "90" until just before the horizontal synchronizing signal rises, starts counting at the rising edge of the horizontal synchronizing signal, and continues counting from "'96" to "'96". A sample period signal (e) is output with a period of "127" as a sample period. When the count exceeds 127# and reaches II O71, the D-type flip-flop 132 is cleared and the load input and enable input are set to low level to return to the load state and stop.

Note that the fall detection circuit 120 and the timing signal generation circuit 122 are similar to the HV separation circuit 1 in FIG. 21, which will be described later.
45d and a part of the timing signal generation section of the system controller 18 in FIG.
The D-type flip-flop 180, inverter 181A, and NAND gate 181B in FIG.
1 to the 1H counter 183 and gate circuit 182 in FIG.
They may be shared with A.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 13, in which parts equivalent to those in FIG. 11 are designated by the same symbols. In this figure, LPF11
The synchronization signal (b) separated and extracted by the synchronization separation circuit 119 from the digitized video signal (a) that has passed through the synchronization separation circuit 119 is supplied to the fall detection circuit 134. The fall detection circuit 134 detects the fall of the synchronization signal (b) during the generation period of the gate signal (C) output from the timing signal generation circuit 135, and supplies the detection output to the timing signal generation circuit 135.

The timing signal generation circuit 135 generates a gate signal (C) based on the clock signal during the non-generation period of the dropout detection signal (f), and also generates the gate signal (C) based on the clock signal during the period when the dropout detection signal (f) is not generated.
34 generates a sample period signal (d) at the front porch of the horizontal synchronizing signal 1H after the falling detection timing as a reference, and supplies it to the pulse generation control circuit 136.

The pulse generation control circuit 136 includes, for example, a three-man power AND gate 137 that receives the sample period signal (d) and the dropout detection signal (f) from the timing signal generation circuit 135, and a set signal from the timing signal generation circuit 135. Set (S) input, reset the output of AND gate 137 (R) input, clock signal to clock (CK)
It consists of an SR flip-flop 138 which serves as an input and whose Q output is used as a single input of an AND gate 137.
The output pulse of gate 137 is the sampling pulse (e)
The signal is supplied to the pedestal sampling circuit 118 as a signal.

The subsequent operations are the same as those shown in FIG.

Figure 15 shows the operating waveforms of the circuit in Figure 14, and Figures (a) to (f) show the waveforms of each section (a) to (f) in Figure 14, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 14, the fall of the horizontal synchronizing signal is detected using the gate signal (C), and after generating a set signal using this fall as a reference and opening the AND gate 137, Since the sample period signal (d) is generated corresponding to the front porch after one day,
The pedestal level can be detected even during the vertical blanking period. Further, after sampling the pedestal level, if the falling edge of the horizontal synchronizing signal cannot be detected while the gate signal (C) is being generated, the falling edge detection circuit 134 generates a pedestal enable signal to detect the sampled level. It is possible to notify the next stage circuit that the pedestal level is invalid, or to hold the previously detected pedestal level. For example, by inputting the pedestal enable signal to the arithmetic circuit 127,
The circuit 127 previously outputted (VRt--Vp o
) will continue to be output.

The gate signal (C) and the sampling period signal (d> are generated except for the part where the dropout occurs, and the pulse generation control circuit 136 generates the sampling pulse (e) for one clock. without accidentally generating the sample period signal (d);
If the length of the dropout during the sample period does not exceed the sample period, it is possible to reliably sample one clock per 1H without the influence of dropout, as shown by the two-dot chain line in Fig. 15(e). can.

As for the example of diversion, the same aspect as in the case of the configuration shown in FIG. 11 can be considered.

FIG. 16 shows the falling detection circuit 13 in FIG.
4 and a specific circuit configuration of the timing signal generation circuit 135 are shown. In this figure, the fall detection circuit 134 is a JK flip-flop 1 which receives the synchronization signal (b) as an inverted clock input and receives the gate signal (C) as the J input.
If the Domei signal (b) falls, that is, the horizontal synchronization signal falls while the gate signal (C) is at high level, the Q output becomes high level, and thereafter the reset signal becomes low. The Q output is held at a high level until it transitions to a high level. When the reset signal goes low, the Q output also goes low.

The timing signal generation circuit 135 includes a D-type flip 70 tube 140 which uses the Q outputs of 13 JK flip-flops as data (D) input and a clock signal as a clock input, the Q output of this flip-flop 140 as D input, and the tarok signal as a clock input. D-type flip-flop 141 as clock input
and load the 0 output of this flip-flop 141 (L
) input, a clock signal as a clock input, and a gate circuit 143 that decodes the output of this 1H counter 142 and generates a gate signal and a reset signal in a predetermined period.
Immediately after the Q output of 39 becomes high level, a load pulse is generated for one clock from the D-type flip-flops 140 and 141 to load the 1H counter 142. 1H counter 142 that counts the period of one day in synchronization with
If the video signal is NTSC, the clock is 14.3M.
Hz=4fsc-91Of+<fH is the horizontal scanning frequency), and becomes a 910-decimal counter.

In the gate circuit 143, the gate signal (C) is not generated during the period when dropout occurs. Further, the reset signal is generated as a pulse once every 1H with a sufficient interval from the gate signal (C) so that the pedestal enable signal is recognized by the next stage circuit.

Note that in the circuit shown in FIG. 16, the gate signal (C) is reduced to 1/2 due to the loading of the 1H counter 142 by the equalization pulse.
Measures similar to those shown in FIG. 13 are taken to prevent H deviation.

Further, it is also possible to replace or share the circuit between the circuit in FIG. 16 and the H-2 separation circuit 145d in FIG. 21 and the circuit in FIG. 31, as in the case of FIG. 13.

In addition, in each of the embodiments of the pedestal level detection circuit 13 described above, the video signal has been described as being digitized, but the application is not limited to digital video signals, and can also be applied to analog video signals. The same applies.

Next, the dropout correction circuit 1 in FIG. 1(B)
9 will be explained. This dropout correction circuit 19
corrects the dropout of the digitized video signal output from the adder 12, but regarding the dropout of the vertical synchronization signal part, it is replaced with a correction signal set in advance to a level equal to the signal level of the vertical synchronization signal. By doing so, the dropout is corrected.

The configuration of this dropout correction circuit 19 is shown in FIG. In this figure, the digitized video signal is supplied to the first selector switch 190, and the output of the switch 190 is passed through the first delay circuit 191 to the second delay circuit 1.
92 and 3.58 MH2 BPF193.

Here, when the delay amount of the BPF 193 is d, the delay amount of the first delay circuit 191 is 1 H-d, and the second delay circuit 192 (7) amJHtd is 1 constant tL. BPFI
The output of 93 is supplied to an adder 195 via a multiplier 194 having a coefficient of -2, and is added to the output of the second delay circuit 192. The addition output of the adder 195 becomes the independent power of the second changeover switch 196, and the output of the switch 196 becomes the power of the first changeover switch 190. Switching of the first changeover switch 190 is controlled by a dropout detection signal supplied from the dropout detection circuit 17 (see FIG. 1(A)).

The address generation circuit 197 generates a field identification signal, horizontal address, and vertical address based on the horizontal synchronization signal and vertical synchronization signal supplied from the signal separation circuit 14, and generates a field identification signal, a horizontal address, and a vertical address based on the address information from the vertical synchronization level generation circuit 198. A correction signal is generated which is set to a level equal to the signal level of the known vertical synchronization signal, and the second
The changeover switch 196 is controlled by someone else. In the 19 switching signal generation circuits, a vertical synchronization period signal is generated during the generation period of the vertical synchronization signal based on the vertical address, and this vertical synchronization period signal becomes a switching signal for controlling the switching of the second changeover switch 196.

By the way, as shown in FIG. 18, the signal (A) before correction
If a dropout occurs in the vertical synchronization pulse part of , the dropout can be corrected by replacing this part with the previous signal (B) one tone before.
Since there is no horizontal correlation, the vertical synchronizing pulse may be misaligned in the corrected signal (C) (in Figure 18, there is a 1/2H misalignment between the O-marked parts). ).

If the vertical synchronizing pulse is misaligned in this way, there is a possibility that field errors will occur in subsequent video equipment. However, prohibiting vertical synchronization pulse dropout correction may cause synchronization disturbance.

Therefore, as shown in FIG. 17, when a dropout occurs in the vertical synchronization pulse portion, the signal level is equal to that of the vertical synchronization signal output from the vertical synchronization level generation circuit 198 instead of the signal 1H before. The level correction signal is
By supplying the signal to the selector switch 190 and replacing it with a digitized video signal, dropout can be corrected without causing a positional shift of the vertical synchronizing pulse.

Note that in FIG. 17, dropout correction is performed using a signal from one day ago, but at this time, the phase of the chroma signal will become reversed if left unchanged. Therefore, the first
The circuit surrounded by the broken line in FIG. 7 inverts the phase of the chroma signal, thereby making it possible to colorize the dropout correction signal. Therefore, when dropout correction is performed only on a luminance signal (monochrome), when a signal 2H earlier (clock signal is in phase), etc., the circuit shown in the broken line is excluded. The address generation circuit 197, vertical synchronization level generation circuit 198, and switching signal generation circuit 199 may be included in the system controller 18, and replaced with 1H counter 183° gate circuit 182A, 1 frame counter 189° gate circuit 182B, etc. in FIG. You may.

The dropout detection circuit 17 in FIG. 1 (Δ) has a level comparator configuration, and as shown in FIG. When it is detected that the signal level of the squared signal (B) of the envelope component of A) has become below a predetermined value, a dropout detection signal (C) is output. According to this configuration, the dropout detection circuit can be configured by simply adding a level comparator to the FM detection circuit 7, so that dropout detection can be reliably performed with a simple circuit configuration, and all detection operations can be performed. Since this is done digitally, stable characteristics can be obtained.

Note that there is a possibility that the detection output is disturbed by ringing that occurs in the output of the sum-of-squares circuit 72 (the area surrounded by a dashed line in FIG. 19(B)) due to a sudden change in the envelope. The dropout detection signal (D) is also output as a dropout section in the n+ point before the signal level of the output signal (B) of 72 becomes below a predetermined value and the 02 point after the level becomes above a predetermined value. This allows subsequent corrections to be performed reliably. At this time, there is a possibility that ringing will occur due to the delay of the Hilbert transformer 70, so nl.

nl is set equal to or larger than the delay time of the delay circuit 71.

The signal separation circuit 14 in FIG. 1(B) separates and extracts control signals such as frame numbers and stop codes along with color burst signals, horizontal synchronization signals, vertical synchronization signals, etc. contained in the digitized video signal. For this signal separation, as shown in FIG.
2 is set.

The configuration of this signal separation circuit 14 is shown in FIG.

In this figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum level of the digitized video signal within a predetermined period. The configuration of the minimum value detection circuit 20 will be explained in detail later. Based on each detection level of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the first. Second reference level VTH
I.

VTI-12 is set, but the reference level generation circuit 140 generates a first reference level VTHI by adding a constant value to the detected level based only on the detection level of the pedestal level detection circuit 13, and generates the first reference level VTHI. The level generation circuit 141 generates an intermediate value between the two levels as a second reference level V-H2 based on the detection levels of the pedestal level detection circuit 13 and the minimum value detection circuit 20. The reference level generation circuits 142 and 143 are minimum value detection circuits.
Based only on the detection level of the first. second reference level V
Generates THI and V engineering H2.

Each output of the reference level generation circuits 140 to 143 is supplied to a selector 144, and this selector 144 selects the reference level generation circuit 140 when the synchronization establishment determination signal is supplied from the system controller 18, that is, when the synchronization is stable. , 141. second reference level V
THI and VTI2 are selected, and in other cases, that is, when the synchronization is unstable, the first level generated by the reference level generation circuits 142 and 143 is selected. Second reference level VTHI, VTI-12
Select. Note that the system controller 18 determines whether or not synchronization is established by comparing a reference synchronization pulse based on an internal clock with the extracted synchronization pulse. The first one selected by the selector 144. The second reference level VTI-11°VTI2 is supplied to the signal detection circuit 145C, and the signal detection circuit 145C detects the LPF1 based on these reference levels VTH1, Vv+-z.
The control signal A is output from the digitized video signal that has passed through 45a.
and the synchronization signal B are separated and extracted.

That is, in the signal separation circuit 14 having the above-described configuration, 1H
When the synchronization is stable, the pedestal level and the first level set based on the pedestal level and the minimum level. Based on the second reference level VTH1, VTI-12, or at the start of rotation of the spindle motor 24 or C
When synchronization is unstable, such as during LV disk search or scanning, the pedestal detection position is not determined and its value is not determined, so the first. Control signal A and synchronization signal B are separated and extracted based on second reference levels VTHI and VTI-12. According to this, signal separation can be performed stably and reliably not only when synchronization is stable but also when synchronization is unstable. The separated synchronization signal B is input to the HV separation circuit 145d, and the horizontal synchronization signal is separated by detecting a fall when the HS gate signal from the system controller 18 is at a high level. Further, the synchronization signal B is subjected to integration processing in the HV separation circuit 145d, and vertical and vertical synchronization signals are separated based on a predetermined reference level. The digitized video signal is transmitted through LPF 145a and fscBPFl 45b.
A color burst signal containing a color signal component is output from the fscBPF 145b.

By the way, regarding the detection of the synchronization signal in the signal detection circuit 145G, as shown in FIG. 22, the digitized video signal is sampled at every predetermined clock (the x mark in the figure is the sample point), and the signal level of the synchronization signal is at the reference level. VT
The synchronization signal is detected at the time when H2 is exceeded.

The configuration of this synchronization signal detection circuit is shown in FIG.

In this figure, a reference level generation circuit 141 (or 143
) to (7) a subtractor 14 which receives as input the reference level vTH2 and the digitized video signal that has passed through the LPF 145a.
6 calculates the level difference between the signal level of the video signal and the reference level VTH2 at each sample point, and detects the sample point where the video signal level is lower than the reference level VTH2 as a synchronization signal. The level difference signal calculated by the subtracter 146 is sent to a delay circuit 147 and a sign determination circuit 148.
and storage bags for ROM (read-only memory), etc.
149. The delay circuit 147 has a delay amount equivalent to 100k, delays the level difference signal from the subtracter 146, and supplies it to the sign determination circuit 148 and the storage device 149. The sign determination circuit 148 detects the level difference at the sample point a immediately before the output A of the delay circuit 147 is positive and the output B of the subtracter 146 is negative, that is, the output A of the delay circuit 147 exceeds the reference level VT)+2. and the output B of the subtracter 146 is determined to be a level difference at the sample point immediately after exceeding the reference level VTH2, and the determination signal is stored in the storage device 1.
Supply to 49.

For example, a time table as shown in FIG. 24 is stored in advance in the storage device 149, and the storage device 149 stores the outputs of the delay circuit 147 and the subtracter 146 when the determination signal is generated from the sign determination circuit 148, That is, corresponding time information is output based on the level differences A and B at the two sample points a and b. Input A of the storage device 149;
B and the output are both 4-bit data, for example, and the first 1 bit of the 4 bits of inputs A and B is a sign bit and is expressed as a two's complement number. Storage device 14
The time information that is the output of 9 is the time point C when the signal level of the synchronization signal exceeds the reference level VTH2 and the sample point a or b.
This makes it possible to accurately detect the position of the falling edge of the synchronization signal even if the time point C does not coincide with the sample point in time.

Next, the minimum value detection circuit 20 in FIG. 21 will be explained. In FIG. 25, the counter 2oO generates a first period pulse every period equivalent to one day by counting the clock, and generates a second period pulse every period longer than one day. Occur. These period pulses are supplied to the selector 201, and in the steady state the first
The second period pulse is selected and supplied to the register 202 and the averaging circuit 203 in an unsteady state where the rotation of the disk is unstable, such as when the spindle motor 24 starts to rotate or during a CLV search or scan. Ru.

The comparator 204, which uses the digitized video signal output from the LPF 145a, compares its input data A with the register 2.
The data B stored in the register 202 is compared with the data B stored in the register 202 every time a clock occurs, and the smaller data is supplied to the register 202. However, the comparator 204 is designed to stop its operation when dropout occurs. Since the register 202 is reset by the first or second period pulse supplied from the selector 201, the smallest value from the previous reset time will be stored in the register 202. The minimum value stored in the register 202 is loaded into an averaging circuit 203 every time a first or second period pulse occurs, and the averaging circuit 203 averages each minimum value of two or more detection periods and finally calculates the minimum value. Output as the minimum value.

In such a configuration, since the minimum value ' of the video signal usually appears during the synchronization signal period, a period of one day is set as the detection period (first period pulse generation interval), but the rotation of the spindle motor 24 At startup and CLV
In an unsteady state such as during a search or scan, the length of the 1H period fluctuates because the rotation of the disk is not stable.

At this time, if minimum value detection is performed at normal intervals based on the first period pulse, there may be cases where the synchronization signal is not included within the interval. Therefore, in an unsteady state, by using a second period pulse that is generated every period longer than the 1H period, the synchronization signal will be included within the detection period, so the minimum level can be detected reliably. This means that fluctuations in the minimum level can be reduced. In addition, when a dropout occurs, a value that is sometimes smaller than the signal level of the synchronization signal may occur, but by stopping the operation of the comparator 204 and inhibiting the detection operation during the dropout period, This makes it possible to prevent erroneous detection of the minimum value.

In addition, the counter 200 is activated by the dropout detection signal.
Since the counter 200 starts counting the predetermined period again after the dropout, even if the synchronization signal part is lost due to a dropout, the level of the synchronization signal part will be reliably detected before the next period pulse is generated. can be done.

The clock generation circuit 21 in FIG. 1(B) generates 4 fsc (fsc is the subcarrier frequency) based on the reference horizontal synchronization signal from the reference signal generator 22 or the horizontal synchronization signal or color burst signal from the signal separation circuit 14. It generates a clock of 4Nfsc (for example, 12fsc) and has a PLL (phase locked loop) circuit configuration. 4fsc and 4 generated here
The NfsC clock is used as a clock for digital signal processing, and the sampling clock of the A/D converter 4 and the signal processing clock up to the video LPF 10 are set to 4Nfsc, and the clock from the output of the video LPF 10 is set to 4fs.
Downsample to c.

The configuration of the tarlock generating circuit 21 is shown in FIG.

In this figure, a phase comparator 210 that uses a color burst signal as a comparison reference input is connected to a sampling pulse generation circuit 21.
1, the sampling pulses CK+, C
Phase comparison is performed in response to K2. Note that when locking the PLL to the reference horizontal synchronization signal or the horizontal synchronization signal, the phase comparator 210 is not used, and another phase comparator (not shown) is used to lock the PLL to one of these signals at 2fs.
The phase is compared with the fH signal obtained by dividing c by 1/455, and the output thereof is input to the LPF 212.

Hereinafter, only the case of locking to the color burst signal will be explained. Phase comparison! The comparison output of 210 is LPF2
The oscillation frequency of V00214 is 12 fsc.
The clock is set to 12fsc, and is output as is as a clock of 12fsc, and the frequency is divided to 4fsc by a 1/3 frequency divider 215. This clock 4fsc is output as it is, serves as the sole power of the sampling pulse generation circuit 211, and is further divided into fsc by 1/2 frequency dividers 216 and 217, and becomes a comparison input of the phase comparator 210. The sampling pulse generation circuit 211 is supplied with the gate pulse generated by the gate pulse generation circuit 218 as an external power, and therefore the phase comparator 210 is supplied with the sampling pulses CK+ and CK2 only during the generation period of the gate pulse. become. The gate pulse generation circuit 218 generates a gate pulse (B) in synchronization with 4fSC based on the horizontal synchronization signal, as shown in FIG. 27, only for a period corresponding to the central portion where the amplitude of the color burst signal (A) is constant. do.

In the phase comparator 210, as shown in FIG.
The color burst signal becomes the output of the adders/subtractors 219 and 220, and each addition/subtraction output passes through delay circuits 221 and 222 and becomes the output of the adders/subtractors 219 and 220, and is divided by the divider 223. The addition/subtraction (±) control of the adders/subtractors 219 and 220 is performed using the clock pulse fsc shown in FIG.
Based on (B), sample point S+, addition at 82,
At sample point 33.84, subtraction is performed. However, when a track jump is performed during still image playback, etc., the phase of the color burst signal changes by 180", so the clock pulse fsc changes every time a track jump occurs.
Invert the phase of (B) to maintain PLL lock. This is controlled by the 1/2 frequency divider 2 by the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).
This is done by controlling 17.

Further, the sampling pulse generation circuit 211 is composed of a D-type flip-flop, and has a sampling clock CK+
, CK2 is synchronized with 4fsc, and 1 of that frequency
/2 and have opposite phases to each other, and serve as clocks for the delay circuits 221 and 222, respectively, only when the gate pulse is at a high level.

As a result, assuming that the amplitude of the color burst signal (A> is A), ΣA sinθ is derived as the output of the delay circuit 221, ΣA CO3θ is derived as the output of the delay circuit 222, and tanθ is derived as the output of the divider 223. Then, this division output tanθ is converted to tan-' circuit 2.
24, the phase difference θ can be obtained.

That is, the phase difference O in the phase comparator 210 can be calculated from the following equation.

θ−tan' (Σ[(St −83)/(8234
)]) Here,]S+-A-sinθ5z=A-cos
θS3−−A−sinθ 54=−A−cosθBy the way, as is clear from the above equation, if the amplitude A of the color burst signal (A) is not constant within 1H, there will be a slight error in the detected phase difference θ, and PL A change in the loop characteristics will occur due to a change in the loop gain.

However, in the clock generation circuit 21 described above, the 5I-
Sampling pulse CK+ to find 8<.

By applying a gate to CK2, phase comparison is performed only during a period in which the amplitude A of the color burst signal (A) is constant, so that the above-mentioned problem does not occur.

In the above configuration, phase comparison is performed only in the central portion of the color burst signal by applying a gate to the sampling pulse, but it is of course possible to apply a gate to the color burst signal itself. . In this case, since it is a digital gate, only the central part of the color burst signal can be extracted more accurately than an analog switch or the like. Furthermore, in FIG. 26, the arrangement relationship between the LPF 212 and the D/A converter 213 may be reversed.

In FIG. 1(B), a reference signal generator 22 includes a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronization signal. The spindle servo circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronization signal from the reference signal generator 22 and the horizontal synchronization signal from the signal separation circuit 14. The chroma inversion circuit 25 adjusts the chroma (color) as necessary to maintain color framing even during special playback such as still playback and slow playback.
A phase inversion of the signal is performed.

The configuration of this chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is sent to a one-day delay circuit 270.
, are supplied to the adder 271. After the signal level of the output of the adder 271 is halved by the level adjustment circuit 272,
It is supplied to a subtracter 273. The subtraction output of the subtracter 273 is supplied to the adder 275 via a phase linear acyclic digital BPF 274, and the addition output of the adder 275 is as follows.
The signal is supplied to the changeover switch 276.

The delayed output of the delay circuit 270 is sent to the subtracter 273 and BPF2.
The signal is supplied to a delay circuit 277 having the same delay delay as 74, and is also supplied to an adder 271 via a one-day delay circuit 278. The delayed output of delay circuit 277 is supplied to adder 275 and changeover switch 276. The changeover switch 276 is appropriately switched depending on the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).

With this configuration, a two- and three-line correlation comb filter is configured, and the subtracted output of the subtracter 273 is transmitted to the one-day delay circuit 2.
With respect to the delayed output of 70 (assumed to be Y+C), the chroma signal (-20) has an opposite phase and twice the level. After unnecessary components are removed from this chroma signal by the BPF 274, the delay level is adjusted by the delay circuit 277 and the delay output (
Y+C) is added in an adder 275, and a digitized video signal (b) having a chroma signal inverted with respect to the delayed output (a>) of a delay circuit 277 is obtained as an addition output.In special playback such as stay and slow, Changeover switch 27
Color framing can be maintained by switching the chroma inversion control signal from the system controller 18 shown in FIG. 1(8).

In FIG. 1 (F3), the output of the chroma inversion circuit 25 is supplied to the video processing circuit 38. Video processing circuit 38
In this case, character insertion, MCA code suppression, squelch, etc. are performed. The digitized video signal that has passed through the video processing circuit 38 is converted into a 4fsc signal that is generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal.
is written into the buffer memory 39 by the clock. Reading from the buffer memory 39 is performed using a 4fsc reference clock generated by the reference signal generator 22. In this way, by reading data from the buffer memory 39 using a stable reference clock that is unrelated to the reproduced signal, jitter in the reproduced signal can be absorbed, eliminating the need for so-called tangential servo or color correction circuits. Become. The digitized video signal read from the buffer memory 39 is converted into an analog signal by the D/A converter 40 and supplied to the output terminal 42 via the LPF 41 .

The system controller 18 has the following main functions. That is, 1. Various servo systems are controlled in response to commands from operating units such as panel switches and remote controls, and state signals from the servo system, to cause the player to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generate signals for compositing frame numbers, chapter numbers, etc. onto the screen.

4. Synchronize the internal counter with the horizontal synchronization signal and vertical synchronization signal, and decode the output of the counter to generate various timing signals.

5. Control the PLL loop for clock generation. A specific configuration for realizing the fourth function among the above-mentioned main functions will be described below.

In Figure 31, the horizontal synchronizing signal (n) is converted to data (D).
input and clock signal of 4 fsc (CK
) A D-type flip 70 tube 180 is provided as an input, and the Q output of this flip-flop 180 is NAND.
Gate 181B will be a one-man force. NAND gate 181
B receives the horizontal synchronizing signal supplied via the inverter 181A, and its output is sent to the 1H counter 183.
This is the load (L) input. The gate circuit 182A is 1
The output of the H counter 183 is decoded to generate the HS gate signal in a predetermined period and inputted to the HV separation circuit 145d in FIG.
A clock HCK with a frequency of H is generated. The HS gate signal is used in the HV separation circuit 145d to detect the fall of the horizontal synchronization signal excluding the equalization pulse and to separate the horizontal signals. In the initial state, the HS gate signal is always at a high level, loads the 1H counter 183 at the falling edge of the synchronizing signal, and thereafter remains at the high level only for a predetermined period so that the falling edge of the horizontal synchronizing signal is detected in 1H cycles.

In the initial state or for some reason, if the 1H counter 183 is loaded due to the falling edge of the equalization pulse and a 1/2H shift occurs, the 1H counter 183 will not be loaded after the vertical blanking period, so the system This state is detected within the controller 18 and the HS gate signal is kept at a high level again. Note that the HV separation circuit 145d generates a pulse of a predetermined width based on the fall of the horizontal synchronizing signal, and outputs this as the horizontal synchronizing signal. The clock HCK is a signal having a duty ratio of 50%, starting from the falling edge of the synchronization signal, and being at a high level in the first half and a low level in the second half. The gate circuit 182A further generates various timing signals for one day and supplies them to each circuit.

The positive polarity vertical synchronization signal (VS) becomes each clock input of D-type flip-flops 184 and 185.

The D-type flip-flop 184 receives the S gate signal outputted from the gate circuit 182B as a data (D) input, and when the vertical synchronization signal rises while the signal is at a high level, its Q output goes to a high level. The d output goes to low level and maintains that state until the reset signal goes to low level, and when the reset signal goes to low level, the Q and Q outputs are inverted.

The D-type flip-flop 185 receives the clock HCK output from the gate circuit 182A as a data input, and is used to determine whether the vertical synchronization signal is from field 1 or field 2.
In field 2, the rising edge of the vertical synchronizing signal arrives when the clock HCK is at a low level, so the Q output goes to a low level, and the 0 output goes to a high level.In field 2, the rising edge of the vertical synchronizing signal arrives when the clock HCK is at a high level, so the Q The output becomes high level and the O output becomes low level. The D-type flip-flop 186 uses the Q output of the flip-flop 184 as a data input, the clock HCK as a clock input, and the Q output of the flip-flop 185 as a clear input. When the level is reached, the Q output becomes high level at the rising edge of clock HCK, and in field 1, the Q output remains low level.

The Q and Q outputs of the D-type flip-flop 184 are J.

K input, the clock HCK is the inverted clock input, and the 0 output of the flip-flop 185 is the clear input.
Flip 70 knob 187 is D when field 1
When the Q output of the type flip-flop 184 becomes high level, the Q output becomes high level at the fall of the clock HCK.
During field 2, the Q output remains at a low level.

A NOR gate 188 that makes each Q output of the D type flip-flop 186 and the J- flip-flop 187 two-man power.
The next stage 1 frame counter 189
is loaded and the D-type flip-flop 184 is reset. Here, the reason why a load pulse is generated using a separate flip-flop for each field is to send a sufficiently wide load pulse to the one frame counter 189 in any field. 1 frame counter 189 counts clock HCK 52
It is a quinary counter and is loaded with the clock HCK when the output of the NOR gate 188 is at a low level.
The output of the D-type flip-flop 185 is controlled so as to increase the number by the same amount.

The gate circuit 182B decodes the output of the one frame counter 189 and generates the above-mentioned VS gate signal in a predetermined period, and also generates a timing signal of H units within one frame and supplies it to each circuit.

Next, the fifth of the above-mentioned five functions of the system controller 18, ie, the function of controlling the clock generation PLL loop, will be explained based on the flowchart of FIG. 32. As mentioned above, this PLL has two phase comparators: one for locking to the reference horizontal synchronizing signal or the reproduced horizontal synchronizing signal, and the other for locking to the color burst signal. The configuration is such that three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal at the input section of the comparator and by switching the phase comparator itself. In FIG. 32, in an initial state such as immediately after the power is turned on or when the spindle motor is forcibly accelerated, the reference signal generator 22 (FIG. 1(B)), which is the reference for the spindle servo,
P to lock to the reference horizontal synchronization signal obtained in
The LL loop operates (step 1), it is determined that it is locked to the reference horizontal synchronization signal (step 2), and when the horizontal synchronization signal can be obtained from the reproduced video signal, the loop is switched to the reproduction horizontal synchronization signal (step 3). At this time, if it is determined that it is not possible to do so, step 4).
Return to step 1 and loop back to the reference horizontal synchronization signal. If it is determined in step 4 that it is locked to the playback horizontal synchronization signal, the presence or absence of a color burst signal is detected in step 5), and if there is no color burst signal, the process returns to step 4 and the lock is maintained to the playback horizontal synchronization signal. . This state occurs during the vertical blanking period for both black and white discs and color discs. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). Here, if it is determined that the color burst signal cannot be locked, the process returns to the loop of the reproduced horizontal synchronizing signal in step 3 (step 7), but if it can be locked, the color burst loop state is maintained. However, at the same time, the synchronization with the playback horizontal synchronization signal must be monitored (Step 8). If either the lock with the color burst signal or the lock with the playback horizontal synchronization signal is lost, it is assumed that the lock is lost and the playback horizontal synchronization signal is looped. Return to (step 3). At this time, if the loop of the reproduced horizontal synchronizing signal fails to lock onto the reproduced horizontal synchronizing signal (step 4), the loop is further returned to the loop of the reference horizontal synchronizing signal (step 1).

Note that the determination of No in steps 4 and 7 indicates that the lock cannot be locked within the predetermined period when passing for the first time.
Passing the pass for the second time or later indicates that it is not locked.

This system has been explained above while showing the specific configuration of each circuit, but the point of this system is that all signal processing is performed digitally between the A/D converter 4 and the D/A converter 40. It has great characteristics. In this way, by digitizing the signal, it is possible to make it multi-functional, such as converting the monochrome dropout correction signal to color, chroma inversion, increasing the accuracy of Y-C separation by introducing frame memory, or increasing the accuracy of Y-C separation by introducing frame memory. Still image playback becomes easier.

In FIG. 1B, the circuits are arranged in the order of the adder 12, the dropout correction circuit 19, the chroma inversion circuit 25, the video processing circuit 38, and the buffer memory 39, but the arrangement is not limited to this arrangement. For example, as shown in FIGS. 33 (Δ) and (B), the order of "dropout correction circuit 19 + chroma inversion circuit 25", "video processing circuit 38" and "buffer memory 39" can be changed. It is. However, since the writing and reading of the three buffer memories is asynchronous, "buffer memory 39"
If there are two other signals after the one shown in FIG. 33 (B), it is necessary to resynchronize or delay the control signals and timing signals for the other two signals. In addition, “Video processing circuit 3
8" is followed by "dropout correction circuit 19 + chroma inversion circuit 25" (in the case of FIG. 33(A)),
When a character is inserted by the video processing circuit 38, a control signal is required to inhibit the dropout correction circuit 19 from performing dropout correction in the character portion.

Furthermore, as shown in FIG. 34, R, G, and B separation can also be performed digitally, and the RGB separation circuit
3 is converted into an analog signal by a D/A converter 44 and sent to each analog output terminal 4 via an LPF 45.
By supplying signals to 6R, 46G, and 46B, if you connect these terminals to a monitor TV (television) with RGB input, there is no need to use the RGB separation circuit in the TV, which improves the image quality. This will lead to improvements.

Furthermore, when using a digital TV that can input RGB as it is digitized, the digital signals separated by the RGB separation circuit 43 are directly input to each digital output terminal 47R, 47G, without going through a D/A converter. 47B.

In this RGB separation, in this system, the clock of the A/D converter 4 is set to 4Nfsc (N is an integer of 2 or more), and the 4fsc clock is locked to the color burst signal of the video signal, so the RGB separation is performed. (m) can be easily performed. The case of demodulating using R-Y and B-Y signals will be explained below.1. Demodulation can be similarly performed using the Q signal.

In the NTSC system, the phase of the color signal is as shown in FIG. 35, which is quadrature two-phase modulated and frequency multiplexed with the luminance signal. The relationship between the R, G, and B signals and the luminance signal Y is shown in the following equation.

Y-0,3OR+ 0.59 G+ 0.118...
...(1) Also, the color signal C in the video signal is expressed by the following equation.

R−Y B−Y C,= −□ COSωct +−5inωCt1.1
42.03 ・・・・・・(2) = I cos(ωCt+33@) + Q 5in(ωct+33°) ・・−−−(3
') where ωC is the angular frequency of the color carrier and ωC=
2πx 3.58 M)-1z.

When the phase of the 4fsc sampling frequency is locked to the color burst signal at O'', Figure 35 and (2) are obtained.
From the formula, each sample point is ±(R
-Y)/1.14, ±(BR)/2.03. Also, from equations (1) and (2), R, G, and B signals are obtained. Furthermore, I.

To obtain the Q signal, ±33° relative to the color burst signal.
Alternatively, the phase may be locked at ±57°.

From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst signal.

In the above embodiment, the case where the system is applied to an NTSC video disc player has been described, but this system is applicable to VTR playback side signal processing, PAL, SEC
It can also be applied to AM video disc players and the like.

As explained above, according to the present invention, when synchronization is stable, the first reference level for separating control signals is set based on the pedestal level, and the first reference level is set based on the pedestal level and the minimum value level. The second reference level is set to separate the synchronization signal based on the synchronization, and when the synchronization is unstable, the first and second reference levels are set based only on the minimum level, so when the synchronization is unstable, the pedestal level Since the reference level can be set even if the synchronization cannot be detected, the control signal and synchronization signal can be separated and extracted stably and reliably not only when the synchronization is stable but also when the synchronization is unstable.

[Brief explanation of drawings]

FIGS. 1(A) and (B) are block diagrams showing an embodiment of a video signal reproducing device according to the present invention, and FIG. 2 is a block diagram showing a specific configuration of the f-digital BPF in FIG. 1(A). , FIG. 3 is a block diagram showing an example of the configuration of the video LPF in FIG. 1(B), FIGS. 4(A) to (C) are spectrum diagrams of each part (Δ) to (C) in FIG. 3, Figure 5 is the third
6 to 8 are block diagrams showing specific configurations of the FIR filter, downsampling circuit, and IIR filter in FIG. 3, and FIG. 9 shows other configurations of the video LPF. 10 is a block diagram showing another configuration of the bit reduction process in FIG. 1(B), and FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit in FIG. 1(B). , FIG. 12 is an operation waveform diagram of each part in FIG. 11, and FIG. 13 is a block diagram showing the specific configuration of the falling detection circuit, rising detection circuit, timing signal generation circuit, and sample period signal generation circuit in FIG. 11. , FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit, FIG. 15 is an operation waveform diagram of each part in FIG. 14, and FIG. 16 is a diagram of the falling detection circuit and timing signal generation circuit in FIG. 14. FIG. 17 is a block diagram showing a specific configuration of the dropout correction circuit in FIG. 1(B), FIG. 18 is a waveform diagram for explaining the circuit operation of FIG. 17, Figure 19 is a waveform diagram for explaining the circuit operation of the dropout detection circuit in Figure 1 (A), and Figure 20 is the relationship between the video signal and the reference level in the signal separation circuit in Figure 1 (B). Waveform diagram showing 2nd
FIG. 1 is a block diagram showing the specific configuration of the signal separation circuit, FIG. 22 is a waveform diagram for explaining the operation of the signal detection circuit in FIG. 21, and FIG. 23 is a block diagram showing the specific configuration of the signal detection circuit. 24 is a diagram showing an example of the time table stored in the ROM in FIG. 23, FIG. 25 is a block diagram showing a specific configuration of the minimum value detection circuit in FIG. 21, and FIG. Block diagram showing the specific configuration of the clock generation circuit in FIG. 1 (8), No. 27
The figure is a waveform diagram of each part in FIG. 26, FIG. 28 is a block diagram showing the specific configuration of the phase comparator in FIG. 26, and FIG.
The figure is a waveform diagram for explaining the circuit operation of Figure 28.
0 is a block diagram showing a specific configuration of the chroma inversion circuit in FIG. 1(B), and FIG. 31 is a block diagram showing the configuration of part of the hardware for performing the predetermined functions of the system controller in FIG. 1(B). The block diagram shown in FIG. 32 is a flowchart of predetermined functions of the controller, and FIG. 33 (
A). (B) is a block diagram showing a modified example of this system, No. 34
The figure is a block diagram showing another modification, and FIG. 35 is a block diagram showing another modification.
FIG. 4 is a phase characteristic diagram of a color signal used to explain the principle of RGB separation, and FIG. 36 is a waveform diagram of a signal at each sample point. Explanation of symbols of main parts 2...Analog LPF 4...A/
D converter 6... Digital BPF 7... FM detection circuit 10... Video LPF 13... Pedestal level detection circuit 14
... Signal separation circuit 17 ... Dropout detection circuit 18 ...
... System controller 19 ... Dropout correction circuit 21 ... Clock generation circuit 22 ... Reference signal generator 24 ... Spindle motor 25 ... ...Chroma inversion circuit 38...Three video processing circuits...Buffer memory 40...D/A converter

Claims (1)

[Claims] A signal separation circuit that separates and extracts a control signal and a synchronization signal included in a video signal, the circuit comprising: a pedestal level detection circuit that detects a pedestal level of the video signal; and a pedestal level detection circuit that detects a minimum level of the video signal within a predetermined period. A first reference level is set based on the detection levels of the minimum value detection circuit and the pedestal level detection circuit, and a second reference level is set based on the detection levels of the pedestal level detection circuit and the minimum value detection circuit. a first reference level setting circuit that sets the first reference level and a second reference level that sets the first and second reference levels based only on the detection level of the minimum value detection circuit;
When the synchronization is stable, the first and second reference level setting circuits set the first and second reference levels, and when the synchronization is unstable, the second reference level setting circuit sets the first and second reference levels.
and a selection means for selecting a second reference level, and the control signal and the synchronization signal are separated and extracted based on the first and second reference levels selected by the selection means. Signal separation circuit.