JPS62140573A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To obtain a video output even at a non-steady-state at CLV scan by applying digital pedestal clamp to a data being an input to a synchronizing separator circuit, reducing bits and applying video processing based on the data subject to bit reduction thereby simplifying the circuit constitution. CONSTITUTION:The number of bits of a signal separation system is set to the number of bits n1 having a wide dynamic range so as to be sufficient even when the pedestal level is changed remarkably at a non-steady-state. The data is fed to a signal separation circuit 14 via an LPF 16. On the other hand, as to a video processing system, the dynamic range of the number of bits n2 is set smaller than the number of bits n1. Thus, the digital FM detection output is separated into 2 systems n1, n2 in such a way, then the circuit is designed by having only to take the steady-state of the circuit after the video LPF 10 only into account, the circuit constitution is simplified and a synchronizing signal is detected surely even at a non-steady-state such as rising of a spindle motor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal reproducing device, and more particularly to a device for reproducing a video signal that has been FM modulated and recorded on a recording medium.

1 and 1 In a video disc player that plays back a recording medium, such as a video disc, in which a video signal is recorded with FM'ff modulation, an FM video signal read from the disc is an FM video signal. Conventionally, signal processing (denoted as ) has generally been performed in an analog manner.

However, when considering the integration of circuits into ICs (integrated circuits), it is extremely advantageous to perform signal processing digitally rather than analogously, and multifunctionality can be easily realized in the signal processing process. Furthermore, higher image quality can also be achieved.

Incidentally, when performing digital signal processing, a smaller number of quantization bits per word is advantageous in designing a circuit. However, in a disc player, although the DC component of the video signal is almost constant in a steady state, in an unsteady state such as when the rotation of the spindle motor starts, or during a search or scan during playback of a CLV (constant linear velocity) disc, the The DC component of the signal fluctuates significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle motor circuit that drives and controls the spindle motor will not be able to lock, and the clock generation circuit that generates the clock signal will also be unable to synchronize, resulting in a permanent steady state. Therefore, in order to be able to detect a synchronization signal even in an unsteady state, the number of bits must be set based on the unsteady state.

1 and 5 MJ.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a video signal reproducing device that can simplify the circuit configuration when digitally processing an FM video signal.

The video signal reproducing apparatus according to the present invention is configured to digitally pedestally clamp the data that is the input of the synchronization separation circuit, reduce bits, and perform video processing based on the bit-reduced data.

less than one margin Length-”L-Yutaka Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1(A), an FM video signal read from a recording medium such as a video disk is passed through an input terminal 1, an analog LPF (low pass filter) 2, and an A/D converter.
(analog/digital) converter 4. The LPF 2 removes aliasing distortion in A/D conversion, but the LPF 2 removes aliasing distortion in A/D conversion.
If there are very few components equal to or higher than ωS (sampling frequency at the time of Δ/D conversion), the LPF 2 may be omitted.

The digitized FM video signal output from the A/D converter 4 is passed through a digital BPF (band pass filter) 6.
supplied to This digital BPF 6 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM audio signal, and supplies the extracted components to the FM detection circuit 7 at the next stage.

As shown in FIG. 2, the digital BPF 6 includes, for example, delay circuits 60+ to 60n connected in series to delay one clock, and the input signal of the delay circuit 60+ and each output of the delay circuits 60+ to 6°n. Multiply the signal by the coefficient k
It is possible to use an FIR filter (acyclic digital filter) consisting of multipliers 61o to 61n that multiply by o''kn, an adder 62 that adds the outputs of each multiplication, and a latch circuit 63 that latches the added output. , multiplier 610~
By appropriately selecting □-kn for each multiplication coefficient of 61n, desired field of view characteristics and group delay characteristics can be obtained. Therefore, when group delay distortion occurs due to the analog LPF 2, by making the group delay characteristics of the digital BPF 6 inverse to those of the analog LPF 2, the digital FM
A video signal can be supplied. Also, analog LP
If the group delay distortion of F2 is small and can be ignored, or if analog LPF2 is deleted, use digital BPF6.
By using a phase linear type filter in the same way, a signal without group delay distortion can be obtained. In Fig. 2, the coefficients Ko-Kn of the digital BPF 6 are symmetrical about n (
If Ko =KnK+ =Knze...-), it becomes an ideal phase linear filter.

The FM detection circuit 7, for example, as shown in FIG. 1(A),
A Hilbert transformer 70 performs Hilbert transform on a digitized FM video signal, a delay circuit 71 delays the digitized FM video signal by n sample periods, and each output signal of the Hilbert transformer 70 and delay circuit 71 is squared. A sum-of-squares circuit 72 for adding, a delay circuit 73 for delaying the output signal of the delay circuit 71 by one sample period, a multiplier 74 for multiplying each output signal of the delay circuits 71 and 73, and the output of this multiplier 74. A divider 75 divides the signal by the output signal of the square sum circuit 72. The Hilbert transformer 70 is composed of a transversal filter and the like.

Furthermore, the delay time of the delay circuit 71 is determined by the Hilbert transformer 70.
This corresponds to the delay time of The FM detection circuit 7 having such a configuration is disclosed in Japanese Patent Application No. 59-2624 by the applicant of the present application.
Proposed in No. 81.

In FIG. 1B, in the video LPFIO to which the detection output of the FM detection circuit 7 is supplied, only the baseband component of the video signal is extracted from the detection output. Video L
The cutoff frequency of P'F 10 is set to, for example, 4.2 MH2 in the case of the NTSC system. FIG. 3 shows the configuration of an example of the video LPF 10.
PFIO operates at a clock frequency of 4Nfsc (N is an integer of 2 or more) and removes the carrier wave component contained in the FM-detected digital video signal and extracts only the baseband component. Filter (FIR filter) 100 and this FIR filter 1
a downsampling circuit 101 that downsamples the output of 00 to a clock frequency of 4fsc;
and a subsequent cyclic digital filter (IIR filter) 102 which operates at a clock frequency of 1 and compensates the phase characteristics of the digitized video signal.

In Fig. 4 (A) to (C), each part (A) in Fig. 3 is shown.
-(C) spectra are shown.

The FM detection output (A) includes not only the baseband video signal but also its second harmonic component, which is passed through the FIR filter 10.
By passing through 0, only the baseband video signal (B) is derived at the output end. This baseband video signal (B) is transmitted to the downsampling circuit 101
The clock frequency of 4Nfsc is downsampled to the clock frequency of 4fsc. The spectrum after downsampling is the same as that in Figure (B).

In this way, by lowering the sampling frequency, it becomes possible to save time and reduce the size of the hard scene.

Note that since the band of the digitized video signal is narrowed to approximately 4.2 MHz by passing through the FIR filter 100, there is no problem even if the sampling frequency is lowered. After downsampling, the baseband video signal (B) is compensated for its phase characteristics by an IIR filter 102. The spectrum (C) after phase compensation is also the same as that in Figure (8).

In the case of video disks, etc., the signal processing system for the playback signal has traditionally been analog, so the phase distortion of the video LPF is calculated when recording information, assuming that the phase will rotate in a video LPF designed in an analog manner. Information is recorded by distorting it in the opposite direction with reverse compensation. Therefore, when playing back a video disc with such a recording format and digitally processing the playback signal, it is necessary to further compensate for the inverse compensation valve for phase distortion during recording, and compensation for this phase characteristic is necessary. is the IIR filter 102
It is done in In FIG. 5, IIR filter 1
02 phase characteristics are shown.

6 to 8 show examples of specific configurations of the FIR filter 100, the downsampling circuit 101, and the IIR filter 102. First, in Figure 6,
The FIR filter 100 includes delay circuits 103+ to 103n connected in series to each other for delaying by one clock;
Input signal of delay circuit 1031 and delay circuits 1031 to 1
Multipliers 104o to 104n that multiply each output signal of 03n by a multiplication coefficient □-kn, an adder 105 that adds the outputs of each multiplication, and a latch circuit 106 consisting of a D-type flip-flop or the like that latches the added output. The clock frequency of the delay circuits 1031 to 103n and the latch circuit 106 is set to 4Nfsc. As shown in FIG. 7, the downsampling circuit 101 is constituted by a latch circuit 107 consisting of a D-type flip-flop or the like, and its clock frequency is 4fsc1. : Set.

As a result, the data input to the latch circuit 107 is N
- Output every other item.

Moreover, as shown in FIG. 8, the IIR filter 102
A multiplier 108o that multiplies an input signal by a multiplication coefficient ko, 10 adders that take this multiplication output as one addition input, a latch circuit 110 consisting of a D-type flip-flop, etc. that latches the addition output, and an adder 109. Delay circuits 1111 to 111n connected in series to each other sequentially delay the addition output by one clock, and these delay circuits 1111 to 1.
Multiplier 1 that multiplies each output of 11n by a multiplication coefficient kl−kn
081 to 108n, and the clock frequency of the latch circuit 110 and delay circuits 1111 to 111n is 4f.
It is set to sc. In this circuit configuration, by appropriately setting the multiplication coefficients k(, -kn) of the multipliers 1080 to 108n, phase characteristics as shown in FIG. 5 can be obtained.

In the video LPF 10 described above, the phase straight line FI
By using the R filter 100 at the front stage, all phase compensation can be determined only by the IIR filter 102 at the rear stage, and the amplitude characteristics can be adjusted without changing the phase characteristics.

Note that downsampling is performed before the IIR filter 102, but this is because the IIR filter 102
This is due to the fact that all operations must be completed within a clock period. If downsampling is to be performed after the FIR filter 102, Vibration processing is not possible for the above-mentioned reasons, and the number of operations must be reduced or a high-speed element must be used, but even this has its limitations. On the other hand,
If downsampling is performed before the IIR filter 102, the clock period will naturally become longer, and if the number of operations is increased accordingly, more accurate characteristics will be obtained and stability will also increase.

In the video LPF 10 configured as described above, the front stage F
The IR filter 100 is operated with a 4Nfsc clock, and its output is processed by a downsampling circuit 101 at 4fsc.
However, as shown in FIG. 9, downsampling is performed before the arithmetic circuit in the FIR filter 100', and the clock after the arithmetic circuit is downsampled at 4fs.
It is also possible to configure it to operate with the clock of c. At this time, the downsampling circuit 101 is not necessary.

That is, in FIG. 9, the FIR filter 100' includes delay circuits 1121 to 112n connected in series that delay one clock, and input signal and delay circuit 1.
latch circuits 1130 to 113n consisting of D-type flip-flops that latch each output signal of 121 to 112n;
Multipliers 1140 to 114n that multiply each latch output of these latch circuits 1130 to 113n by multiplication coefficients ko to kn.
, an adder 115 that adds these multiplication outputs, and a latch circuit 116 consisting of a D-type flip-flop that latches this addition output, and delay circuits 112t to 112n.
The operation of the latch circuits 1130 to 113n in the next stage is performed with the clock of 4Nfsc, and the operation of the final stage arithmetic circuits (multipliers 1140 to 114n,
The operation of the adder 115 and latch circuit 116) is 4 fsc.
The configuration is such that the operation is performed using the same clock.

In the FIR filter 100'' having such a configuration, the calculation is 4f.
Since it is performed using the sc clock, unnecessary calculations are omitted,
In addition, since the clock cycle becomes longer, the number of calculations can be increased, and relatively, the FIR filter 10 having the above-mentioned configuration
This means that the circuit scale can be reduced more than 0.

Note that in order for the FXR filter to have a phase linear characteristic in FIGS. 6 and 9, the coefficient Ko−Kn must be symmetrical about the center (Ko =)(n,
K+ = Kn-+, --).

Referring again to FIG. 1B, the digitized video signal that has passed through the video LPF 10 passes through the de-emphasis circuit 11 and is then passed through the adder 12, pedestal level detection circuit 13, and signal separation circuit 14, which constitute pedestal clamp means. supplied to

By the way, when performing digital signal processing, it is clear that it is advantageous in designing a circuit to have a smaller number of m-bits per word n (bits/word).

However, when considering the FM detection output, the output level is constant in the steady state of the disc player, but it is unsteady due to the rise of rotation of the spindle motor 24, search and scan during CLV (constant linear velocity) disc playback, etc. In this state, the DC component of the video signal changes significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle servo circuit 23 cannot be locked, and the clock generation circuit 21 cannot be synchronized, so the steady state cannot be achieved forever, so the synchronization signal can be detected even in the unsteady state. You need to be able to do it. For this purpose, the number of bits n must be set based on the unsteady state.

Therefore, at least the number n of bits from the input of the signal separation circuit 14 to the output of the de-emphasis circuit 11 is set to a number of bits with a wide dynamic range that is sufficient even if the pedestal level changes significantly based on the unsteady state. n
Set to 1 (bit/word). As a result, not only in a steady state but also in an unsteady state, the de-emphasis circuit 11 can be removed from the signal separation circuit 14 from the FM detection output.
This means that the synchronization signal can be reliably detected.

The pedestal level detection circuit 13 detects the pedestal level V
PD is detected and the pedestal level Vp is determined from the reference voltage VRF.
The video signal is digitally pedestally clamped by generating an output (VRF - VP D ) obtained by subtracting o and adding it to the digitized video signal in an adder 12 to cancel the variation in the pedestal level. The pedestal-clamped n + (bit/word) data is output from the adder 12 as n 2 (bit/word).
bits are reduced to the data (nz < n+
). nl is determined by the dynamic range and resolution required for a video signal in a steady state. This bit reduction facilitates the circuit design of the adder 2 and subsequent parts.

Furthermore, by performing pedestal clamping, the signal level of the digitized video signal will be within the dynamic range of n 2 (bit/word) not only in the steady state but also in the unsteady state, so when scanning the CLV. This means that images can be viewed even in unsteady conditions such as.

In the above configuration, regarding the dynamic range of each circuit constituting the digital signal processing system, the dynamic range up to the input of the signal separation circuit 14 is n + (bit/WOrd), and regarding video processing, the pedestal is digitally After clamping, n 2 (bit/
As shown in Figure 10, the output of the digital FM detection circuit 7 was separated into two systems: a video processing system and a signal separation system, and It is also possible to make the number of bits n different.

That is, in FIG. 10, the pitch number n of the signal separation system is
is the number of bits n + with a wide dynamic range that is sufficient even if the pedestal level changes significantly in an unsteady state.
(bit/word). This n + (
The data (bit/word) is supplied to the signal separation circuit 14 via the filter PFl 6. The LPF1 6 may be any filter having characteristics that allow the synchronization signal to be detected from its output, and therefore the configuration can be simplified by using simplified filter coefficients. On the other hand, regarding the video processing system, the number of bits n 2 (bit
/word) dynamic range. n
l is determined by the dynamic range and resolution required for a video signal in a steady state.

In this way, the digital FM detection output is nl+n 2
By separating into two systems (bit/word),
Since the circuit after the video LPF 10 can be designed by considering only the steady state case, the circuit configuration can be simplified, and the synchronization signal can be reliably detected even in an unsteady state such as when the spindle motor 24 starts up. Become.

In addition, in such a circuit configuration, in an unsteady state, there may be cases where the image cannot be seen due to changes in the pedestal level, but this is only possible if the image can be seen in the steady state, and the synchronization signal can be reliably detected in the unsteady state. It is based on ideas. However, in the CLV scan, since the clock generation circuit 21 is synchronized to some extent, changes in the pedestal level are often small, and in this case, the image can also be viewed.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit 13. In this figure, LPFl
The digitized video signal (a) from which the color burst has been removed in step 17 is supplied to a pedestal sampling circuit 118 and a sync separation circuit 119, respectively. Synchronous separation circuit 1
19, the synchronization signal (b) included in the digitized video signal (a) is separated and extracted, and the corresponding direction! I11 signal (b)
are the rising detection circuit 121 and the falling detection circuit 120.
are supplied respectively. The fall detection circuit 120 detects the fall of the same signal (b) during the generation period of the first gate signal (C) output from the timing signal generation circuit 122.
The rising edge detection circuit 121 detects the rising edge of the synchronizing signal (1) during the generation period of the second gate signal (d).

The timing signal generation circuit 122 generates a first gate signal (C) based on a clock signal during a period in which a dropout detection signal (Q) from a dropout detection circuit 17 (see FIG. 1(A)), which will be described later, is not generated. The dropout detection signal (C
A second gate signal (d> is generated during the non-generation period of 1).

The sample period signal generation circuit 123 generates a sample period signal (e) of a certain period in response to the detection output of the rising edge detection circuit 121, and supplies it to the pulse generation control circuit 124.

The pulse generation control circuit 124 is, for example, a three-man power AN[
) The detection outputs of the gate 125 and the rise detection circuit 121 are set (S) input, the output of the AND gate 125 is reset (R) input, the clock signal is the clock (GK) input, and its Q output is input to one of the AND gates 125. It consists of a human-powered SR flip-flop 126, and supplies the output pulse of the AND gate 125 to the pedestal sampling circuit 118 as a sampling pulse (f). The pedestal sampling circuit 118 is composed of a D-type flip-flop or the like, and latches the pedestal level Vpo of the digitized video signal in response to the sampling pulse (f). The sampled pedestal level path 127 is subtracted from the reference level VRF and a plurality of H
It is averaged between them, and the detected output is at the (VR t: -Vpo) level.

FIG. 12 shows the operating waveforms of the circuit in FIG. 11.
The corresponding waveforms are shown.

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the fall of the horizontal synchronization signal included in the synchronization signal (b) is detected by the first gate signal (C), and the horizontal synchronization signal is detected using this fall as a reference. After a time corresponding to the width, the second gate signal (d) is generated to detect the rise of the horizontal synchronization signal C b ), and the sample period signal (e) is generated based on this rise, so horizontal synchronization is reliably achieved. It is possible to capture the signal and sample the pedestal level at the bank porch during the horizontal blanking period. Further, since the color burst is removed from the digital video signal <a) by the LPF I 1 7, it is possible to generate a sample period signal (e) having a wide period including the portion where the color burst was present.

The sampling pulse (f) is the sampling period signal (
It is generated during the generation period of e) and the non-occurrence period of the dropout detection signal (q), and has a pulse width equivalent to one clock of the clock signal. Therefore, if there is a dropout shorter than the sample period, then if there is a dropout shorter than the sample period, then
As shown by the two-dot chain line in f), one clock worth of sampling can be reliably performed in 1H without the influence of dropout. Also, 1st. Second gate signal (C).

(d) is generated excluding the part where dropout occurs, so even if a false horizontal synchronization signal is generated due to dropout, a sample period signal may be generated incorrectly based on this horizontal synchronization signal. There isn't.

Output of pedestal level detection circuit 13 (VRF-Vpo
) is added to the video signal by the Kel adder 12 as shown in FIG. 1(B), thereby performing pedestal clamping. Further, the pedestal level VPD is also supplied to the signal separation circuit 14 in FIG. 1(B), and in this circuit 14, synchronization signals and control signals are separated using the pedestal level Vpo as a reference level.

Note that in the above configuration, the LPF 117 in the input section can be omitted, but if it is omitted, it is necessary to generate the sampling period signal in a period other than the color burst section. Furthermore, the configuration of the pulse generation control circuit 124 is not limited to the circuit configuration described above, and various configurations are possible, such as using a microprocessor, for example. Also,
The LPF 117 and the synchronization separation circuit 119 can be respectively replaced with an LPF 145a and a signal detection circuit 145C in FIG. 21, which will be described later, and these circuits may be used in common.

FIG. 13 shows the falling detection circuit 12 in FIG.
0, an example of a specific circuit configuration of a rising edge detection circuit 121, a timing signal generation circuit 122, and a sample period signal generation circuit 123 is shown. In this figure, the fall detection circuit 120 includes a D-type flip-flop 128 that receives the synchronizing signal (b) as data (D> input) and a clock signal as the clock input, and an inverter 129A that receives the synchronizing signal (b) as the input. The Q output of the flip-flop 128 is composed of the Q output of the flip-flop 128, the first gate signal (C) from the timing signal generation circuit 122, and a 3-man power NAND gate 129B that uses the output from the inverter 129Δ as the 3-man power. is the synchronization signal (b) delayed by one clock, and the NAND gate 129B
Then, when the synchronization signal (b) falls while the first gate signal (C) is at a high level, that is, the horizontal synchronization signal falls, all three signals become high level at the moment of the fall. A low level detection output is generated.

The timing signal generation circuit 122 includes the falling detection circuit 1
1H counter 130 which takes the detection output of No. 20 as a load input and a clock signal as a clock input;
A gate circuit 131 that generates second gate signals (c) and (d) is connected to a one-day counter 13.
0 counts the clock for 1H period in synchronization with the falling edge of the horizontal synchronization signal, and if the video signal is NTSC, the clock is 14.3MH2=4fsc=91Of+
−+ (f+ is the horizontal scanning frequency), which becomes a 910 progress counter. Also, the gate signals (c) and (d) are not generated during the period when dropout occurs.

Although not shown in the figure, if the 1H counter 130 is not loaded several times in succession, the first gate signal (C) is forced to a high level and the horizontal synchronizing signal is raised. Detect the drop. This is to prevent the 1H counter 130 from being loaded with a 1/2H shift due to the equalization pulse, which will no longer be loaded by the horizontal synchronizing signal, making it impossible to detect the pedestal level. .

The rising edge detection circuit 121 is the timing signal generation circuit 1
It consists of a D-type flip-flop 132 which takes the second gate signal (d) from 22 as the data (D> input and the synchronization signal (b>) as the clock input, and the second gate signal (d)
When the signal (b) rises, that is, the horizontal synchronizing signal rises while the signal (b) is at a high level, a high level detection output is generated from the Q output terminal. Sample period signal generation circuit 1
23 connects the detection output of the rising edge detection circuit 121 to a port (
L) Input and enable (EN) Consists of a manually operated 7-dot counter 133, which is loaded with '90' until just before the horizontal synchronizing signal rises, starts counting at the rising edge of the horizontal synchronizing signal, and counts from '96' to '96'. 127”
A sample period signal (e) is output with the period as a sample period. When the count exceeds '127' and becomes 0'', the D-type flip-flop 132 is cleared and the load input and enable input are set to low level, returning to the load state and stopping.

Note that the fall detection circuit 120 and the timing signal generation circuit 122 are similar to the HV separation circuit 1 in FIG. 21, which will be described later.
45d and a part of the timing signal generation section of the system controller 18 in FIG.
The D-type flip-flop 180, inverter 181A, and NAND gate 181B in FIG.
1 to the 1H counter 183 and gate circuit 182 in FIG.
They may be shared with A.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 13, in which parts equivalent to those in FIG. 11 are designated by the same symbols. In this figure, LPFl
The synchronization signal (b) separated and extracted by the synchronization separation circuit 119 from the digitized video signal (a) that has passed through the digital video signal (a) that has passed through the digital video signal (a) is supplied to the falling edge detection circuit 134. The fall detection circuit 134 detects the fall of the synchronization signal (b) during the generation period of the gate signal (C) output from the timing signal generation circuit 135, and supplies the detection output to the timing signal generation circuit 135.

The timing signal generation circuit 135 generates a gate signal (C) based on the clock signal during the non-generation period of the dropout detection signal (f), and also generates the gate signal (C) based on the clock signal during the period when the dropout detection signal (f) is not generated.
34 generates a sample period signal (d) at the front porch of the horizontal synchronizing signal 1H after the falling detection timing as a reference, and supplies it to the pulse generation control circuit 136.

The pulse generation control circuit 136 includes, for example, a three-man power AND gate 137 that receives the sample period signal (d) and the dropout detection signal (f) from the timing signal generation circuit 135, and a set signal from the timing signal generation circuit 135. Set (S) input, reset the output of AND gate 137 (R) input, clock signal to clock (GK)
It consists of an SR flip-flop O-tube 138 which serves as an input and whose Q output is the input of an AND gate 137.
The output pulse of gate 137 is the sampling pulse (e)
The signal is supplied to the pedestal sampling circuit 118 as a signal.

The subsequent operations are the same as those shown in FIG.

Figure 15 shows the operating waveforms of the circuit in Figure 14, and Figures (a) to (f) show the waveforms of each section (a) to (f) in Figure 14, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 14, the fall of the horizontal synchronizing signal is detected using the gate signal (C), and after generating a set signal using this fall as a reference and opening the AND gate 137, Since the sample period signal (d) is generated corresponding to the front porch after 1H,
The pedestal level can be detected even during the vertical blanking period. Further, after sampling the pedestal level, if the falling edge of the horizontal synchronizing signal cannot be detected while the gate signal (C) is being generated, the falling edge detection circuit 134 generates a pedestal enable signal to detect the sampled level. It is possible to notify the next stage circuit that the pedestal level is invalid, or to hold the previously detected pedestal level. For example, by inputting the pedestal enable signal to the arithmetic circuit 127,
The circuit 127 is caused to continue outputting the previously output (VRF-VF6).

The gate signal (C) and the sampling period signal (d) are generated except for the part where the dropout occurs, and the pulse generation control circuit 136 generates the sampling pulse (e) for one clock. without accidentally generating the sample period signal (d);
If the length of dropout during the sample period does not exceed the sample period, sampling for one clock every 1H must be performed reliably without the influence of dropout a, as shown by the two-dot chain line in FIG. 15(e). I can do it.

As for the example of diversion, the same aspect as in the case of the configuration shown in FIG. 11 can be considered.

FIG. 16 shows the falling detection circuit 13 in FIG.
4 and a specific circuit configuration of the timing signal generation circuit 135 are shown. In this figure, the fall detection circuit 134 is a JK flip-flop 1 which receives the synchronization signal (b) as an inverted clock input and receives the gate signal (C) as the J input.
39, when the synchronization signal (1)) falls while the gate signal (C) is at high level, that is, the horizontal synchronization signal falls, the Q output becomes high level, and thereafter the reset signal becomes low level. The Q output is held at a high level until the transition occurs. When the reset signal goes low, the Q output also goes low.

The timing signal generation circuit 135 includes a D-type flip-flop 140 which uses the Q output of the JK flip-flop 139 as a data (D) input and a clock signal as a clock input, and a D-type flip-flop 140 that uses the Q output of this flip-flop 140 as a D input and receives a clock signal. D-type flip-flop 141 with O-lock input
And load the ◇output of this flip-flop 141 (L
JK flip-flop 1 consists of a 1H counter 142 whose clock input is an input of
Immediately after the Q output of 39 becomes high level, an O-do pulse is generated for one clock from the D-type flip-flops 140 and 141 to load the 1H counter 142. 1H counter 142 that counts 1H period in synchronization with falling
If the video signal is NTSC, the clock is 14.3M.
H2=4fSC=910fH (f+ is horizontal scanning frequency)
Therefore, it becomes a 910-decimal counter.

In the gate circuit 143, the gate signal (C) is not generated during the period when dropout occurs. Further, the reset signal is generated as a pulse once every 1H with a sufficient interval from the gate signal (C) so that the pedestal enable signal is recognized by the next stage circuit.

Note that in the circuit shown in FIG. 16, the gate signal (C) is reduced to 1/2 due to the loading of the IH counter 142 by the equalization pulse.
Measures similar to those shown in FIG. 13 are taken to prevent H deviation.

Further, the circuit in FIG. 16 can be replaced or shared with the HV separation circuit 145d in FIG. 21 and the circuit in FIG. 31, as in the case of FIG. 13.

In each of the embodiments of the pedestal level detection circuit 13 described above, the video signal has been described as being digitized, but the application is not limited to digital video signals, and can be applied to analog video signals. It can be applied in the same way.

Next, the dropout correction circuit 1 in FIG. 1 (8)
9 will be explained. This dropout correction circuit 19
corrects the dropout of the digitized video signal output from the adder 12, but regarding the dropout of the vertical synchronization signal part, it is replaced with a correction signal set in advance to a level equal to the signal level of the vertical synchronization signal. By doing so, the dropout is corrected.

The configuration of this dropout correction circuit 19 is shown in FIG. In this figure, the digitized video signal is supplied to the first selector switch 190, and the output of the switch 190 is passed through the first delay circuit 191 to the second delay circuit 1.
92 and 3.58 MH2 BPF193.

Here, when the delay amount of the BPF 193 is set to d, the delay amount of the first delay circuit 191 is set to IH-d, and the delay amount of the second delay circuit 192 is set to d. The output of BPF 193 is sent to adder 195 via multiplier 194 with a coefficient of -2.
and is added to the output of the second delay circuit 192. The addition output of the adder 195 is sent to the second changeover switch 196.
The output of the switch 196 becomes the power of the first selector switch 190. Switching of the first changeover switch 190 is controlled by a dropout detection signal supplied from the dropout detection circuit 17 (see FIG. 1(A)).

address generation circuit 197, signal tit circuit 14
A field identification signal, a horizontal address, and a vertical address are generated based on the horizontal synchronization signal and vertical synchronization signal supplied from the vertical synchronization signal, and the signal level of the vertical synchronization signal known from the vertical synchronization level generation circuit 198 and the signal level of the vertical synchronization signal are generated based on these address information. A correction signal set to the same level is generated and acts as an input to the second changeover switch 196. In the switching signal generation circuit 199, a vertical synchronization period signal is generated during the generation period of the vertical synchronization signal based on the vertical address, and this vertical synchronization period signal becomes a switching signal for controlling the switching of the second changeover switch 196.

By the way, as shown in FIG. 18, the signal before correction (A>
If a dropout occurs in the vertical synchronizing pulse part of ) may cause a positional deviation of the vertical synchronizing pulse (in FIG. 18, a 1/2H positional deviation occurs between the O-marked parts).

If the vertical synchronizing pulse is misaligned in this way, there is a possibility that field errors will occur in subsequent video equipment. However, if dropout correction of vertical synchronization pulses is prohibited, synchronization loss may occur.

Therefore, as shown in FIG. 17, when a dropout occurs in the vertical synchronization pulse portion, the signal level is equal to that of the vertical synchronization signal output from the vertical synchronization level generation circuit 198 instead of the signal 1H before. The level correction signal is
By supplying the signal to the selector switch 190 and replacing it with a digitized video signal, dropout can be corrected without causing a positional shift of the vertical synchronizing pulse.

Note that in FIG. 17, dropout correction is performed using a signal from one day ago, but at this time, the phase of the chroma signal will become reversed if left unchanged. Therefore, the first
The circuit surrounded by the broken line in FIG. 7 inverts the phase of the chroma signal, thereby making it possible to colorize the dropout correction signal. Therefore, when the dropout correction is performed only on the luminance signal (monochrome), when the dropout correction is performed on the signal from two days ago (the red signal is in phase), the circuit shown in the broken line portion is excluded. The address generation circuit 197, vertical synchronization level generation circuit 198, and switching signal generation circuit 199 may be included in the system controller 18, and may be replaced with the 1H counter 183° gate circuit 182A, the 1 frame counter 189 gate circuit 182B, etc. in FIG. It's okay.

The dropout detection circuit 17 in FIG. 1<A) has a level comparator configuration, and as shown in FIG. It is detected that the signal level of the squared signal (B) of the envelope component of Δ) has become below a predetermined value, and a dropout detection signal (C) is output. According to this configuration, the dropout detection circuit can be configured by simply adding a level comparator to the FM detection circuit 7, so that dropout detection can be reliably performed with a simple circuit configuration, and all detection operations can be performed. Since this is done digitally, stable characteristics can be obtained.

Note that there is a possibility that the detection output is disturbed by ringing that occurs in the output of the sum-of-squares circuit 72 (the area surrounded by a dashed line in FIG. 19(B)) due to a sudden change in the envelope. A dropout detection signal (D>) is also output as a dropout section at n1 points before the signal level of the output signal (B) of 72 becomes below a predetermined value and at n2 points after the level becomes above a predetermined value. Therefore, subsequent corrections can be executed reliably.At this time, there is a possibility that ringing will occur due to the delay of the Hilbert transformer 70, so nl.

nl is set equal to or larger than the delay time of the delay circuit 71.

The signal separation circuit 14 shown in <8> of FIG. 1 separates and extracts control signals such as frame numbers and stop codes along with the color burst signal, horizontal synchronization signal, vertical synchronization signal, etc. contained in the digitized video signal. For this signal separation, as shown in FIG.
is set.

The configuration of this signal separation circuit 14 is shown in FIG.

In this figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum level of the digitized video signal within a predetermined period. The configuration of the minimum value detection circuit 20 will be explained in detail later. Based on each detection level of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the first. second reference level VT)
-II.

VTI-12 is set, and the reference level generation circuit 140 generates the first 1' level VTH+ by adding a certain value to the level based only on the detection level of the pedestal level detection circuit 13. Based on the detection levels of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the reference level generation circuit 141 generates an intermediate value between both levels as a second reference level VT)-12. The reference level generation circuits 142 and 143 generate the first. A second F4Q level Vv+-z, Vv+I2 is generated.

Each output of the reference level generation circuits 140 to 143 is supplied to a selector 144, and this selector 144 selects the reference level generation circuit 140 when the synchronization establishment determination signal is supplied from the system controller 18, that is, when the synchronization is stable. The first .141 generated. second reference level V
TI-11 and VTH2 are selected, and in other cases, that is, when the synchronization is unstable, the first. Second reference level VTI-11, Tl-1
Select 2. Note that in the system controller 18,
It is determined whether synchronization is established by comparing the reference synchronization pulse based on the internal clock and the extracted synchronization pulse. The first one selected by the selector 144.
The second reference level VTI-11°VTH2 is supplied to a signal detection circuit 145c, and this signal detection circuit 145c detects the digitized data that has passed through the t-P F 145a based on these reference levels VT)-11 and VTI-12. Control signal A and synchronization signal B are separated and extracted from the video signal.

That is, in the signal separation circuit 14 configured as described above, when the daily cycle is stable, the pedestal level and the first . Based on the second reference level VTH1, VTI-12, or at the start of rotation of the spindle motor 24 or C
When synchronization is unstable, such as during LV disk search or scanning, the pedestal detection position is not determined and its value is not determined, so the first. Second reference level) L, rVT) -11, VT H
The control signal A and the synchronization signal B are separated and extracted based on the reference signal A and the synchronization signal B. According to this, signal separation can be performed stably and reliably not only when synchronization is stable but also when synchronization is unstable. The separated synchronization signal B is sent to the HV separation circuit 1.
45d and 1 from the system controller 18.
- (The horizontal synchronizing signal is separated by detecting the fall when the S gate signal is at a high level. Also, the synchronizing signal B is integrated in the HV separation circuit 145d, and the vertical synchronizing signal is separated based on a predetermined reference level. The digitized video signal is separated from the fscBPF along with the LPF 145a.
145b, and a color burst signal containing a color signal component is output from the fscBPF 145b.

By the way, regarding the detection of the synchronization signal in the signal detection circuit 145C, as shown in FIG. 22, the digitized video signal is sampled at every predetermined clock (the X mark in the figure is the sample point), and the signal level of the synchronization signal is at the reference level. VT
The synchronization signal is detected at the point when the signal passes I-12.

The configuration of this synchronization signal detection circuit is shown in FIG.

In this figure, a reference level generation circuit 141 (or 143
) and the digitized video signal that has passed through the PF 145a, the subtracter 146 outputs the level difference between the signal level of the video signal and the reference level VTI-12 at each sample point. A sample point whose signal level is lower than the reference level VT)-12 is detected as a synchronization signal. The level difference signal calculated by the subtracter 146 is sent to a delay circuit 147 and a sign determination circuit 1.
48 and a storage device 149 such as a ROM (read only memory). The delay circuit 147 has a delay 1 equivalent to one clock, and delays the level difference signal from the subtracter 146h) to the sign determination circuit 148 and the storage device 149.
supply to. The sign determination circuit 148 detects that the output A of the delay circuit 147 is positive and the output B of the subtracter 146 is negative, that is, the level difference at the sample point a immediately before the output A of the delay circuit 147 exceeds the reference level VTH2, and It is determined that the output B of the subtracter 146 is already a level difference at the sample point immediately after exceeding the reference level VTH2, and a determination signal is supplied to the storage device 149.

For example, a time table as shown in FIG. 24 is stored in advance in the storage device 149, and the storage device 149 stores the outputs of the delay circuit 147 and the subtracter 146 when the determination signal is generated from the sign determination circuit 148, That is, corresponding time information is output based on the level differences A and B at the two sample points a and b. Input A of the storage device 149;
B and the output are both 4-bit data, for example, and the first 1 bit of the 4 bits of inputs A and B is a sign bit and is expressed as a two's complement number. Storage device 14
The time information that is the output of 9 is the time difference between the time point C at which the signal level of the synchronization signal exceeds the reference level VTI-12 and sample point a or b, and thereby the time point C coincides with the sample point in time. Even if this is not the case, the position of the falling edge of the synchronization signal can be accurately detected.

Next, the minimum value detection circuit 20 in FIG. 21 will be explained. In FIG. 25, the counter 200 counts the clock so that the first
The second period pulse is generated at intervals of a period longer than one day. These period pulses are supplied to the selector 201, and the first period pulse is used in a steady state, and the second period pulse is used in an unsteady state where the rotation of the disk is unstable, such as when the spindle motor 24 starts rotating, or when a CLV search or scan is performed. Pulses are selected and provided to register 202 and averaging circuit 203. L
The comparator 204, which uses the digitized video signal output from the PF 145a, inputs its input data 8 and the register 20.
The data B stored in the register 202 is compared with the data B stored in the register 202 every time a clock occurs, and the smaller data is supplied to the register 202.

However, the comparator 204 is designed to stop its operation when dropout occurs. Since the register 202 is reset by the first or second period pulse supplied from the selector 201, the smallest value from the previous reset time will be stored in the register 202. The minimum value stored in register 202 is the first or second
The average value is loaded into the averaging circuit 203 every time a period pulse occurs, and the averaging circuit 203 averages each minimum value of two or more detection periods and outputs the average value as the minimum value.

In such a configuration, since the minimum value of the video signal usually appears during the synchronization signal period, a 1H period is set as the detection period (first period pulse generation interval). In an unsteady state such as during a CLV search or scan, the rotation of the disk is not stable, so the length of one day period fluctuates.

At this time, if minimum value detection is performed at normal intervals based on the first period pulse, there may be cases where the synchronization signal is not included within the interval. Therefore, in an unsteady state, by using a second period pulse that is generated every period longer than the 1H period, the synchronization signal will be included within the detection period, so the minimum level can be detected reliably. This means that fluctuations in the minimum level can be reduced. In addition, when a dropout occurs, a value that is temporarily lower than the signal level of the synchronization signal may occur, but by stopping the operation of the comparator 204 and inhibiting the detection operation during the dropout period, the minimum value This means that false detections can be prevented.

In addition, the counter 200 is activated by the dropout detection signal.
Since the counter 200 starts counting the predetermined period again after the dropout, even if the synchronization signal part is lost due to a dropout, the level of the synchronization signal part is reliably reached before the next period pulse is generated. Detection can be performed.

The clock generation circuit 21 in FIG. 1(B) generates 4 fsc (fsc is the subcarrier frequency) based on the reference horizontal synchronization signal from the reference signal generator 22 or the horizontal synchronization signal or color burst signal from the signal separation circuit 14. It generates a clock of 4Nfsc (for example, 12fsc) and has a PLL (phase locked loop) circuit configuration. 4fsc and 4 generated here
The NfsC clock is used as a glue lock for digital signal processing, and the sampling clock of the A/D converter 4 and the signal processing clock up to the video LPFIO are set to 4Nfsc, and the clock is set to 4fs from the output of the video LPF 10.
Downsample to c.

The configuration of the clock generation circuit 21 is shown in FIG.

In this figure, a phase comparator 210 that uses a color burst signal as a comparison reference input is connected to a sampling pulse generation circuit 21.
1, the sampling pulses CK+, C
Phase comparison is performed in response to K2. Note that when locking the PLL to the reference horizontal synchronization signal or the horizontal synchronization signal, the phase comparator 210 is not used, and another phase comparator (not shown) is used to lock the PLL to one of these signals at 2fs.
Compare the phase of c with the signal of 1/455L and f+-+,
The output is input to LPF212.

Hereinafter, only the case of locking to the color burst signal will be explained. The comparison output of the phase comparator 210 is LPF2
The signal is supplied to the D/A converter 213 via the signal line 12, where it is converted into an analog signal and becomes a control signal for the VCO (voltage controlled oscillator) 214. The oscillation frequency of VGO214 is 12fsc
The clock is set to 12fsc, and is output as is as a clock of 12fsc, and the frequency is divided to 4fsc by a 1/3 frequency divider 215. This clock 4fsc is output as it is, serves as the sole power of the sampling pulse generation circuit 211, is further divided into fsc by 172 frequency dividers 216 and 217, and becomes a comparison input of the phase comparator 210. The gate pulse generated by the gate pulse generation circuit 218 is supplied to the sampling pulse generation circuit 211 as an external power, and therefore the sampling pulses CK+ and CK2 are supplied to the phase comparator 210 only during the generation wJ of the gate pulse. It turns out. The gate pulse generation circuit 218 synchronizes with 4 fsc based on the horizontal synchronization signal, and generates Goo 1 to Pulse (B) only during a period corresponding to the central portion where the amplitude of the color burst signal (A) is constant, as shown in FIG. occurs.

In the phase comparator 210, as shown in FIG.
The color burst signal becomes the output of the adder/subtractors 219 and 220, and each addition/subtraction output passes through delay circuits 221 and 222 and becomes the output of the adder and subtractor 219 and 220, and is divided by the divider 223. The addition/subtraction (±) control of the adders/subtractors 219 and 220 is performed using the clock pulse fsc shown in FIG.
Based on (B), addition is performed at sample points S+ and Sz, and subtraction is performed at sample point 83.8a. However, when a track jump is performed for still image playback, etc., the phase of the color burst signal changes by 180', so the clock pulse fs changes every time a track jump occurs.
c Reverse the phase of (B) to maintain PLL lock. This is the system controller 18 in FIG. 1(B).
This is done by controlling the 1/2 frequency divider 217 using the 0-ma inversion control signal supplied from the 1/2 frequency divider 217.

Further, the sampling pulse generation circuit 211 is composed of a D-type flip-flop, and has a sampling clock CK+
, CK2 is synchronized with 4fsc, and 1 of that frequency
/2 and have opposite phases to each other, and serve as clocks for the delay circuits 221 and 222 only when the gate pulse is at a high level.

As a result, assuming that the amplitude of the color burst signal (A) is A, ΣΔsinθ is derived as the output of the delay circuit 221, ΣA CO3θ is derived as the output of the delay circuit 222, and tanθ is derived as the output of the splitter 223. Ru. Then, this division output tanθ is converted to the tan' circuit 224.
By passing , the phase difference θ is reduced by 19.

That is, the phase difference θ in the phase comparator 210 can be calculated from the following equation.

θ=jan-' (Σ[(S+ -83)/(S2-
84)]) Here, S+=A-sin θ 52=A-
CO3θS]=-△-sinθ 34 =-A-cos
θBy the way, as is clear from the above formula, if the amplitude Δ of the color burst signal (A) is not constant within 1H,
A slight error will occur in the detected phase difference θ, and a change in loop characteristics will occur due to a change in the loop gain of the PLL.

However, in the clock generation circuit 21 described above, 81 to
Sampling pulse CK+ for obtaining S4.

By applying a gate to CK2, phase comparison is performed only during a period in which the amplitude A of the color burst signal (A) is constant, so that the above-mentioned problem does not occur.

In the above configuration, phase comparison is performed only in the central portion of the color burst signal by applying a gate to the sampling pulse, but it is of course possible to apply a gate to the color burst signal itself. . In this case, since it is a digital gate, only the central part of the color burst signal can be extracted more accurately than an analog switch or the like. Furthermore, in FIG. 26, the arrangement relationship between the LPF 212 and the D/A converter 213 may be reversed.

In FIG. 1(B), a reference signal generator 22 includes a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronization signal. The spindle servo circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronization signal from the reference signal generator 22 and the horizontal synchronization signal from the signal separation circuit 14. The chroma inversion circuit 25 adjusts the chroma (color) as necessary to maintain color framing even during special playback such as still playback and slow playback.
A phase inversion of the signal is performed.

The configuration of this chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is sent to a one-day delay circuit 270.
1 adder 271. After the signal level of the output of the adder 271 is halved by the level adjustment circuit 272,
It is supplied to a subtracter 273. The subtraction output of the subtracter 273 is supplied to the adder 275 via a phase linear acyclic digital BPF 274, and the addition output of the adder 275 is as follows.
The signal is supplied to the changeover switch 276.

The delayed output of the delay circuit 270 is sent to the subtracter 273 and BPF2.
The signal is supplied to a delay circuit 277 having the same delay amount as 74, and is also supplied to an adder 271 via a one-day delay circuit 278. The delayed output of delay circuit 277 is supplied to adder 275 and changeover switch 276. The changeover switch 276 is appropriately switched depending on the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).

With this configuration, a 2.3-line correlation mouth filter is configured, and the subtracted output of the subtracter 273 is transmitted to the one-day delay circuit 2.
A chroma signal (-2G) with an opposite phase and twice the level as compared to the delayed output of 70 (assumed to be Y+C) is obtained. After this chroma signal has unnecessary components removed by the BPF 274, the delay circuit 277 adjusts the delay m and outputs the delay (
Y+C) is added by an adder 275, and a digitized video signal (b) having a chroma signal inverted with respect to the delayed output (a) of the delay circuit 277 is obtained as an addition output. For special playback such as stay and slow, selector switch 27
Color framing can be maintained by switching the chroma inversion control signal from the system controller 18 of FIG. 1(B).

In FIG. 1B, the output of chroma inversion circuit 25 is supplied to video processing circuit 38. In FIG. The video processing circuit 38 performs character insertion, MC eight head suppression, squelch, and the like. The digitized video signal that has passed through the video processing port 2838 is a 4fsc signal that is generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal.
The data is written to three buffer memories by the clock. Reading from the buffer memory 39 is performed using a 4fsc reference clock generated by the reference signal generator 22. In this way, by reading data from the buffer memory 39 using a stable reference clock that is unrelated to the reproduced signal, jitter in the reproduced signal can be absorbed, eliminating the need for so-called tangential servo or color correction circuits. Become. The digitized video signal read from the buffer memory 39 is converted into an analog signal by the D/A converter 40 and supplied to the output terminal 42 via the LPF 41 .

The system controller 18 has the following main functions. That is, 1. Various servo systems are controlled in response to commands from operating units such as panel switches and remote controls, and state signals from the servo system, to cause the player to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generate signals for compositing frame numbers, chapter numbers, etc. onto the screen.

4. Synchronize the internal counter with the horizontal synchronization signal and vertical synchronization signal, and decode the output of the counter to generate various timing signals.

5. Control the PLL loop for clock generation. A specific configuration for realizing the fourth function among the above main functions will be described below.

In Figure 31, the horizontal synchronization signal (1 stone) is converted to data (D
) input and a 4fsc clock signal as a clock (C
K) A D-type flip-flop 180 is provided as an input, and the Q output of this flip-flop 180 is NAN.
It will become the sole strength of D Gate 181B. NAND gate 18
1B has the horizontal synchronization signal supplied via the inverter 181A as another input, and its output is the 1H counter 18.
3 load (L) input. The gate circuit 182A is
The output of the one-day counter 183 is decoded to generate the HS gate signal in a predetermined period and inputted to the HV separation circuit 145d in FIG. 21, and a clock HCK having a frequency of f+ synchronized with the horizontal synchronization signal is generated. . The HS gate signal is used in the HV separation circuit 145d to detect the fall of the horizontal synchronization signal excluding the equalization pulse and to separate the horizontal signals. In the initial state, the HS gate signal is always at a high level, and the 1H counter 183 is loaded at the fall of the synchronization signal, and thereafter it is kept at a high level only for a predetermined period so that the fall of the horizontal dome signal is detected every day. Become. In the initial state or for some reason, if the 1H counter 183 is loaded due to the fall of the equalization pulse and a 1/2H shift occurs, the IH counter 183 will not be loaded after the vertical blanking period.
This state is detected within the system controller 18 and the HS gate signal is kept at a high level again. Note that the HV separation circuit 145d generates a pulse of a predetermined width based on the fall of the horizontal synchronizing signal, and outputs this as the horizontal synchronizing signal. The clock HCK is a signal having a duty ratio of 50%, starting from the falling edge of the synchronization signal, and being at a high level in the first half and a low level in the second half.

The gate circuit 182A further generates various timing signals within 1H and supplies them to each circuit.

The positive polarity vertical synchronization signal (VS) becomes each clock input of D-type flip-flops 184 and 185.

The D-type flip-flop 184 receives the S gate signal outputted from the gate circuit 182B as a data (D) input, and when the vertical synchronization signal rises while the signal is at a high level, its Q output goes to a high level. The Q output goes to low level and maintains that state until the reset signal goes to low level. When the reset signal goes to low level, the Q and Φ outputs are inverted.

The D-type flip-flop 185 receives the clock HCK output from the gate circuit 182A as a data input, and is used to determine whether the vertical synchronization signal is from field 1 or field 2.
Then, when the clock HCK is at a low level, the rising edge of the vertical synchronization signal arrives, so the Q output goes to a low level and the d output goes to a high level.In field 2, the rising edge of the vertical synchronizing signal comes when the clock 1-ICK is at a high level. Zuru de Q
The output is a high level, and the 0 output is a low level. The D-type flip-flop 186 uses the Q output of the flip-flop 184 as a data input, the clock HCK as a clock input, and the Q output of the flip-flop 185 as a clear input. When the clock HCK rises, the Q output becomes high level, and in field 1, the Q output remains low level.

The Q and Φ outputs of the D-type flip-flop 184 are J.

The flip-flop 187 uses GK as the inverted clock input and the Φ output of the flip-flop 185 as the clear input. When the clock HCK falls, the Q output becomes high level, and in field 2, the Q output remains low level. NOR gate 1 with two inputs for each Q output of flip-flop 187 on D-type flip-flop O-tube 186 and J-
88 uses the output of the 17 frame counter 1 in the next stage.
89 and resets the D-type flip-flop 184. Here, the reason why a load pulse is created using a separate flip-flop for each field is that the load pulse, which has a sufficient width in any field, is
This is to send out to 18 frame counters. The 1 frame counter 189 is a 525-decimal counter that counts the clock HCK, and is loaded with the clock HCK when the output of the NOR gate 188 is at a low level.
D type flip-flop 18 so that the number is increased by 63
It is controlled by the d output of 5.

The gate circuit 182B decodes the outputs of the 18 one-frame counters and generates the aforementioned VS gate signal in a predetermined period, and also generates a timing signal in units of H within one frame and supplies it to each circuit.

Next, the fifth of the above-mentioned five functions of the system controller 18, ie, the function of controlling the clock generation PLL loop, will be explained based on the flowchart of FIG. 32. As mentioned above, this PLL has two phase comparators: one for locking to the reference horizontal synchronizing signal or the reproduced horizontal synchronizing signal, and the other for locking to the color burst signal. The configuration is such that three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal at the input section of the phase comparator, and by switching the phase comparator itself. In FIG. 32, in an initial state such as when the electric current is turned on or when the spindle motor is forcibly accelerated, the reference signal generator 22 (see FIG. 1), which is the reference for the spindle servo,
The slip Pl to be locked to the reference horizontal dome signal obtained in (see B)).

A loop of L operates (step 1). When it is determined that the loop is locked to the reference horizontal synchronization signal (step 2) and the horizontal synchronization signal becomes 17 times the reproduction video signal, the loop is switched to the reproduction horizontal synchronization signal (step 3). At this time, if it is determined that locking is not possible (step 4),
Return to step 1 and loop back to the reference horizontal dome signal. If it is determined in step 4 that it is locked to the playback horizontal synchronization signal, the presence or absence of a color burst signal is detected in step 5), and if there is no color burst signal, the process returns to step 4 and the lock is maintained to the playback horizontal synchronization signal. . This state occurs during the vertical blanking period for both black and white discs and color discs. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). Here, if it is determined that the color burst signal cannot be locked (step 7), the process returns to the loop of the reproduced horizontal synchronizing signal in step 3, but if it can be locked, the color burst loop state is maintained. However, at the same time, the synchronization with the playback horizontal synchronization signal must be monitored (Step 8). If either the lock with the color burst signal or the lock with the playback horizontal synchronization signal is lost, it is assumed that the lock is lost and the playback horizontal synchronization signal is looped. Return to (step 3). At this time, if the loop of the reproduced horizontal synchronizing signal fails to lock onto the reproduced horizontal synchronizing signal (step 4), the loop is further returned to the loop of the reference horizontal synchronizing signal (step 1>).

Note that a NO determination in step 4.7 indicates that the lock cannot be achieved within the predetermined interval rrJ'1 when passing for the first time, and indicates that the lock is not achieved when passing from the second time onwards.

This system has been explained above while showing the specific configuration of each circuit, but the point of this system is that all signal processing is performed digitally between the A/D converter 4 and the D/A converter 40. It has great characteristics. In this way, by digitizing the signal, it is possible to make it multi-functional, such as converting the monochrome dropout correction signal to color, chroma inversion, increasing the accuracy of Y-C separation by introducing frame memory, or increasing the accuracy of Y-C separation by introducing frame memory. Still image playback becomes easier.

In addition, in FIG. 1(B), after the adder 12.

Although the circuits are arranged in the order of dropout correction circuit 19, chroma inversion circuit 25, video processing circuit 38, and buffer memory 39, the arrangement is not limited to this.
For example, as shown in FIGS. 33(A) and (B), the order of "dropout correction circuit 19 + rear camera inversion circuit 25", "video processing circuit 38" and "buffer 1 memory 39" can be changed. be. However, since the writing and reading of the three buffer memories is asynchronous, if there are other two after "buffer memory 39" (in the case of FIG. 33 < 8), the control signals for the other two Re-synchronization or delay of timing signals is required. In addition, when there is "dropout correction circuit 19 + chroma inversion circuit 25" after "video processing circuit 38" (in the case of Fig. 33 (A))
In this case, when a character is inserted by the video processing circuit 38, a control signal is required to inhibit the dropout correction circuit 19 from performing dropout correction in the character part.

Furthermore, as shown in FIG. 34, R, G, and B separation can also be performed digitally, and the RGB separation circuit
3 is converted into an analog signal by a D/A converter 44 and sent to each analog output terminal 4 via an LPF 45.
By supplying signals to 6R, 46G, and 46B, if you connect these terminals to a monitor TV (television) with RGB input, there is no need to use the RGB separation circuit in the TV, which improves image quality. It will be possible to achieve this.

In addition, when using a digital TV that can input RGB as it is digitized, each digital signal separated by the RGB separation circuit 43 is sent directly to the digital output terminals 47R, 47G, without going through a D/A converter. 47B.

In this RG8 separation, in this system, the clock of the A/D converter 4 is set to 4Nfsc (N is an integer of 2 or more), and the 4fsc clock is locked to the color burst signal of the video signal, so the RG8 separation (demodulation) can be easily performed. A case in which demodulation is performed using the RY and BY signals will be described below, but the demodulation can be similarly performed using the 2 and Q signals.

In the NTSC system, the phase of the color signal is as shown in FIG. 35, which is quadrature two-phase modulated and frequency multiplexed with the luminance signal. The relationship between the R, G, and B signals and the luminance signal Y is shown in the following equation.

Y= 0.3OR+ 0.59 G 〇, 11 [3・
(1) Also, the color signal C in the video signal is expressed by the following equation.

RY B-Y C= -co sωCt +-5inωct1.14
2.03 ......(2) =Icos(ωct+33") + Qsin(ωct+33") ・=-(3)
Here, ωC is the angular frequency of the color carrier wave, and ωC−2π
x 3.58 MHz.

When the phase of the 4fsc sampling frequency is locked to the color burst signal at Oo, Fig. 35 and (2) are obtained.
From the formula, each sample point is ±(R
-Y)/1.14, ±(BR)/2.03. Also, from equations (1) and (2), R, G, and B signals are obtained. Furthermore, I.

To obtain the Q signal, ±33° relative to the color burst signal.
Alternatively, the phase may be locked at ±57°.

From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst signal.

In the above embodiment, the case where the system is applied to an NTSC video disc player has been described, but this system is applicable to VTR playback side signal processing, PAL, SEC
It can also be applied to AM video disc players and the like.

As explained above, according to the present invention, the data that is input to the synchronization separation circuit is digitally pedestally clamped and then bits are reduced, and video processing is performed based on this bit-reduced data. Now that we have done that, let's consider the video processing circuit only when the player is in a steady state. 1, and the number of pits in the system can be set to a small number, so the circuit configuration can be simplified and video output can be obtained even in an unsteady state such as during CLV scanning. In addition, at the input stage of the synchronization separation circuit, the number of bits is set to have a wide dynamic range so that it can handle large changes in the pedestal level during unsteady conditions of the player, so even under unsteady conditions, the synchronization signal remains can be reliably detected.

[Brief explanation of drawings]

1(A) and (B) are block diagrams showing an embodiment of a video signal reproducing device according to the present invention, FIG. 2 is a block diagram showing a specific configuration of the digital BPF in FIG. 1(A), FIG. 3 is a block diagram showing an example of the configuration of the video LPF in FIG. 1(B), FIGS. 4(Δ) to (C) are spectrum diagrams of each part (A) to Figure 5 is the third
6 to 8 are block diagrams showing the specific configuration of the FIR filter, downsampling circuit, and FIR filter in FIG. 3, and FIG. 9 is another configuration of the video filter. 10 is a block diagram showing another configuration of the bit reduction process in FIG. 1(B), and FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit in FIG. 1(B). A block diagram, FIG. 12 shows an operation waveform diagram of each part in FIG. 11, and FIG. 13 shows the specific configuration of the falling detection circuit, rising detection circuit, timing signal generation circuit, and sample period signal generation circuit in FIG. 11. Block diagram, Figure 14 is a block diagram showing another configuration of the pedestal level detection circuit, Figure 15 is an operation waveform diagram of each part in Figure 14, Figure 1a is the falling detection circuit and timing signal detection in Figure 14. 17 is a block diagram showing the specific configuration of the dropout correction circuit in FIG. 1(B). FIG. 18 is a waveform for explaining the circuit operation of FIG. 17. 19 is a waveform diagram for explaining the circuit operation of the dropout detection circuit in FIG. 1<A), and FIG. 20 is a waveform diagram for explaining the circuit operation of the dropout detection circuit in FIG. 1 (B). Waveform diagram showing the relationship between
FIG. 1 is a block diagram showing the specific configuration of the signal separation circuit, FIG. 22 is a waveform diagram for explaining the operation of the signal detection circuit in FIG. 21, and FIG. 23 is a block diagram showing the specific configuration of the signal detection circuit. FIG. 24 is a block diagram showing an example of the time table stored in the ROM in FIG. 23, FIG. 25 is a block diagram of the specific configuration of the minimum value detection circuit in FIG. 21, and FIG. Block diagram showing the specific configuration of the clock generation circuit in FIG. 1(B), No. 27
The figure is a waveform diagram of each part in FIG. 26, FIG. 28 is a block diagram showing the specific configuration of the phase comparator in FIG. 26, and FIG.
The figure is a waveform diagram for explaining the circuit operation of Figure 28.
0 is a block diagram showing a specific configuration of the chroma inversion circuit in FIG. 1(B), and FIG. 31 is a block diagram showing the configuration of part of the hardware for performing the predetermined functions of the system controller in FIG. 1(B). The block diagram shown in FIG. 32 is a flowchart of predetermined functions of the controller, and FIG. 33 (
A). (B) is a block diagram showing a modified example of this system, No. 34
The figure is a block diagram showing another modification, and FIG. 35 is a block diagram showing another modification.
FIG. 4 is a phase characteristic diagram of a color signal used to explain the principle of RGB separation, and FIG. 36 is a waveform diagram of a signal at each sample point. Explanation of symbols of main parts 2...Analog PF 4...A/
D converter 6... Digital BPF 7... FM detection circuit 10... Video LPF 13... Pedestal level detection circuit 14
... Signal separation circuit 17 ... Dropout detection circuit 18 ...
... One system controller ... Dropout correction circuit 21 ... Clock generation circuit 22 ... Reference signal generator 24 ... Spindle motor 25 ... ... Chroma inversion circuit 38 ... Three video processing circuits ... Buffer memory 40 ... D/A converter

Claims (1)

[Claims] an A/D (analog/digital) converter that digitizes an FM video signal; a first digital filter that extracts only components necessary for detecting the video signal from the output of the A/D converter; an FM detection circuit that performs FM detection on the output of the digital filter; a second digital filter that extracts only the baseband component of the video signal from the detection output of the FM detection circuit; and a synchronization signal from the output of the second digital filter. a pedestal clamp circuit that clamps the pedestal level of the output of the second digital filter to a predetermined reference level; and a bit reduction circuit that reduces the number of quantization bits of the output of the pedestal clamp circuit. , a buffer memory that stores the output of the second filter using a clock signal synchronized with the horizontal synchronization signal or color burst signal included in the output, and sequentially outputs the stored information in synchronization with a predetermined reference clock signal. and a D/A (digital/analog) converter that converts the digitized video signal outputted from the buffer memory into an analog signal, the number of quantization bits of the output of the second digital filter being in an unsteady state. A video signal reproducing device characterized in that a value is set to correspond to changes in a pedestal level.