JPS62140589A - Video filter circuit - Google Patents

Abstract

PURPOSE:To compensate excellently the phase characteristic of recorded information by arranging a phase linear noncyclic digital filter to a prestage, arranging a cyclic digital filter to a post-stage and decreasing the sampling frequency at the post-stage. CONSTITUTION:A base band video signal and its 2nd order harmonic wave are included in an FM detection output A and only a base band video signal B is led out at the output terminal through an FIR filter 100. The base band video signal B is down-sampled by a down-sampling circuit 101 from a 4Nfsc clock frequency into a 4fsc clock frequency. In decreasing the sampling frequency in this way, it is possible to reduce the time margin and the hardware. Since the band of the digitized video signal is narrow as nearly 4.2MHz through the FIR filter 100, no hindrance is caused even when the sampling frequency is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video filter circuit, and more particularly to a video filter circuit in a video signal processing device J3 that digitally reproduces and processes a video signal that has been FM modulated and recorded on a recording medium. It is related to.

In a video disc player that plays back a recording medium, such as a video disc, on which a video signal is FM-modulated and recorded, the FM-modulated video signal read from the disc (hereinafter referred to as FM 11!l! image signal) Conventionally, signal processing (denoted as ) has generally been performed in an analog manner.

However, when considering the integration of circuits into ICs (integrated circuits), it is extremely advantageous to perform signal processing digitally rather than analogously, and multifunctionality can be easily realized in the signal processing process. This means that even higher image quality can be achieved.

By the way, in the case of a bidet sub-disk, etc., the signal processing system for the reproduced signal has traditionally been analog, so the phase will be rotated in a bidet designed in analog; a tLPF (low pass filter). When information is recorded, information is recorded by distorting the video LF'F in the opposite direction by inversely compensating for the phase distortion. Therefore, when a video disc having such a recording format is reproduced and the reproduced signal is digitally processed, it is necessary to further compensate for the phase distortion during recording.

The present invention has been made in view of the above-mentioned points, and is aimed at improving the phase characteristics of recorded information in correspondence with analog processing when performing digital signal processing of 1M video (No. ii). It is an object of the present invention to provide a compensable video filter circuit.

The video filter circuit according to the present invention includes a phase-linear acyclic digital filter at the front stage that removes a carrier wave component included in the digitized video signal, and a cyclic digital filter at the rear stage that compensates for the phase characteristics of the digitized video signal. including subki X/rear frequency f'sc
In the case of It is configured to operate at a clock frequency of .

Length-JLJI Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1(A), an FM video signal read from a recording medium such as a video disk is passed through an input terminal 1, an analog LPF (low pass filter) 2, and an A/D converter.
(analog/digital) converter 4. The LPF 2 removes aliasing distortion in A/D conversion, but the LPF 2 removes aliasing distortion in A/D conversion.
ωS is the sampling frequency at the time of A/D conversion) or above), the LPF 2 may be omitted if there are very few components.

The digitized FM video signal output from the Δ/D converter 4 is supplied to a digital BPF (band pass filter) 6. This digital BPF 6 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM audio signal, and supplies the extracted components to the FM detection circuit 7 at the next stage.

For example, as shown in FIG. 2, the digital BPF 6 includes delay circuits 601 to 60n connected in series that delay one clock, and input signals of the delay circuit 60+ and output signals of the delay circuits 601 to 60n. An FIR filter (acyclic digital filter) is used, which is composed of multipliers 61o to 61n that multiply the multiplication coefficient by □-kn, an adder 62 that adds the outputs of each multiplication, and a latch circuit 63 that latches the added output. The multiplier 610~
By appropriately selecting each of the multiplication coefficients kO to kn of 61n, desired amplitude characteristics and group delay characteristics can be obtained. Therefore, when group delay distortion occurs due to the analog LPF 2, by making the group delay characteristics of the digital BPF 6 inverse to those of the analog LPF 2, the digital FM
A video signal can be supplied. Also, analog LP
If the group delay distortion of F2 is small and can be ignored, or if you delete analog PF2, use digital BPF6.
By using a phase linear type filter in the same way, a signal without group delay distortion can be obtained. In FIG. 2, the coefficients KO to Kn of the digital BPF 6 are set symmetrically around n (
Ko=Kn.

If K+=Kn-+...-), it becomes an ideal phase linear filter.

The FM detection circuit 7, for example, as shown in FIG. 1(A),
A Hilbert transformer 70 performs Hilbert transform on a digitized FM video signal, a delay circuit 71 delays the digitized FM video signal by n sample periods, and each output signal of the Hilbert transformer 70 and delay circuit 71 is squared. A sum-of-squares circuit 72 for adding, a delay circuit 73 for delaying the output signal of the delay circuit 71 by one sample period, a multiplier 74 for multiplying each output signal of the delay circuits 71 and 73, and the output of this multiplier 74. A divider 75 divides the signal by the output signal of the square sum circuit 72. The Hilbert transformer 70 is composed of a transversal filter and the like.

Furthermore, the delay time of the delay circuit 71 is determined by the Hilbert transformer 70.
This corresponds to the delay time of The FM detection circuit 7 having such a configuration is disclosed in Japanese Patent Application No. 59-2624 by the applicant of the present application.
Proposed in No. 81.

In FIG. 1(B), a video LPF 10 to which the detection output of the FM detection circuit 7 is supplied extracts only the baseband component of the video signal from the detection output. video LP
The cutoff frequency of the FIO is set to, for example, 4.2 MH2 in the case of the NTSC system. Figure 3 shows the video LPF
An example configuration of 10 is shown in this video LPF1
0 is a phase-linear acyclic digital signal at the front stage that operates at a clock frequency of 4Nfsc (N is an integer of 2 or more) and removes the carrier component contained in the FM-detected digital video signal and extracts only the baseband component. filter(
FIR filter) 100 and this FIR filter 100
a down-sampling circuit 101 that downsamples the output of the circuit to a clock frequency of 4fsc, and a subsequent cyclic digital filter (■
IR filter) 1o2.

In Fig. 4 (A) to (C), each part (A) in Fig. 3 is shown.
-(C) spectra are shown.

The FM detection output (A) includes not only the baseband video signal but also its second harmonic component, which is passed through the FIR filter 10.
By passing through 0, only the baseband video signal (B) is derived at the output end. This baseband video signal (B) is transmitted to the Da Kun sampling circuit 10.
1, the clock frequency of 4Nfsc is downsampled to the clock frequency of 4fsc. The spectrum after downsampling is the same as that in Figure (B).

By lowering the sampling frequency in this way, it is possible to save time and reduce the amount of hardware required.

Note that since the band of the digitized video signal is narrowed to about 4.2 MH7 by passing through the FIR filter 100, there is no problem even if the sampling frequency is lowered. After downsampling, the baseband video signal (B) is compensated for its phase characteristics by an IIR filter 102. The spectrum (C) after phase compensation is also the same as that in Figure (B).

In the case of video disks, etc., the signal processing system for the playback signal has traditionally been analog, so the phase distortion of the video LPF is calculated when recording information, assuming that the phase will rotate in a video LPF designed in an analog manner. Information is recorded by distorting it in the opposite direction with reverse compensation. Therefore, when playing back a video disc with such a recording format and digitally processing the playback signal, it is necessary to further compensate for the inverse compensation valve for phase distortion during recording, and compensation for this phase characteristic is necessary. is the IIR filter 102
It is done in In Fig. 5, 11R filter 1
02 phase characteristics are shown. .

6 to 8 show examples of specific configurations of the FIR filter 100° downsampling circuit 101 and the IIR filter 102. First, in Figure 6,
The FIR filter 100 includes delay circuits 1031 to 103n connected in series to each other for delaying one clock;
Input signal of delay circuit 1031 and delay circuits 103+ to 1
Multipliers 1040 to 104n that multiply each output signal of 03n by a multiplication coefficient kO to kn, an adder 105 that adds each multiplication output, and a latch circuit 106 consisting of a D-type flip-flop or the like that latches the added output. The clock frequency of the delay circuits 1031 to 1030 and the latch circuit 106 is set to 4Nfsc. As shown in FIG. 7, the downsampling circuit 101 is constituted by a latch circuit 107 consisting of a D-type flip-flop or the like, and its clock frequency is set to 4 fsc.

As a result, the data input to the latch circuit 107 is N
- Output every other item.

Moreover, as shown in FIG. 8, the IIR filter 102
A multiplier 1080 that multiplies an input signal by a multiplication coefficient ko, an adder 109 that uses this multiplication output as one addition input, a latch circuit 110 consisting of a D-type flip-flop or the like that latches this addition output, and an adder 109 Delay circuits 1111 to 111n connected in series to each other sequentially delay the addition output by one clock, and these delay circuits 1111 to 1.
Multiplier 1 that multiplies each output of 11n by a multiplication coefficient of 1 to kn.
081 to 108n, and the clock frequency of the latch circuit 110 and delay circuits 1111 to 111n is 4f.
It is set to sc. In this circuit configuration, the phase characteristics shown in FIG. 5 can be obtained by appropriately setting the multiplication coefficients of the multipliers 1080 to 108n to kn.

In the video LPF 10 described above, the phase straight line FI
By using the R filter 100 at the front stage, all phase compensation can be determined only by the IIR filter 102 at the rear stage, and the amplitude characteristics can be adjusted without changing the phase characteristics.

Note that downsampling is performed before the ITR filter 102, but this is because I[<filter 102 is 1
This is due to the fact that all operations must be completed within a clock period. In order to perform downsampling after the IIR filter 102, pipeline processing is impossible for the above-mentioned reasons, and the number of operations must be reduced or high-speed elements must be used, but there are limits to this as well. On the other hand,
If downsampling is performed before the IIR filter 02, the clock cycle will naturally become longer, and if the number of operations increases accordingly, more accurate characteristics will be obtained and stability will also increase.

In the video LPF 10 configured as described above, the front stage F
The IR filter 00 is operated at 4Nfsc, and the output is converted to 4fsc by the downsampling circuit 101.
However, as shown in FIG. 9, downsampling is performed before the arithmetic circuit in the FIR filter 100', and the clock after the arithmetic circuit is downsampled at 4fs.
It is also possible to configure it to operate with c-glue lock. At this time, the downsampling circuit 101 is not necessary.

That is, in FIG. 9, the FIR filter 00' includes delay circuits 1121 to 112n that are connected in series to delay one clock, and input signal and delay circuit 1.
latch circuits 1130 to 113n consisting of D-type flip-flops that latch each output signal of 121 to 112n;
Multipliers 1140 to 114n multiply each latch output of these latch circuits 1130 to 113n by a multiplication coefficient of □-kn.
, a latch circuit 116 consisting of a D-type flip-flop that latches this addition output, and delay circuits 1121 to 112n.
The operation of the latch circuits 1130 to 113n in the next stage is performed with the clock of 4Nfsc, and the operation of the final stage arithmetic circuits (multipliers 1140 to 114n,
The operation of the adder 115 and latch circuit 116) is 4 fsc.
The configuration is such that the operation is performed using the same clock.

In the FIR filter 100' having such a configuration, the calculation is 4f.
Since it is performed using the sc clock, unnecessary calculations are omitted,
In addition, since the clock cycle becomes longer, it is possible to increase the number of vJ paralysis, and relatively, the FIR filter 1 with the above-mentioned configuration
This means that the circuit scale can be reduced compared to 00.

Note that in order for the FIR filter to have a phase linear characteristic in FIGS. 6 and 9, the coefficient Ko−Kn must be symmetrical with respect to the center (K○−)(n,
K+ = Kn-1,...).

Referring again to FIG. 1(B), the digitized video signal that has passed through the video I-P F 10 passes through the de-emphasis circuit 11 and is then passed through the adder 12, the pedestal level detection circuit 13, and the signal separation circuit constituting the pedestal clamp means. 14.

By the way, when performing digital signal processing, it is clear that a smaller number of interdigitated bits per word (bit/word) is advantageous in designing a circuit.

However, when considering the 1M detection output, the output level is constant in the steady state of the disc player, but there are irregularities such as the rise of rotation of the spindle motor 24, and the collision and scanning during CLV (constant linear velocity) disc playback. In a steady state, the DC component of the video signal changes significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle servo circuit 23 cannot be locked, and the clock generation circuit 21 cannot be synchronized, so the steady state cannot be achieved forever, so the synchronization signal can be detected even in the unsteady state. You need to be able to do it. For this purpose, the number of bits n must be set based on the unsteady state.

Therefore, at least the number n of bits from the input of the signal separation circuit 14 to the output of the de-emphasis circuit 11 is set to a number of bits with a wide dynamic range that is sufficient even if the pedestal level changes significantly based on the unsteady state. n
Set to l (bit/Word). As a result, not only in a steady state but also in an unsteady state, the signal separation circuit 14 receives the 1M detection output that has passed through the de-emphasis circuit 11
This means that the synchronization signal can be reliably detected.

The pedestal level detection circuit 13 detects the pedestal level V
po is detected and the pedestal level Vp is determined from the reference voltage VRF.
generates an output (VRr: -Vpo) with o subtracted,
The adder 12 adds it to the digitized video signal to cancel fluctuations in the pedestal level, thereby digitally pedestally clamping the video signal. The pedestal-clamped n 1 (bit/word) data is output from the adder 12 into n 2 (bit/word) data.
word) data (nl<nl
). nl is determined by the dynamic range and resolution required for a video signal in a steady state. This bit reduction facilitates the circuit design of the adder 2 and subsequent parts. Furthermore, by performing pedestal clamping, the signal level of the digitized video signal will be within the dynamic range of n 2 (bit/word) not only in the steady state but also in the unsteady state, so when scanning the CLV. This means that images can be viewed even in unsteady conditions such as.

In the above configuration, regarding the dynamic range of each circuit constituting the digital signal processing system, the dynamic range up to the input of the signal separation circuit 14 is n l (bit/WOrd), and regarding video processing, the pedestal is digitally After clamping, n 2 (bit/w
The output of the digital FM detection circuit 7 was separated into two systems, a video processing system and a signal separation system, and each It is also possible to make the number of bits n of prefectures different.

That is, in FIG. 10, the number of bits n of the signal separation system
is the number of bits n + with a wide dynamic range that is sufficient even if the pedestal level changes significantly in an unsteady state.
(bij/Word). This n + (
The data (bit/word) is supplied to the signal separation circuit 14 via the LPF1 6. The LPF16 may be any filter that has characteristics that allow the synchronization signal to be detected from its output, and therefore the configuration can be simplified by using simplified filter coefficients. On the other hand, regarding the video processing system, please refer to nl.

The dynamic range is set to a small number of bits n 2 (bit/word). nl is determined by the dynamic range and resolution required for the average signal in a steady state.

In this way, the digital FM detection output is nl.

By separating into two systems of n 2 (bit/word), the circuits after the video LPF 10 can be designed by considering only the steady state case, so the circuit configuration can be simplified, and the spindle motor 24 This means that the synchronization signal can be reliably detected even in an unsteady state such as the rise of the signal.

In addition, in such a circuit configuration, in an unsteady state, there may be cases where the image cannot be seen due to changes in the pedestal level, but this is only possible if the image can be seen in the steady state, and the synchronization signal can be reliably detected in the unsteady state. It is based on ideas. However, in the CLV scan, since the clock generation circuit 21 is synchronized to some extent, changes in the pedestal level are often small, and in this case, the image can also be viewed.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit 13. In this figure, LPFl
The digitized video signal (a) from which the color burst has been removed in step 17 is supplied to a pedestal sampling circuit 118 and a sync separation circuit 119, respectively. Synchronous separation circuit 1
At step 19, the synchronization signal (b) included in the digital video signal (a) is separated and extracted, and the synchronization signal @(b) is supplied to a rise detection circuit 121 and a fall detection circuit 120, respectively. The falling detection circuit 120 receives the first gate signal (
The rising detection circuit 121 detects the falling of the synchronizing signal @(b) during the period in which the signal C) is generated, and the rising of the synchronizing signal (b) during the period in which the second gate signal (d) is generated.

The timing signal generation circuit 122 generates a first gate signal (C) based on a clock signal during a period in which a dropout detection signal (q) from a dropout detection circuit 17 (see FIG. 1(A)), which will be described later, is not generated. The dropout detection signal @(q
) is not generated, the second gate signal @(d) is generated.

The sample period signal generation circuit 123 generates a sample period signal (e) of a certain period in response to the detection output of the rising edge detection circuit 121, and supplies it to the pulse generation control circuit 124.

The pulse generation control circuit 124 is, for example, a three-way AND circuit that receives the number period signal (e) and the dropout detection signal (Q) from the sample period signal generation circuit 123.
The gate 125 and the detection output of the rising edge detection circuit 121 are set (S) input, the output of the AND gate 125 is set as the reset (R) input, the output of the AND gate 125 is set as the clock (GK) input, and its Q output is set as the AND gate 125's output. It consists of a single SR flip-flop 126, and supplies the output pulse of the AND gate 125 to the pedestal sampling circuit 118 as a sampling pulse (f). The pedestal sampling circuit 118 is composed of a D-type flip-flop or the like, and latches the pedestal level Vpo of the digitized video signal in response to the sampling pulse (f). The sampled pedestal level Vpo is subtracted from the reference level VRF by the performance circuit 127 and averaged among the plurality of H's, resulting in a detection output of the (VRp-Vpo) level.

Figure 12 shows the operating waveforms of the circuit in Figure 11, and Figures (a) to (0) show the waveforms of each part (a) to (q) in Figure 11, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the fall of the horizontal synchronization signal included in the synchronization signal (b) is detected by the first gate signal (C), and the horizontal synchronization signal is detected using this fall as a reference. After a time corresponding to @width, a second gate signal (d) is generated to detect the rise of the horizontal synchronization signal (b), and the sample period signal (
e), it is possible to reliably capture the horizontal synchronizing signal and sample the pedestal level on the back porch during the horizontal blanking period. Further, since the color burst has been removed from the digitized video signal (a) by the LPFI 17, it is possible to generate a sample period signal (e) having a wide period including the portion where the color burst was present.

The sampling pulse (f> is the sampling period signal (
It is generated during the generation period of e) and the non-occurrence period of the dropout detection signal (q), and has a pulse width equivalent to one clock of the clock signal. Therefore, if there is a dropout that is shorter than the sample period, as shown in Figure 12 (f
), one clock worth of sampling can be reliably performed in 1H without the influence of dropout. Also, 1st. Second gate signal (C).

(d) is generated excluding the part where dropout occurs, so even if a false horizontal synchronization signal is generated due to dropout, a sample period signal will not be generated erroneously based on this horizontal synchronization signal. It is.

Output of pedestal level detection circuit 13 (VRF-Vpo
) is added to the video signal by the adder 12 in FIG. 1(B), thereby performing pedestal clamping. Further, the pedestal level Vpo is also supplied to the signal separation circuit 14 in FIG. 1(B), and in this circuit 14, synchronization signals and control signals are separated using the pedestal level Vpo as a reference level.

In the above configuration, the LPF 117 in the input section can be omitted, but if omitted, it is necessary to generate the sampling period signal in a period other than the color burst section. Furthermore, the configuration of the pulse generation control circuit 124 is not limited to the circuit configuration described above, and various configurations are possible, such as using a microprocessor, for example. Also,
The LPF 117 and the synchronization separation circuit 119 can be respectively replaced with an LPF 145a and a signal detection circuit 145C in FIG. 21, which will be described later, and these circuits may be used in common.

FIG. 13 shows the falling detection circuit 12 in FIG.
0, an example of a specific circuit configuration of a rising edge detection circuit 121, a timing signal generation circuit 122, and a sample period signal generation circuit 123 is shown. In this figure, the fall detection circuit 120 includes a D-type flip-flop 128 that receives the synchronization signal (b) as a data (D) input and a clock signal as the clock input, and an inverter 129A that receives the synchronization signal (b) as an input. , the Q output of the flip-flop 128, the first gate signal (C) from the timing signal generation circuit 122, and a 3-man power NAND gate 129B that uses the output from the inverter 129A as the 3-man power, and the Q output of the flip-flop 128. The synchronization signal (b) is delayed by one clock, and the NAND gate 129B
Then, when the synchronization signal (b) falls while the first gate signal (C) is at a high level, that is, the horizontal synchronization signal falls, all three signals become high level at the moment of the fall. A low level detection output is generated.

The timing signal generation circuit 122 includes the falling detection circuit 1
1H counter 130 which takes the detection output of No. 20 as a load (L) input and a clock signal as a clock input, and the output of this counter 130 is decoded and the first.
The gate circuit 131 generates second gate signals (c) and (d). The 1-to-1 counter 130 counts the clock for 1H period in synchronization with the falling edge of the horizontal synchronization signal, and when the video signal is NTSC, the clock is 14.3MHz=4fsc=91Of+ (
fH is the horizontal scanning frequency) and becomes a 910 progress counter. Moreover, the gate signals (c) and (d> are not generated during the period when dropout occurs.

Although not shown in the figure, if the 1H counter 130 is not loaded several times in succession, the first gate signal (C) is forced to a high level and the horizontal synchronizing signal is raised. Detect the drop. This is to prevent the 1H counter 130 from being loaded with a 1/2H shift due to the equalization pulse, which will no longer be loaded by the horizontal synchronizing signal, making it impossible to detect the pedestal level. .

The rising edge detection circuit 121 is the timing signal generation circuit 1
The second gate signal @(d) consists of a D-type flip-flop 132 which takes the second gate signal (d) from 22 as the data (D) input and the synchronization signal (b) as the clock input.
When the signal (b) rises, that is, the horizontal synchronizing signal rises while the signal (b) is at a high level, a high level detection output is generated from the Q output terminal. Sample period signal generation circuit 1
23 connects the detection output of the rising edge detection circuit 121 to a port (
L) Input and enable (EN) 7 bits 1~
The counter 133 is loaded with 90'' until just before the horizontal synchronizing signal rises, starts counting at the rising edge of the horizontal synchronizing signal, and uses the period from “96” to “127” as a sample period to output the number period signal (e). When the count exceeds ``127'' and becomes 0'', the D-type flip-flop 132 is cleared and the load input and enable input are set to low level, returning to the load state and stopping.

Note that the fall detection circuit 120 and the timing signal generation circuit 122 are similar to the HV separation circuit 1 in FIG. 21, which will be described later.
45d and a part of the timing signal generation section of the system controller 18 in FIG. 31, the falling edge detection of the horizontal synchronizing signal in the 1-IV separation circuit 145d, and the D-type flip-flop 180 and inverter 181A in FIG. 1.1FI counter 130 and gate circuit 131 may be shared by 1H counter 183 and gate circuit 182A in FIG. 31, respectively.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 13, in which parts equivalent to those in FIG. 11 are designated by the same symbols. In this figure, LPFI
The synchronization signal (b) separated and extracted by the synchronization separation circuit 119 from the digitized video signal (a) that has passed through the digital video signal (a) that has passed through the digital video signal (a) is supplied to the falling edge detection circuit 134. The fall detection circuit 134 detects the fall of the synchronization signal (b) during the generation period of the gate signal (C) output from the timing signal generation circuit 135, and supplies the detection output to the timing signal generation circuit 135.

The timing signal generation circuit 135 generates a gate signal (C) based on the clock signal during the non-generation period of the dropout detection signal (f), and also generates the gate signal (C) based on the clock signal during the period when the dropout detection signal (f) is not generated.
34 generates a sample period signal (d) at the front porch of the horizontal dome signal 1H after the falling detection timing, and supplies it to the pulse generation control circuit 136.

The pulse generation control circuit 136 includes, for example, a three-man power AND gate 137 that receives the sample period signal (d) and the dropout detection signal (f) from the timing signal generation circuit 135, and a set signal from the timing signal generation circuit 135. Set (S) input, AND gate 137 output to reset (R) input, clock signal to clock (CK
) and an SR flip-flop 138 whose Q output is used as an input to an AND gate 137,
The output pulse of the D gate 137 is converted into a sampling pulse (e
) to the pedestal sampling circuit 118. The subsequent operations are the same as those shown in FIG.

Figure 15 shows the operating waveforms of the circuit in Figure 14, and Figures (a) to (f) show the waveforms of each section (a) to (f) in Figure 14, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 14, the falling edge of the horizontal synchronizing signal is detected using the gate signal (C), and after generating a set signal using this falling edge as a reference and inquiring the AND gate 137, Since the sample period signal (d) is generated corresponding to the front porch after one day,
The pedestal level can be detected even during the vertical blanking period. Further, after sampling the pedestal level, if the falling edge of the horizontal synchronizing signal cannot be detected while the gate signal (C) is being generated, the falling edge detection circuit 134 generates a pedestal enable signal to detect the sampled level. It is possible to notify the next stage circuit that the pedestal level is invalid, or to hold the previously detected pedestal level. For example, by inputting the pedestal enable signal to the arithmetic circuit 127,
The circuit 127 previously outputted (VRF -VP D
) will continue to be output.

The gate signal (C) and the sampling period signal (d) are generated except for the part where the dropout occurs, and the pulse generation control circuit 136 generates the sampling pulse (e) for one crotch. without accidentally generating the sample period signal (d);
If the length of the dropout during the sample period does not exceed the sample period, it is possible to reliably sample one clock per 1H without the influence of dropout, as shown by the two-dot chain line in Fig. 15(e). can.

As for the example of diversion, the same aspect as in the case of the configuration shown in FIG. 11 can be considered.

FIG. 16 shows the falling detection circuit 13 in FIG.
4 and a specific circuit configuration of the timing signal generation circuit 135 are shown. In this figure, the fall detection circuit 134 is a JK flip-flop 1 which receives the synchronization signal (b) as an inverted clock input and receives the gate signal (C) as the J input.
39, when the synchronization signal (b) falls while the gate signal (C) is at high level, that is, the horizontal synchronization signal falls, the Q output becomes high level, and thereafter the reset signal becomes low level. The Q output is held high until the transition occurs. When the reset signal goes low, the Q output also goes low.

The timing signal generation circuit 135 includes a D-type flip-flop 140 which uses the Q outputs of 13 JK flip-flops as data (D) input and a clock signal as a clock input, and a D-type flip-flop 140 that uses the Q outputs of this flip-flop 140 as D input and uses the clock signal as a clock signal. D-type flip-flop 141 as input
and load the Φ output of this flip-flop 141 (L
) input, a clock signal as a clock input, and a gate circuit 143 that decodes the output of this 1H counter 142 and generates a gate signal and a reset signal in a predetermined period.
Immediately after the Q output of 39 becomes high level, a load pulse is generated for one clock from the D-type flip-flops 140 and 141 to load the 1H counter 142. 1H counter 142 that counts the period of one day in synchronization with
If the video signal is NTSC, the clock is 14.3M.
Hz=4fsc=91Of+ (fH is the horizontal scanning frequency), resulting in a 910-decimal counter.

In the gate circuit 143, the gate signal (C) is not generated during the period when dropout occurs. Further, the reset signal is generated as a pulse once every 1H with a sufficient interval from the gate signal (C) so that the pedestal enable signal is recognized by the next stage circuit.

Note that in the circuit shown in FIG. 16, the gate signal (C) is reduced to 1/2 due to the loading of the 1H counter 142 by the equalization pulse.
Measures similar to those shown in Fig. 13 were not taken to prevent H from shifting.

Further, the circuit in FIG. 16 can be replaced or shared with the HV separation circuit 145d in FIG. 21 and the circuit in FIG. 31, as in the case of FIG. 13.

In addition, in each of the embodiments of the pedestal level detection circuit 13 described above, the video signal has been described as being digitized, but the application is not limited to digital video signals, and can also be applied to analog video signals. The same applies.

Next, the dropout correction circuit 1 in FIG. 1(B)
9 will be explained. This one dropout correction circuit corrects the dropout of the digitized video signal output from the adder 12, but regarding the dropout of the vertical synchronization signal part, it is set to a level equal to the signal level of the vertical synchronization signal in advance. The configuration is such that dropout correction is performed by replacing it with a set correction signal.

The configuration of this dropout correction circuit 19 is shown in FIG. In this figure, the digitized video signal is supplied to the first selector switch 190, and the output of the switch 190 is passed through the first delay circuit 191 to the second delay circuit 1.
92 and 3.58 MHz BPF193.

Here, when the delay amount of the BPF 193 is set to d, the delay amount of the first delay circuit 191 is set to 1 H-d, and the delay m of the second delay circuit 192 is set to d. The output of the BPF 193 is sent to the adder 19 via a multiplier 194 with a coefficient of -2.
5 and is added to the output of the second delay circuit 192. The addition output of the adder 195 is sent to the second changeover switch 19.
6, and the output of the switch 196 becomes the output of the first changeover switch 19O. The first changeover switch 190 is connected to the dropout detection circuit 17 (FIG. 1(A)).
Switching control is performed by a dropout detection signal supplied from (see).

The address generation circuit 197 generates a field identification signal, horizontal address, and vertical address based on the horizontal synchronization signal and vertical synchronization signal supplied from the signal separation circuit 14, and generates a vertical synchronization level generation circuit based on these address information. A correction signal set to a level equal to the signal level of the known vertical synchronization signal is generated from 198 , and serves as an input to the second changeover switch 196 . In the switching signal generation circuit 199, a vertical synchronization period signal is generated during the generation period of the vertical synchronization signal based on the vertical address, and this vertical synchronization period signal becomes a switching signal for controlling the switching of the second changeover switch 196.

By the way, as shown in FIG. 18, the signal (A) before correction
A dropout occurs in the vertical sync pulse part of 1.
In this case, if you correct the dropout by replacing this part with the signal (B) from 1H before,
Because there is no horizontal correlation, the positional deviation of the vertical synchronizing pulse may occur in the corrected signal (C) (in Fig. 18, there is a 1/2H positional deviation between the Q-marked parts). ).

If the vertical synchronization pulse is misaligned in this way, there is a possibility that field errors will occur in subsequent video equipment. However, if vertical synchronization pulse dropout correction is prohibited, synchronization errors may occur.

Therefore, as shown in FIG. 17, when a dropout occurs in the vertical synchronization pulse portion, the signal level is equal to that of the vertical synchronization signal output from the vertical synchronization level generation circuit 198 instead of the signal 1H before. The level correction signal is
By supplying the signal to the selector switch 190 and replacing the digitized video signal with the digital video signal 5, dropout can be corrected without causing a positional shift of the vertical synchronizing pulse.

Note that in FIG. 17, dropout correction is performed using a signal from one day ago, but at this time, the phase of the chroma signal will become reversed if left unchanged. Therefore, the first
The circuit surrounded by the broken line in FIG. 7 inverts the phase of the chroma signal, thereby making it possible to colorize the dropout correction signal. Therefore, when dropout correction is performed only on a luminance signal (monochrome), when a signal 2H earlier (clock signal is in phase), etc., the circuit shown in the broken line is excluded. The address generation circuit 197, vertical synchronization level generation circuit 198, and switching signal generation circuit 199 may be included in the system controller 18, and replaced with 1H counter 183° gate circuit 182A, 1 frame counter 189° gate circuit 182B, etc. in FIG. You may.

The dropout detection circuit 17 in FIG. 1(A) has a level comparator configuration, and as shown in FIG. When it is detected that the signal level of the squared signal (B) of the envelope component of A) has become below a predetermined value, a dropout detection signal (C) is output. According to this configuration, the dropout detection circuit can be configured by simply adding a level comparator to the FM detection circuit 7, so that dropout detection can be reliably performed with a simple circuit configuration, and all detection operations can be performed. Since this is done digitally, stable characteristics can be obtained.

Note that there is a possibility that the detection output is disturbed by ringing that occurs in the output of the sum-of-squares circuit 72 (the area surrounded by a dashed line in FIG. 19(B)) due to a sudden change in the envelope. The dropout detection signal (D) is also output as a dropout section at n+ points before the signal level of the output signal (B) of 72 becomes below a predetermined value and at n2 points after the level becomes above a predetermined value. This allows subsequent corrections to be performed reliably. At this time, there is a possibility that ringing will occur due to the delay of the Hilbert transformer 70, so nl+02 is the delay circuit 70.
It is set equal to or larger than one delay time.

The signal separation circuit 14 in FIG. 1(B) separates and extracts control signals such as frame numbers and stop codes along with color burst signals, horizontal synchronization signals, vertical synchronization signals, etc. contained in the digitized video signal. For this signal separation, as shown in FIG. 20, a first reference level VTI1 for separating and extracting the control signal A, and a second reference level VTH2 for separating and extracting the synchronizing signal B
is set.

The configuration of this signal separation circuit 14 is shown in FIG.

In this figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum level of the digitized video signal within a predetermined period. The configuration of the minimum value detection circuit 2o will be explained in detail later. Based on each detection level of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the first. Second reference level VTI
-11°VTI-12 is set, and the reference level generation circuit 140 generates the first level VTHI by adding a constant value to the detected level based only on the detection level of the pedestal level detection circuit 13. Based on the detection levels of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the reference level generation circuit 141 generates an intermediate value between both levels as a second reference level VTI-12. The reference level generation circuits 142 and 143 generate the first. Second reference levels VTH1 and VT12 are generated.

Each output of the reference level generation circuits 140 to 143 is supplied to a selector 144, and this selector 144 selects the reference level generation circuit 140 when the synchronization establishment determination signal is supplied from the system controller 18, that is, when the synchronization is stable. The first .141 generated. second reference level V
TH1 and VTH2 are selected, and in other cases, that is, when the synchronization is unstable, the first. Select second reference levels VTH1 and VTI-12. Note that the system controller 18 determines whether or not synchronization is established by comparing a reference synchronization pulse based on an internal clock with the extracted synchronization pulse. The first one selected by the selector 144. The second reference levels VTI-11°VTI-12 are supplied to a signal detection circuit 145C, which detects these reference levels Vv1-11. Based on VTI-12
- Separate and extract the control signal A and synchronization signal B from the digitized video signal that has passed through the P F 145 a.

That is, in the signal separation circuit 14 having the above-described configuration, when the 1st day is stable, the pedestal level and the 1st. Based on the second reference level VTH1, VTI-12, or at the start of rotation of the spindle motor 24 or C
When synchronization is unstable, such as during LV disk search or scanning, the pedestal detection position is not determined and its value is not determined. , Vyl-1
The control signal A and the synchronization signal B are separated and extracted on the basis of 2. According to this, signal separation can be performed stably and reliably not only when synchronization is stable but also when synchronization is unstable. The separated synchronization signal B is input to the 1-(V separation circuit 145d, and the horizontal synchronization signal is separated by detecting a fall when the HS gate signal from the system controller 18 is at a high level. B is integrated in the HV separation circuit 145d, and the vertical synchronization signal is separated based on a predetermined reference level.
The fsc8PF145b outputs a color burst signal containing color signal components.

By the way, regarding the detection of the synchronization signal in the signal detection circuit 145c, as shown in FIG. 22, the digitized video signal is sampled at predetermined clock intervals (the X mark in the figure is the sample point), and the signal level of the synchronization signal is the standard. level VT
The synchronization signal is detected at the time when H2 is exceeded.

The configuration of this synchronization signal detection circuit is shown in FIG.

In this figure, a reference/level generation circuit 141 (or 14
3) reference level from VT)-12 and LPF145a
A filter reducer 1 inputs the digitized video signal that has passed through the
46 determines the level difference between the signal level of the video signal with respect to the reference level V t + (z) at each sample point, and detects the sample point where the video signal level is smaller than the reference level V TH2 as a synchronization signal. C) with the Q reducer 146
The output level difference signal is supplied to a delay circuit 147, a sign determination circuit 148, and a storage device 149 such as a ROM (read only memory). The delay circuit 147 has a delay amount equivalent to 1/0, and delays the level difference signal from the reducer 146 to pass the signal to the sign determination circuit 148 and the memory/memory head 14.
Supply to 9. The sign determination circuit 148 is in a state where the output Δ of the R extension circuit 147 is positive and the output B of the subtractor 146 is negative;
That is, the output of the delay circuit 147 A h< J^ Quasi-level VT
It is determined that the level difference is at the number point a immediately before exceeding I-12 and that the output B of the reducer 146 is already the level difference at the number point I immediately after exceeding the reference level VTL12, and a judgment signal is sent. is supplied to the storage device 149.

The storage device 1/19 stores in advance a time table as shown in FIG. , that is, the corresponding time information is output based on the level differences Δ and B between the two sample points a and b. Memory BE/149
The inputs .DELTA., B and the output are both 4-bit data, for example, and the first 1 bit of the 4 bits of input B is a sign bit and is expressed as a two's complement number.

The output of the storage device 149 "11-interval information is synchronized ft
This is the time difference between the point C when the signal level of @ exceeds the reference level VTH2 and the point a or b.
Even if the time point C does not temporally coincide with the sample point, the position of the falling edge of the synchronization signal can be accurately detected.

Next, the minimum value detection circuit 20 in FIG. 21 will be explained. In FIG. 25, the counter 200 counts the clock so that the first
It generates a pulse for a period of 1], and also generates a second Itl1 pulse for a period fυ, which is longer than the 1!11 period corresponding to 1]1. These period pulses are supplied to the selector 201, and in a steady state, the first period pulse is used as the first period pulse, and in an unsteady state where the disk rotation is unstable, such as when the spindle motor 240 rotation starts [, 1, CLV Zage, or scanning], the second period pulse is used.
The period pulses are selected and supplied to the register 202 and the averaging circuit 203. The comparator 204, which uses the digitized video signal output from the LPF 145a, inputs data B stored in the register 202 to its input data.
The data is compared every time a clock is generated, and the smaller data is supplied to the register 202. However, the comparator 204 is designed to stop its operation when dropout occurs. Since the register 202 is reset by the first or second period pulse supplied from the selector 201, the smallest filling from the previous reset time is stored in the register 202. The minimum value stored in the register 202 is loaded into the averaging circuit 203 at each occurrence of the first or second period pulse, and the averaging circuit 203
The minimum values of the above detection periods are averaged and finally output as the minimum value.

In such a configuration, since the minimum value of the video signal normally appears during the synchronization signal period, a period of 1] is set as the detection period (first period pulse generation interval), but the rotation of the spindle motor 24 At startup and CLV
- In an unsteady state such as reach or scan, the length of the 1F1 period fluctuates because the rotation of the disk is not stable.

At this time, if the minimum arrow detection is performed at a normal interval based on the first period pulse, there will be a case where the same 1v1 signal is not included within the interval. Therefore, in an unsteady state, by using a second period pulse generated at fσ for a period longer than the period equivalent to one day, the synchronization signal will be included within the detection period, so the minimum value level will be reliably By detecting this, it is possible to reduce the fluctuation of 1 iti in the minimum value level.

In addition, when a dropout occurs, the signal level of the synchronization signal may temporarily become smaller than J:, but by stopping the operation of the comparator 204 and prohibiting the detection operation during the dropout period, This makes it possible to prevent erroneous detection of the minimum value.

In addition, the counter 200 is activated by the dropout detection signal.
Since the counter 200 starts counting the predetermined period again after the dropout, even if the synchronization signal part is lost due to a dropout, the level of the synchronization signal part will be reliably detected before the next period pulse is generated. can be done.

The clock generation circuit 21 in FIG. 1(B) generates 4 fsc (fsc is the subcarrier frequency) based on the reference horizontal synchronization signal from the reference signal generator 22 or the horizontal synchronization signal or color burst signal from the signal separation circuit 14. It generates a clock of 4Nfsc (for example, 12fsc) and has a PLL (phase locked loop) circuit configuration. 4fsc and 4 generated here
The NfsC clock is used as a clock for digital signal processing, and the sampling clock of the A/D converter 4 and the signal processing clock up to the video LPF 10 are set to 4Nfsc, and the clock is set to 4fsc from the output of the video LPFIO.
Downsample to c.

The configuration of the clock generation circuit 21 is shown in FIG.

In this figure, a phase comparator 210 that uses a color burst signal as a comparison reference input is connected to a sampling pulse generation circuit 21.
1, the sampling pulses CK+, C
Phase comparison is performed in response to K2. Note that when locking the PLL to the reference horizontal synchronization signal or the horizontal synchronization signal, the phase comparator 210 is not used, and another phase comparator (not shown) is used to lock the PLL to one of these signals at 2fs.
The phase is compared with the fH signal obtained by dividing c by 1/455, and the output thereof is input to the LPF 212.

Hereinafter, only the case of locking to the color burst signal will be explained. The comparison output of the phase comparator 210 is LPF2
The signal is supplied to the D/A converter 213 via the signal line 12, where it is converted into an analog signal and becomes a control signal for the VC○ (voltage control excavator) 214. ■The oscillation frequency of CO214 is 12fsc
The clock is set to 12fsc, and is output as is as a clock of 12fsc, and the frequency is divided to 4fsc by a 1/3 frequency divider 215. This clock 4fsc is outputted as is, serves as the sole power of the sampling pulse generation circuit 211, and is further divided into fSC by 1/2 frequency dividers 216 and 217, and becomes a comparison input of the phase comparator 210. The sampling pulse generation circuit 211 is supplied with the gate pulse generated by the gate pulse generation circuit 218 as an external power, and therefore the phase comparator 210 is supplied with the sampling pulses CK+ and CK2 only during the generation period of the gate pulse. become. The gate pulse generation circuit 218 synchronizes with 4t'sc based on the horizontal synchronization signal and generates a gate pulse (B) only during a period corresponding to the central portion where the amplitude of the color burst signal (A> is constant), as shown in FIG. occurs.

In the phase comparator 210, as shown in FIG.
The color burst signal becomes the input power of the adder/subtractors 219 and 220, and each addition/subtraction output passes through delay circuits 221 and 222 and becomes the input power of the adder/subtractors 219 and 220, and is divided by the divider 223. The addition/subtraction (±) control of the adders/subtractors 219 and 220 is performed using the clock pulse fsc shown in FIG.
Based on (B), addition is performed at sample point S+, 82, and subtraction is performed at sample points 83 and 84. However, when a track jump is performed during still image playback, etc., the phase of the color burst signal changes by 180°, so the clock pulse fs changes every time a track jump occurs.
Maintain PLL lock by inverting the phase of c(B). This is controlled by the 1/2 frequency divider 2 by the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).
This is done by controlling 17.

Further, the sampling pulse generation circuit 211 is composed of a D-type flip-flop, and has a sampling clock CK+
, CK2 have the same frequency as 4fsc and have 1/2 of the same frequency and are in opposite phases to each other, and only when the gate pulse is at a high level, are the delay circuits 221.2
22 clock.

As a result, when the amplitude of the color burst signal (A) is Δ, ΣΔsinθ is derived as the output of the delay circuit 221, ΣA CO3θ is derived as the output of the delay circuit 222, and tanθ is derived as the output of the divider 223. Ru. Then, this split cylinder output tanθ is converted to tan-' circuit 22.
4, the phase difference θ can be obtained.

That is, the phase difference θ in the phase comparator 210 can be calculated from the following equation.

θ=tan' (Σ[(Sz -33)/(S2
SJ)]) Here, S+=A-sinθ 52=A-
CO3θS3 = -A -sinθ SJ = -A -
cos θ By the way, as is clear from the above equation, if the amplitude A of the signal (A) to colorverse 1 is not constant within 1H, there will be some error in the detected phase difference θ and the loop characteristics will change due to changes in the PLL loop gain. Change will occur.

However, in the clock generation circuit 21 described above, 81 to
Sampling pulse CK+ to find $4.

By applying a gate to CK2, phase comparison is performed only during a period in which the amplitude A of the color burst signal (A) is constant, so that the above-mentioned problem does not occur.

In the above configuration, phase comparison is performed only in the central portion of the color burst signal by applying a gate to the sampling pulse, but it is of course possible to apply a gate to the color burst signal itself. . In this case, since it is a digital gate, only the central part of the color burst signal can be extracted more accurately than an analog switch or the like. Furthermore, in FIG. 26, the arrangement relationship between the LPF 212 and the D/A converter 213 may be reversed.

In FIG. 1(B), a reference signal generator 22 includes a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronization signal. The spindle servo circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronization signal from the reference signal generator 22 and the horizontal synchronization signal from the signal separation circuit 14. The chroma inversion circuit 25 adjusts the chroma (color) as necessary to maintain color framing even during special playback such as still playback and slow playback.
A phase inversion of the signal is performed.

The configuration of this chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is sent to a one-day delay circuit 270.
1 elevator 271. After the signal level of the output of the adder 271 is halved by the level adjustment circuit 272,
It is supplied to a subtracter 273. The subtraction output of the subtracter 273 is supplied to the adder 275 via a phase linear acyclic digital BPF 274, and the addition output of the adder 275 is as follows.
The signal is supplied to the changeover switch 276.

The delayed output of the delay circuit 270 is sent to the subtracter 273 and BPF2.
The signal is supplied to a delay circuit 277 having the same delay ω as 74, and is also supplied to an adder 271 via a one-day delay circuit 278. The delayed output of the d detour 277 is supplied to an adder 275 and a changeover switch 276. The changeover switch 276 is appropriately switched depending on the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).

With this configuration, a 2.3-line correlation rectangular filter is configured, and the subtracted output of the subtracter 273 is transmitted to the 1-day delay circuit 2.
With respect to the delayed output of 70 (Y is assumed to be 10), the chroma signal (-2G) has an opposite phase and twice the level. After unnecessary components are removed from this chroma signal by the BPF 274, the delay output is adjusted by the delay circuit 277 (
Y+C) is added by an adder 275, and a digitized video signal (b) having a chroma signal inverted with respect to the delayed output (a) of the delay circuit 277 is obtained as an addition output. For special playback such as stay and slow, selector switch 27
Color framing can be maintained by switching the chroma inversion control signal from the system controller 18 of FIG. 1(B).

In FIG. 1B, the output of chroma inversion circuit 25 is supplied to video processing circuit 38. In FIG. The video processing circuit 38 performs character insertion, MCA code suppression, squelch, etc. The digitized video signal passed through the video processing circuit 38 is written into the buffer memory 39 using a 4fsc clock generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal.

Reading from the buffer memory 39 is performed using a 4fsc reference clock generated by the reference signal generator 22. In this way, by reading data from the buffer memory 39 using a stable reference clock that is unrelated to the reproduced signal, jitter in the reproduced signal can be absorbed, eliminating the need for so-called tangential servo or color correction circuits. Become. The digitized video signal read from the buffer memory 39 is converted into an analog signal by a D/A converter 340, and is supplied to the output terminal 42 via the LPF 41.

The system controller 18 has the following main functions. That is, 1. Various nervo systems are controlled from 1 to 1 in response to commands from an operating section such as a panel switch or remote control, and a date signal from a servo system, thereby causing the player to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generate signals for compositing frame numbers, chapter numbers, etc. onto the screen.

4. Synchronize the internal counter with the horizontal synchronization signal and vertical synchronization signal, and decode the output of the counter to generate various timing signals.

5. Perform i and If i of the PLL loop for clock generation. A specific configuration for realizing the fourth function among the above main functions will be described below.

In Figure 31, the horizontal synchronization signal (H8) is converted to data (D
) input and a clock signal of 4fsc (C
K) A D-type flip-flop 180 is provided as an input, and the Q output of this flip-flop 180 is NAN.
It will become the sole strength of D Gate 181B. NAND gate 18
1B has the horizontal synchronization signal supplied via the inverter 181A as another input, and its output is the 1H counter 18.
3 load (L) input. The gate circuit 182A is
The output of the one-day counter 183 is decoded to generate the HS gate signal in a predetermined period and inputted to the HV separation circuit 145d in FIG. 21, and a clock HCK having a frequency of f+ synchronized with the horizontal synchronization signal is generated. . The HS gate signal is used in the HV separation circuit 145d to detect the fall of the horizontal synchronization signal excluding the equalization pulse and to separate the horizontal signals. In the initial state, the HS gate signal is always at a high level, loads the 1H counter 183 at the falling edge of the synchronizing signal, and thereafter remains at a high level only for a predetermined period so that the falling edge of the horizontal synchronizing signal is detected every day. . In the initial state or for some reason, if the 1H counter 183 is loaded due to the fall of the equalization pulse and a 1/2H shift occurs, the 11-1 counter 183 will not be loaded after the vertical blanking period. , the system controller 18 detects that this state has occurred, and sets the HS gate signal to a high level again. Note that the l-IV separation circuit 145d generates a pulse of a predetermined width based on the fall of the horizontal synchronizing signal, and outputs this as a horizontal synchronizing signal. clock)
-10 has a duty ratio of 50%, with the fall of the synchronization signal as the starting point, and the level is high in the first half and low in the second half.
This is the signal. The gate circuit 182A further generates various timing signals within 1H and supplies them to each circuit.

The positive polarity vertical synchronization signal (VS) becomes each clock input of D-type flip-flops 184 and 185.

The D-type flip-flop 184 receives the VS gate signal output from the gate circuit 182B as a data (D) input, and when the vertical synchronization signal rises while the signal is at a high level, its Q output goes to a high level, Φ The output becomes a low level, and this state is maintained until the reset signal becomes a low level. When the reset signal becomes a low level, the Q and Φ outputs are inverted.

The D-type flip-flop 185 receives the clock l-1GK output from the gate circuit 182A as data input, and determines whether the vertical synchronizing signal is from field 1 or field 2.
In field 1, the clock) (in field 1, the rising edge of the vertical dosing signal arrives when CK is low level, so the Q output goes low level, the Φ output goes high level, and the field In 2, when the clock HCK is at a high level, the rising edge of the vertical synchronization signal arrives, so the Q output becomes a high level and the ○ output becomes a low level.The Q output of the flip-flop 184 is used as data input, and the clock HCK
The D-type flip-flop 186 uses the clock input as the clock input and the Q output of the flip-flop 185 as the clear input.
When the Q output of the flip-flop 184 becomes high level after field 2, the Q output becomes high level at the rising edge of clock HCK, and during field 1, the Q output remains low level.

The Q and Q outputs of the D-type flip-flop 184 are J.

J- with K input, clock HGK as inverted clock input, and d output of flip-flop 185 as clear input.
The flip-flop 187 is D when field 1
When the Q output of the type flip-flop 184 becomes high level, the Q output becomes high level at the fall of the clock HCK.
During field 2, the Q output remains at a low level.

0 type flip-flop 186 and a NOR gate 188 that makes each Q output of the flip-flop 187 into J-
The next stage 1 frame counter 189
is loaded and the D-type flip-flop 7184 is reset. Here, the reason why a load pulse is created using another 70 flips for each field is to send a sufficiently wide load pulse to 18 one-frame counters in any field. 1 frame counter 18 counts clock HCK 52
It is a quinary counter and is loaded with the clock) - ICK when the output of the NOR game 1-188 is at a low level.
The D-type flip-flop 1 is loaded so that the number loaded in field 2 is 263 more than that in field 1.
It is controlled by the 0 output of 85.

The gate circuit 182B decodes the output of the one frame counter 189 and generates the above-mentioned S gate signal in a predetermined period, and also generates a timing signal of H units within one frame and supplies it to each circuit.

Next, the fifth of the above-mentioned five functions of the system controller 18, ie, the function of controlling the clock generation PLL loop, will be explained based on the flowchart of FIG. 32. As mentioned above, this PLL has two phase comparators: one for locking to the reference horizontal synchronizing signal or the reproduced horizontal synchronizing signal, and the other for locking to the color burst signal. The configuration is such that three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal at the input section of the comparator and by switching the phase comparator itself. In FIG. 32, in an initial state such as immediately after the power is turned on or when the spindle motor is forcibly accelerated, the reference signal generator 22 (FIG. 1(B)), which is the reference for the spindle servo,
), the PL loop operates to lock to the reference horizontal synchronization signal (step 1).It is determined that the lock is to the reference horizontal synchronization signal (step 2), and the horizontal synchronization signal is obtained from the reproduced video signal. When the computer starts working, the loop is switched to the reproduction horizontal synchronization signal (Step 3). At this time, if it is determined that locking is not possible, step 4)
, return to step 1 and loop back to the reference horizontal synchronization signal. If it is determined in step 4 that it is locked to the playback horizontal synchronization signal, the presence or absence of a color burst signal is detected in step 5), and if there is no color burst signal, the process returns to step 4 and the lock is maintained to the playback horizontal synchronization signal. . This state occurs during the vertical blanking period for both black and white discs and color discs. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). Here, if it is determined that the color burst signal cannot be locked (step 7), the process returns to the loop of the reproduced horizontal synchronizing signal in step 3, but if it can be locked, the color burst loop state is maintained. However, at the same time, the synchronization with the playback horizontal synchronization signal must be monitored (Step 8). If either the lock with the color burst signal or the lock with the playback horizontal synchronization signal is lost, it is assumed that the lock is lost and the playback horizontal synchronization signal is looped. (Step 3)
Return to At this time, if the loop of the reproduced horizontal synchronizing signal fails to lock onto the reproduced horizontal synchronizing signal (step 4), the loop is further returned to the loop of the reference horizontal synchronizing signal (step 1).

Note that the determination of No in step 4.7 indicates that it is not possible to lock within the predetermined period when passing for the first time.
When passing for the second time or later, it indicates that it is not locked.

This system has been explained above while showing the specific configuration of each circuit, but the point of this system is that all signal processing is performed digitally between the A/D converter 4 and the D/A converter 40. It has great characteristics. In this way, by digitizing the signal, it is possible to make it multi-functional, such as converting the monochrome dropout correction signal to color, chroma inversion, increasing the accuracy of Y-C separation by introducing frame memory, or increasing the accuracy of Y-C separation by introducing frame memory. Still image playback becomes easier.

In FIG. 1(B), the circuits are arranged in the order of adder 12, one dropout correction circuit, chroma inversion circuit 25, video processing circuit 38, and three buffer memories, but the circuits are not limited to this arrangement. For example, as shown in FIGS. 33(A) and 33(B), the order of "one dropout correction circuit + chroma inversion circuit 25", "video processing circuit 38" and "buffer memory 39" is Replacement is possible. However, since writing and reading of the buffer memory 39 are asynchronous, [buffer memory 39]
If there are two other signals after the one shown in FIG. 33 (B), it is necessary to resynchronize or delay the control signals and timing signals for the other two signals. In addition, [video processing circuit 3
8" is followed by "dropout correction circuit 19 + chroma inversion circuit 25" (in the case of FIG. 33(A)),
When a character is inserted by the video processing circuit 38, a control signal is required to inhibit the dropout correction circuit 19 from performing dropout correction in the character portion.

Furthermore, as shown in FIG. 34, R, G, and B separation can also be performed digitally, and the RGB separation circuit
3 is converted into an analog signal by a D/A converter 44 and sent to each analog output terminal 4 via an LPF 45.
By supplying signals to 6R, 46G, and 46B, if these terminals are connected to a monitor TV (television) with RGB input, there is no need to use the RGB separation circuit in the TV, which improves the image quality. It will be possible to achieve this.

Furthermore, when using a digital TV that can input RGB as it is digitized, the digital signals separated by the RGB separation circuit 43 are directly input to each digital output terminal 47R, 47G, without going through a D/A converter. 47B.

In this RGB separation, in this system, the clock of the A/D converter 4 is set to 4Nfsc (N is an integer of 2 or more), and the 4fsc clock is locked to the color burst signal of the video signal, so the RGB separation is performed. (demodulation) can be easily performed. The case of demodulating using R-Y and B-Y signals will be explained below.1. Demodulation can be similarly performed using the Q signal.

In the NTSC system, the phase of the color signal is as shown in FIG. 35, which is quadrature two-phase modulated and frequency multiplexed with the luminance signal. The relationship between the R, G, and B signals and the luminance signal Y is shown in the following equation.

Y= 0.3OR+ 0.59 G+ 0.11 B・
(1) Also, the color signal C in the video signal is expressed by the following equation.

R−Y B−Y □, = −co sωCt + −s r nωc
t1.14 2.03 ・・・・・・(2) −I cos(ωct+33°) + Q 5in(ωct+33°) −−−−・−(3
) where ωC is the angular frequency of the color carrier and Q)(=
2πx 3.58 MH7.

When the phase of the 4fsc sampling frequency is locked to the color burst signal at Oo, Fig. 35 and (2) are obtained.
From the formula, each Zamburu point is ±(R
-Y)/1.14, ±(BR)/2.03. Also, from equations (1) and (2), it becomes 1.174', and 8 R, G, and 8 signals are obtained. Furthermore, I.

To obtain the Q signal, ±33″ for the color burst signal.
Alternatively, the phase may be locked at ±57°.

From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst signal.

In the above embodiment, the case where the system is applied to an NTSC video disc player has been described, but this system is applicable to VTR playback side signal processing, PAL, SEC
It can also be applied to AM video disc players and the like.

As explained above, according to the present invention, a phase linear acyclic digital filter is placed in the front stage, a cyclic digital filter is placed in the latter stage, and the sampling frequency is lowered in the latter stage. The influence of aliasing components due to downsampling is suppressed to a minimum by the high-frequency attenuation characteristics of the phase-linear acyclic digital filter at the front stage, and the phase compensation is determined only by the recursive digital filter at the rear stage, making analog processing Correspondingly, the phase characteristics of the recorded information can be compensated well. In addition, by lowering the ringing frequency, it becomes possible to have more time and reduce the hardware group.

[Brief explanation of drawings]

1 (A>, (B) is a block diagram showing an embodiment of the video signal reproducing device according to the present invention, FIG. 2 is a block diagram showing the specific configuration of the digital BPF in FIG. 1 (A>), FIG. 3 is a block diagram showing an example of the configuration of the video LPF in FIG. 1(B), FIGS. Figure 5 is the third
6 to 8 are block diagrams showing specific configurations of the FIR filter, downsampling circuit, and IIR filter in FIG. 3, and FIG. 9 shows other configurations of the video LPF. 10 is a block diagram showing another configuration of the bit reduction process in FIG. 1(8), and the eleventh factor is a block diagram showing an example of the configuration of the pedestal level detection circuit in FIG. 1(B). , FIG. 12 is an operation waveform diagram of each part in FIG. 11, and FIG. 13 is a block diagram showing the specific configuration of the falling detection circuit, rising detection circuit, timing signal generation circuit, and sample period signal generation circuit in FIG. 11. , FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit, FIG. 15 is an operation waveform diagram of each part in FIG. 14, and FIG. 16 is a diagram of the falling detection circuit and timing signal generation circuit in FIG. 14. FIG. 17 is a block diagram showing a specific configuration of the dropout correction circuit in FIG. 1(B), FIG. 18 is a waveform diagram for explaining the circuit operation of FIG. 17, Figure 19 is a waveform diagram for explaining the circuit operation of the dropout detection circuit in Figure 1 (A>), and Figure 20 is the relationship between the video signal and the reference level in the signal separation circuit in Figure 1 (B). Waveform diagram showing 2nd
FIG. 1 is a block diagram showing the specific configuration of the signal separation circuit, FIG. 22 is a waveform diagram for explaining the operation of the signal detection circuit in FIG. 21, and FIG. 23 is a block diagram showing the specific configuration of the signal detection circuit. 24 is a diagram showing an example of the time table stored in the ROM in FIG. 23, FIG. 25 is a block diagram showing a specific configuration of the minimum value detection circuit in FIG. 21, and FIG. Block diagram showing the specific configuration of the clock generation circuit in FIG. 1(B), No. 27
The figure is a waveform diagram of each part in FIG. 26, FIG. 28 is a block diagram showing the specific configuration of the phase comparator in FIG. 26, and FIG.
The figure is a waveform diagram for explaining the circuit operation of Figure 28.
Figure 0 is a block diagram showing the specific configuration of the chroma inversion circuit in Figure 1 (B), and Figure 31 shows the configuration of some hardware for performing the prescribed functions of the system controller in Figure 1 (B). The block diagram shown in FIG. 32 is a flowchart of predetermined functions of the controller, and FIG. 33 (
A). (8) is a block diagram showing a modified example of this system, No. 34
The figure is a block diagram showing another modification, and FIG. 35 is a block diagram showing another modification.
FIG. 4 is a phase characteristic diagram of a color signal used to explain the principle of RGB separation, and FIG. 36 is a waveform diagram of a signal at each sample point. Explanation of symbols of main parts 2...Analog LPF 4...A/
D converter 6... Digital 8PF 7... FM detection circuit 10... Video LPF 13... Pedestal level detection circuit 14
... Signal separation circuit] 7 ... Dropout detection circuit 18 ...
... System controller 19 ... Dropout correction circuit 21 ... Clock generation circuit 22 ... Reference signal generator 24 ... Spindle motor 25 ... ... Rima inversion circuit 38 ... Video processing circuit 39 ... Buffer memory 40 ... D/A converter

Claims (1)

[Claims] A video filter circuit that extracts only the baseband component of a video signal from a digitized video signal obtained by FM detection of a digitized FM video signal, the phase of which is a pre-stage that removes a carrier wave component included in the digitized video signal. It includes a linear acyclic digital filter and a subsequent cyclic digital filter that compensates for the phase characteristics of the digitized video signal, and has a subcarrier frequency of f_s.
_c, the clock frequency of the acyclic digital filter is set to 4Nf_s_c (N is an integer of 2 or more), and the output of the acyclic digital filter is set to 4f_s_c.
A video filter circuit characterized in that the cyclic digital filter is operated at a clock frequency of 4f_s_c by downsampling to a clock frequency of _s_c.