JPS62142412A - Digital signal processing circuit for fm video signal - Google Patents

Abstract

PURPOSE:To eliminate waveform distortion after FM detection by group delay caused by an analog filter inserted before A/D conversion stage by setting group delay characteristics of an analog filter and a digital filter complementally. CONSTITUTION:FM video signals are supplied to an analog LPF 2 through an input terminal 1, and after extracting necessary band component in the LPF 2, supplied to an A/D converter 4, and outputted digitalized FM video signals are supplied to a digital BPF 6. The digital BPF 6 extracts only component necessary for detecting video signals from A/D conversion output including FM aural signals and supplies to an FM detection circuit 7 of next stage. In such a case, the digital BPF 6 has group delay characteristic complementary to group delay characteristic of the analog LPF 2. By using digital BPF 6 having such group delay characteristic, group delay (phase distortion) caused by the analog LPF 2 before A/D conversion is corrected, and can be supplied to an FM detecting circuit 7 in the state devoid of group delay.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an FM modulated video signal (hereinafter referred to as FMl!!).
X! Regarding digital signal processing circuits for image signals,
In particular, the present invention relates to a circuit that digitally reproduces a video signal that has been FM modulated and recorded on a recording medium.

In a video disc player that plays back a recording medium, such as a video disc, on which a video signal is FM modulated and recorded, signal processing of the FM modulated video signal read from the disc has conventionally been done in an analog manner. It was common to do so.

However, when considering the possibility of converting a circuit into a TC (integrated circuit), it is extremely advantageous to perform signal processing digitally rather than analogously, and it is also easy to realize multiple functions in the signal processing process. Furthermore, higher image quality can also be achieved.

By the way, when performing digital signal processing, the FM video signal read from the disk is A/D converted, but an analog LPF (low pass filter) is used before the A/D conversion stage to prevent so-called aliasing. ) is inserted. However, in this analog LPF, if the aliasing is attenuated to the extent that it can be ignored, the group delay cannot be ignored, and this group delay becomes F
This will appear as waveform distortion after M detection.

Group 1 Natsumi 1 The present invention has been made in view of the above-mentioned points, and eliminates waveform distortion after FM detection due to group delay caused by the analog filter inserted before the A/D conversion stage, and enables good signal processing. An object of the present invention is to provide a digital signal processing circuit for FM video signals that can perform the following.

FMI according to the invention! ! l! The digital signal processing circuit for image signals includes an analog filter that cuts a predetermined band component including the high frequency range of the FM-modulated video signal, and an A/D (A/D) that digitizes the output of this analog filter.
Equipped with an analog/digital) converter and a digital filter that extracts only the components necessary for detecting the video signal from the output of this A/D converter, the group delay characteristics of the analog filter and digital filter are set complementary. The structure is as follows.

叉-”L-separate Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1(A), an FM video signal read from a recording medium such as a video disk is supplied to an analog 1P (low-pass filter) 2 via an input terminal 1, and only the necessary band components are filtered out by the LPF 2. After being extracted, △/D
(analog/digital) converter 4. A/
The digitized "M" video signal output from the D converter 4 is supplied to a digital BPF (Pandobass Filter) 6. This digital BPF 6 converts the video signal from the A/D conversion output that also includes the FM audio signal. Only the components necessary for detection are extracted and supplied to the next stage FM detection circuit 7.

The analog L P F 2 is provided to prevent so-called aliasing, in which an unnecessary signal component overlaps with a signal component to be extracted during Δ/D conversion, causing a type of distortion. That is, F which is the input of the LPF2 concerned
In FIG. 2(A) showing the spectrum of the M video signal, ωs1. 'Sampling angular frequency during LA/D conversion, 8 is the required video signal component, B is 1 during A/L conversion.
This is an unnecessary signal component that causes rearing, and
In the 1G LPF 2, the unnecessary signal component B is removed and only the necessary signal component A is extracted using the amplitude characteristics shown in FIG. 2(B). In the LPF2, if the attenuation is set to a level where aliasing can be ignored,
Group delay cannot be ignored, and this group delay appears as waveform distortion after FM detection.

In order to correct this group delay, the digital BPF 6 is
In contrast to the group delay characteristic of the analog IPF 2 as shown in FIG. 2(C), it has a group delay characteristic as shown in FIG. 2(D). In other words, digital BPF6 is analog LPF2
It has complementary group delay characteristics to the group delay special case of . In the digital BPF 6, for example, as shown in FIG. 3A, delay circuits 60+ to 60n are connected in series to each other to delay one clock, and the input signal of the delay circuit 60+ and each output of the delay circuits 60+ to 60n are connected in series. An FIR filter (acyclic digital filter) is made up of multipliers 61o to 61n that multiply a signal by a multiplication coefficient ko-kn, an adder 62 that adds the outputs of each multiplication, and a latch circuit 63 that latches the added output. Multiplier 61
Desired amplitude characteristics and group delay characteristics can be obtained by appropriately selecting each of the multiplication coefficients ko-kn from o to 61n. Therefore, by using a digital BPF 6 having group delay characteristics as shown in FIG. 2(D), the A/
The group delay (phase distortion) caused by the analog LPF 2 before D conversion can be corrected and the signal can be supplied to the FM detection circuit 7 in a state where the group delay is eliminated.

The FM detection circuit 7, for example, as shown in FIG. 1(A),
A Hilbert converter 70 that performs Hilbert transform on a digitized FM video signal, a delay circuit 71 that delays the digitized FM video signal by n ripple periods, and a Hilbert converter 70 that converts each output signal of the converter 70 and delay circuit 71 into Hilbert 1, respectively.
a square-sum circuit 72 that multiplies and adds; a delay circuit 73 that delays the output signal of the delay circuit 71 by one sample period;
It consists of a multiplier 74 that multiplies the output signals of the delay circuits 71 and 73, and a divider 75 that divides the output signal of the multiplier 74 by the output signal of the sum of squares circuit 72. The Hilbert transformer 70 is composed of a transversal filter.

Also, the delay time of the delay circuit 71 is from Hilbel 1 to converter 7.
This corresponds to a delay time of 0. The FM detection circuit 7 having such a configuration is disclosed in Japanese Patent Application No. 59-262 by the applicant of the present application.
It was proposed in No. 481.

In FIG. 1(B), in the video L P F 10 to which the detection output of the FM detection circuit 7 is supplied, only the baseband component of the video signal is extracted from the detection output. The cutoff frequency of the video LPFIO is set to, for example, 4.2 MH1 in the case of the NTSC system. FIG. 3B shows the configuration of an example of the video LPF 10, and this video LPF 10 has a 4Nfsc (N is an integer of 2 or more).
a front-stage phase linear acyclic digital filter (FIR filter) 100 that operates at a clock frequency of a downsampling circuit 101 that downsamples the output of 4fsc to a clock frequency of 4fsc;
It is comprised of a subsequent stage cyclic digital filter (IR filter) 102 which operates at a clock frequency of fsc and compensates for the phase characteristics of the digitized video signal.

FIGS. 4(A) to (C) show each part (A) in FIG. 3B.
) to (C) are shown. The FM detection output (A) includes not only the baseband video signal but also its second harmonic component, and by passing through the FIR filter 100, the baseband video signal (B
) will be derived. This baseband video signal (B) is processed at 4NfS by the downsampling circuit 101.
The clock frequency of C is downsampled to a clock frequency of 4 fsc. The spectrum after downsampling is the same as that in Figure (B). in this way,
By lowering the sampling frequency, time margin and hardware quality can be reduced. In addition, FIR filter 1
By passing through 00, the band of the digitized video signal becomes narrow to about 4°2MH7, so there is no problem even if the sampling frequency is lowered. The baseband video signal (B) is subjected to IIR filter 10 after downlinking.
Compensation of phase characteristics is performed in step 2. The spectrum (C) after phase compensation is also the same as that in Figure (B).

In the case of video disks, etc., the signal processing system for the playback signal has conventionally been analog-based, so the phase of the video LPF is changed when recording information, assuming that the phase of the analog-designed video LPF will rotate. Information is recorded by mixing the distortion in the opposite direction by inversely compensating for the distortion. Therefore, when playing back a video disc with such a recording format and digitally processing the playback signal, it is necessary to further compensate for the inverse compensation valve for phase distortion during recording, and compensation for this phase characteristic is necessary. is IIR filter 1
It will be held in 02. FIG. 5 shows the phase characteristics of the IIR filter 102.

6 to 8 show examples of specific configurations of the FIR filter 100, the downsampling circuit 101, and the IIR filter 102. First, in Figure 6,
The FIR filter 100 includes delay circuits 1031 to 103n connected in series to each other for delaying one clock;
Input signal of delay circuit 1031 and delay circuits 1031 to 1
Multipliers 1040 to 104n that multiply each output signal of o31 by a multiplication coefficient ko-kn, an adder 105 that adds each multiplication output, and a latch circuit 106 consisting of a D-type flip-flop or the like that latches the added output. The clock frequency of the delay circuits 1031 to 103n and the latch circuit 106 is set to 4Nfsc. As shown in FIG. 7, the down-resampling circuit 101 is constituted by a latch circuit 107 consisting of a D-type flip-flop or the like, and its clock frequency is set to 4 fsc.

As a result, the data input to the latch circuit 107 is N
- Output every other item.

Moreover, as shown in FIG. 8, the IIR filter 102
A multiplier 108o that multiplies the input signal by a multiplication coefficient ko, an adder 109 that uses this multiplication output as one addition n input, a latch circuit 110 consisting of a D-type flip 70 tube, etc. that latches this addition output, and an addition Delay circuits 1111 to 111n connected in series sequentially delay the addition output of the circuit 109 by one clock, and these d delay circuits 111+ to 1.
A multiplier 1 that multiplies each output of 11n by a multiplication coefficient of -kn.
081 to 108n, and the clock frequency of the latch circuit 110 and delay circuits 1111 to 111n is 4f.
It is set to sc. In this circuit configuration, by appropriately setting the zero coefficients ko to kn of the multipliers 1080 to 108n, the phase characteristics shown in FIG. 5 can be obtained.

In the video L P F 10 described above, by using the phase linear FIR filter 100 in the front stage, all phase compensation can be determined only by the IIR filter 102 in the latter stage, and the amplitude characteristics can be changed without changing the phase characteristics. It will be possible to adjust.

Note that downsampling is performed before the IIR filter 102, but this is because the IIR filter 102
This is due to the fact that the entire operation must be completed within a clock period. IIR filter 102 down 1j combing
For the reasons mentioned above, pipeline processing is not possible and the number of operations must be reduced or high-speed elements must be used, but there are limits to this. On the other hand, if downsampling is performed before the ITR filter 102, the clock cycle will naturally become longer, and if the number of operations increases accordingly, more accurate characteristics can be obtained and stability will also increase.

In the video LPF 10 configured as described above, the front stage F
The IR filter 100 is operated with a 4Nfsc clock, and its output is processed by a downsampling circuit 101 at 4fsc.
However, as shown in FIG. 9, the downsampling is performed before the arithmetic circuit in the FIR filter 100', and the clock after the arithmetic circuit is downsampled to the 4-clock.
It is also possible to configure it to operate with the fsc clock. Nowadays, downlink ring circuit 10
1 is not necessary.

That is, in FIG. 9, the FIR filter 100' includes delay circuits 1121 to 112n connected in series that delay one clock, and input signal and delay circuit 1.
latch circuits 1130 to 113n consisting of D-type flip-flops that latch each output signal of 121 to 112n;
Multipliers 114o to 114 multiply each latch output of these latch circuits 1130 to 113n by multiplication coefficients ko to kn.
n, an adder 115 that adds these formwork outputs, and a latch circuit 116 consisting of a D-type flip-flop that wraps this addition output, and delay circuits 1121 to 11.
2n is performed with a 4Nfsc clock, the next stage latch circuits 1130 to 113n are performed in one 4fsc clock, and the final stage arithmetic circuit (multipliers 1140 to 11
4n, adder 115 and latch circuit 116)
The configuration is such that it is performed using the fsc clock.

In the FTR filter 100' having such a configuration, the calculation is 4f.
Since it is performed using the sc clock, unnecessary calculations are omitted,
In addition, the number of calculations can be increased because one cycle is longer, and the FIR filter 1 with the above-mentioned configuration is relatively
This means that the circuit scale can be reduced compared to 00.

Note that in order for the FIR filter to have a phase linear characteristic in FIGS. 6 and 9, the coefficients Ko to Kn must be symmetrical about the center (Ko = Kn, + = Kn-+, - −).

Referring again to FIG. 1B, the digitized video signal that has passed through the video LPF 10 passes through the de-emphasis circuit 11 and is then passed through the adder 12, pedestal level detection circuit 13, and signal separation circuit 14, which constitute pedestal clamp means. supplied to

By the way, when performing digital signal processing, it is clear that a smaller number of quantization bits per word n (bit/word) is advantageous in designing a circuit.

However, when considering the FM detection output, the output level is constant in the steady state of the disc player, but there are irregularities such as the rise of rotation of the spindle motor 24, search and scan during CLV (Constant Linear Velocity) disc playback. In a steady state, the DC component of the video signal changes significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle motor circuit 23 will not be able to lock it, and the clock generation circuit 21 will also be unable to synchronize, and the steady state will never be achieved. Therefore, even in an unsteady state, the synchronization signal cannot be detected. It needs to be detectable. To do this, it is necessary to set the unsteady state to 51 and set the number 1 to number n.

Therefore, at least the number n of bits from the input of the signal separation circuit 1/I, that is, to the output of the de-emphasis circuit 11, is set to have a dynamic range that is sufficient even if the pedestal level changes significantly based on the unsteady state. Set the number n I (bit/word) to a wide pitch 1. This results in
Not only in the steady state but also in the J1 steady state, the signal separation circuit 14 can reliably detect the synchronizing signal from the FM detection output that has passed through the de-emphasis circuit 11.

The pedestal level detection circuit 13 detects the pedestal level V
po is detected and the pedestal level vP is determined from the reference voltage VRF.
l) generates an output (VRF - VP o ),
The adder 12 adds it to the digitized video signal to cancel fluctuations in the pedestal level, thereby digitally pedestally clamping the video signal. Pedestal clamped n, (bit/word)
The data of n 2 (bit/
The bits are reduced to the data of (nz < jl
l). nl is determined by the dynamic range and resolution required for a video signal in a steady state. This bit reduction facilitates the circuit design of the adder 2 and subsequent parts. Furthermore, by performing pedestal clamping, the signal level of the digitized video signal is n2 (bit/word) not only in a steady state but also in an unsteady state.
Since it is within the dynamic range of CL
This means that the image can be viewed even in an unsteady state such as when scanning V.

In the above configuration, regarding the dynamic range of each circuit constituting the digital signal processing system, the dynamic range up to the input of the signal separation circuit 14 is set to nl (bit/word), and regarding video processing, a pedestal clamp is used digitally. After that, n 2(bit/wo
However, as shown in Figure 10, digital FM
It is possible to separate the output of the detection circuit 7 into two systems, a video processing system and a signal separation system, and to make the number of bits n for each prefecture different.

That is, in FIG. 10, the number of bits n of the signal separation system
U) The number of bits n that has a sufficiently wide dynamic range even when the pedestal level changes significantly in steady state.
It is set to I (bit/word). This n 1(b
The data of "it/word" is supplied to the signal separation circuit 14 via the I-P F 16. 1. The PF 16 may be any filter that has characteristics that allow the synchronization signal to be detected from its output, and the configuration can be simplified by using a filter coefficient simplified as J:. On the other hand, regarding the video processing system, the number of bits n2 (formerly t/
word) divemic range. 02 is determined by the dynamic range and resolution required for a video signal in a steady state.

In this way, the digital FM detection output is nl+n 2
By separating into two systems (bit/word),
Since the circuit after the video LPF 10 can be designed by considering only the steady state case, the circuit configuration can be simplified, and the synchronization signal can be reliably detected even in the steady state, such as when the spindle motor 24 starts up. In addition, in such a circuit configuration, in an unsteady state, there may be cases where the image cannot be seen due to changes in the pedestal level, but this means that the image can only be seen in the steady state, and the synchronization cannot be ensured in the unsteady state. This is based on the idea that it is sufficient if the signal can be detected. However, in the CLV scan, synchronization is achieved to some extent in the clock generation circuit 21, so there are many gaps in which the change in the pedestal level is small, and in this case, the image can also be viewed.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit 13. In this figure, LPF11
The digitized video signal (a) from which the color verse 1- has been removed at step 7 is supplied to a pedestal limp ring circuit 118 and a synchronization pre-circuit 119, respectively. Synchronous separation circuit 1
At step 19, the synchronization signal (b) included in the digital video signal (a) is separated and extracted, and the synchronization signal (b) is supplied to a rise detection circuit 121 and a fall detection circuit 120, respectively. The fall detection circuit 120 detects the fall of the synchronizing signal (b) during the generation period of the first signal (C) output from the timing signal generation circuit 122, and the rise detection circuit 121 detects the fall of the synchronization signal (b) during the generation period of the first signal (C) output from the timing signal generation circuit 122. The rise of the synchronous signal 8(b) is detected during the generation period of d).

The timing signal generation circuit 122 generates a first gate signal (C ), and then generates a dropout detection signal (9) after a certain period of time based on the falling detection timing by the falling detection circuit 120
) is not generated, the second gate signal (d) is generated.

The sample period signal generation circuit 123 generates a sample period signal (e) of a certain period in response to the detection output of the rising edge detection circuit 121, and supplies it to the pulse generation control circuit 124.

The pulse generation control circuit 124 is, for example, a three-way AND circuit that receives the sample period signal (e) from the sample period signal generation circuit 123 and the dropout detection circuit (Q) as inputs.
Game h125 and the detection horn of the rising edge detection circuit 121 are input to Serah (S), and the output of 125 to AND Group 1 is input to Reset I- (R), and the clock signal is input to Clock (CK
A
The output pulse of the ND gate 125 is converted into a limp ring pulse (
f) to the pedestal 1 non-pulling circuit 118. The pedestal limp ring circuit 118 is composed of a D-type flip-flop or the like, and responds to the lean pull pulse (f) to convert the pedestal level Vp of the digitized video signal.
Latch o. The sampled pedestal level Vpo is subtracted from the reference level VRF by the arithmetic circuit 127 and averaged among the plurality of 11's.
p o ) level detection output.

FIG. 12 shows the operating waveforms of the circuit of FIG. 11, and FIGS. 12(a) to 11(l) respectively show the waveforms of each part (a) to (q) of FIG. 11, respectively.

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the fall of the horizontal synchronization signal included in the synchronization signal (b) is detected by the first gate signal (C), and the horizontal synchronization signal is detected using this fall as a reference. After a time corresponding to the width, a second gate signal (d) is generated to detect the fall of the horizontal synchronizing signal (b), and the sample period signal (
e), it is possible to reliably capture the horizontal synchronizing signal and sample the pedestal level on the back porch during the horizontal planking period. Furthermore, since color bursts have been removed from the digitized video signal (a) by the LPF 17, it is possible to generate a wide period signal (e) including the portion where the color bursts were present.

The sampling pulse (f) is the generation period of the 4 non-pulling period signal (e) and the dropout detection signal (q).
It is generated during the non-occurrence period, and has a pulse width equivalent to one clock of the clock signal. Therefore, if there is a dropout shorter than the sample period, Figure 12 (
As shown by the two-dot chain line in f), one clock worth of sampling can be reliably performed in 1H without the influence of dropout. Also, 1st. Second gate signal (C).

(d) is generated excluding the part where dropout occurs, so even if a false horizontal synchronization signal is generated due to dropout, a sample period signal will not be generated erroneously based on this horizontal synchronization signal. It is.

Output of pedestal level detection circuit 13 (VRF-Vpo
) is added to the video signal by the adder 12 in FIG. 1(B), thereby performing pedestal clamping. Further, the pedestal level Vpo is also supplied to the signal separation circuit 14 in FIG. 1(B), and in this circuit 14, synchronization signals and control signals are separated using the pedestal level Vpo as a reference level.

Note that in the above configuration, [P"117 in the input part can be omitted, but if omitted, it is necessary to generate the sampling period signal in a period other than the color burst part. In addition, the pulse generation control circuit 124 The configuration of the circuit is not limited to the above-mentioned circuit configuration, and various configurations are possible, such as using a microprocessor.
1. The P F117 and the synchronous separation circuit 119 are the same as the LPF1 45a and the signal detection circuit 145 in FIG. 21, which will be described later.
Each of these circuits can be replaced with C, and these circuits may be used in common.

In Fig. 13, falling detection as in Fig. 11 = 23
- Circuit 120, rising detection circuit 121, timing signal generation circuit 122, and 1 non-pull period signal generation circuit 123
An example of a specific circuit configuration is shown. In this figure, the rising edge detection circuit 120 includes an l flip-flop 128 that receives the synchronization signal (b) as the data (D) input and a clock signal as the clock input, an inverter 129A that receives the synchronization signal (b) as the input, flip flop 12
Q output of 8, the first of the timing signal generation circuit 122
The Q output of the flip-flop 128 is a synchronizing signal (
b) is delayed by one clock, and in the NAND gate 129B, the fall of the synchronization signal (b), that is, the fall of the horizontal synchronization signal, is detected while the first gate signal (C) is at a high level. If there is, all three forces will be at high level at the moment of falling, and a low level detection output will be generated.

The timing signal generation circuit 122 includes the falling detection circuit 1
1H counter 130 which takes the detection output of No. 20 as a load (L) input and a clock signal as a clock input, and the output of this counter 130 is decoded and the first.
The circuit 131 generates the second gate signals (c) and (d). 1)” counter 130
is to count the clock for one day in synchronization with the falling edge of the horizontal synchronization signal, and if the video signal is NTSC, the clock is 14.3MHz=4fsc=91Of+
(fH is the horizontal scanning frequency) and becomes a 910 progress counter. Furthermore, the gate signals (c) and (d) are not generated during the period when the do [1 tube out is occurring.

Although not shown in the figure, if the 1H counter 130 is not loaded several times in succession, the first goo 1~ signal (C) is forcibly set to a high level to perform horizontal synchronization. Detect the falling edge of the signal. This means that the 1H counter 130 is shifted by 1/2H due to the equalization pulse.
This is to prevent the loading of the horizontal synchronizing signal from being performed thereafter, which prevents the pedestal level from becoming impossible to detect.

The rising edge detection circuit 121 is the timing signal generation circuit 1
It consists of a D-type flip-flop 132 which takes the second gate signal (d) from 22 as the data (D> input and the synchronization signal (b) as the clock input, and the second gate signal (d)
When the signal (b) rises, that is, the horizontal synchronizing signal rises while the signal (b) is at a high level, a high level detection output is generated from the Q output terminal. Sample period signal generation circuit 1
23 loads the detection output of the rising edge detection circuit 121 (
L) Consists of a 7-bit counter 133 that has input and enable (EN) input, is loaded with '90' until just before the horizontal synchronization signal rises, starts counting at the rise of the horizontal synchronization signal, and 1496 II~"127
” as the ripple period and the sample period signal (0
). Callan 1~ exceeds '127' and 0''
When this happens, the D-type flip-flop 132 is cleared and the load input and enable input are set to low level, returning to the load state and stopping.

Note that the fall detection circuit 120 and the timing signal generation circuit 122 are similar to the HV separation circuit 14 in FIG. 21, which will be described later.
5d and a part of the timing signal generation section of the system controller 18 in FIG.
D-type flip-flop 180 and inverter 1 in the figure
81A and NAND gate 181B as fall detection circuit 1
20, 1 counter 130 and gate circuit 13
1 to the 11-1 counter 183 and gate circuit 1 in FIG.
It would be nice if they could be shared with 82A.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 13, in which parts equivalent to those in FIG. 11 are designated by the same symbols. In this figure, LPFl
The synchronization signal @(b) separated and extracted by the synchronization separation circuit 119 from the digitized video signal (a) which has passed through the digital video signal (a) through the synchronization signal 17 is supplied to the fall detection circuit 134. Falling detection circuit 134 [
The falling edge of the synchronizing signal (b) is detected during the generation period of the gate signal (C) output from the timing signal generating circuit 135, and the detection output is supplied to the timing signal light <1- circuit 135.

The timing signal generation circuit 135 generates a gate signal l1l (C) based on the clock signal during the non-generation period of the dropout detection signal (f), and further generates a gate signal l1l (C) based on the falling detection timing by the falling detection circuit 134.
A thimble period signal (d) is generated at the front board of the horizontal synchronization signal after 1 day, and is supplied to the pulse generation control circuit 136.

The pulse generation control circuit 136 is, for example, a three-man-powered ANr) that receives the sample period signal (d) and dropout detection signal (f) from the timing signal generation circuit 135.
The set signal from the gate 137 and the timing generation circuit 135 is input as a set (S), the output of the AND gate 137 is input as a reset (R), and the clock signal is input as a clock (CK).
) and an SR flip-flop 138 whose Q output is used as an input to an AND gate 137,
The output pulse of the D gate 137 is converted into a sampling pulse (e
) to the pedestal limbering circuit 118. The subsequent operations are the same as those shown in FIG.

FIG. 15 shows the operating waveforms of the circuit in FIG.
) waveforms are shown correspondingly.

In the pedestal level detection circuit 13 having the configuration shown in FIG. 14, the fall of the horizontal synchronizing signal is detected using the gate signal (C), and after generating a set signal using this fall as a reference and opening the AND gate 137, Since the sample period signal (d) is generated corresponding to the front boardage after one day,
The pedestal level can be detected even during the vertical blanking period. In addition, if the falling edge of the horizontal synchronizing signal cannot be detected while the gate signal (C) is being generated after the pedestal level is limbed, the pedestal enable signal is generated from the rising edge detection circuit 134, and the pedestal level is limbed. When the next stage circuit is informed that the detected pedestal level is invalid, the previously detected pedestal level can be held. For example, by inputting the pedestal enable signal to the arithmetic circuit 127, the circuit 127 is caused to continue outputting the previously output (VRF - Vpo).

The gate signal (C) and the sampling period signal (d) are generated except for the part where the drop error 1 is generated, and the pulse generation control circuit 136 generates the sampling pulse (e) by 1[1]. Therefore, if the sample period signal (d) is not erroneously generated due to dropout, and the length of the dropout during the sample period does not exceed the sample period, the signal shown by the two-dot chain line in FIG. 15(e) Thus, one clock worth of sampling can be reliably performed in 1H without the influence of dropout.

As for the example of diversion, the same aspect as in the case of the configuration shown in FIG. 11 can be considered.

FIG. 16 shows the falling detection circuit 13 in FIG.
4 and a specific circuit configuration of the timing signal generation circuit 135 are shown. In this figure, the fall detection circuit 134 is a JK flip-flop 1 which receives the synchronization signal (b) as an inverted clock input and receives the gate signal @(C) as the J input.
39, when the synchronization signal (b) falls while the gate signal (C) is at high level, that is, the horizontal synchronization signal falls, the Q output becomes high level, and thereafter the reset signal becomes low level. The Q output is held high until the transition occurs. When the reset signal goes low, the Q output also goes low.

The timing signal generation circuit 135 uses the Q output of the JK flip 70 tube 139 as data (D> input, and a D type flip 70 tube 140 which uses the clock signal as the clock input, and the Q output of this flip 70 tube 140 as the D input, clock signal. D-type flip 70 tube 141 that uses a signal as a clock input
and load the Φ output of this flip 70 tube 141 (L
) input, a clock signal as a clock input, and a gate circuit 143 that decodes the output of this 1H counter 142 and generates a gate signal and a reset signal in a predetermined period.
Immediately after the Q output of the D-type flip 70 becomes high level, a load pulse for one clock is generated from the D-type flip 70 knob 140 and 141 to load the 1H counter 142. 1H counter 142 that counts the period of one day in synchronization with the falling
If the video signal is NTSG, the clock is 14.3M.
Hz-4fsc=91Of+ (f+ is the horizontal scanning frequency), which becomes a 910-decimal counter.

In the gate circuit 143, the gate signal (C) is not generated during the period when dropout occurs. Further, the reset signal is generated as a pulse once every 1H with a sufficient interval from the gate signal (C) so that the pedestal enable signal is recognized by the next stage circuit.

In addition, in the circuit of FIG. 16, the gate signal (C) is reduced to 1/2 due to the date and time of the 1H counter 142 due to the equalization pulse.
Measures similar to those shown in FIG. 13 are taken to prevent H deviation.

Further, it is also possible to replace or share the circuit between the circuit in FIG. 16 and the H-2 separation circuit 145d in FIG. 21 and the circuit in FIG. 31, as in the case of FIG. 13.

In addition, in each of the embodiments of the pedestal level detection circuit 13 described above, the video signal has been described as being digitized, but the application is not limited to digital video signals, and can also be applied to analog video signals. The same applies.

Next, the dropout correction circuit 1 in FIG. 1(B)
9 will be explained. This dropout correction circuit 19
corrects the dropout of the digitized video signal output from the adder 12, but regarding the dropout of the vertical synchronization signal part, it is replaced with a correction signal set in advance to a level equal to the signal level of the vertical synchronization signal. By doing so, the dropout is corrected.

The configuration of this dropout correction circuit 19 is shown in FIG. In this figure, the digitized video signal is supplied to the first selector switch 190, and the output of the switch 190 is passed through the first delay circuit 191 to the second delay circuit 1.
92 and 3.58 MH1 BPF193.

Here, when the delay amount of the BPF 193 is set to d, the delay amount of the first delay circuit 191 is set to IH-d, and the delay amount of the second delay circuit 192 is set to d. The output of the BPF 193 is sent to the adder 19 via a multiplier 194 with a coefficient of -2.
5 and is added to the output of the second delay circuit 192. The addition output of the adder 195 is sent to the second changeover switch 19.
6, and the output of the switch 196 becomes the output of the first changeover switch 190. The first changeover switch 190 is connected to the dropout detection circuit 17 (see FIG.
Switching control is performed by a dropout detection signal supplied from (see ).

The address generation circuit 197 generates a field identification signal, horizontal address, and vertical address based on the horizontal synchronization signal and vertical synchronization signal supplied from the signal separation circuit 14, and generates a field identification signal, a horizontal address, and a vertical address based on the address information from the vertical synchronization level generation circuit 198. A correction signal is generated which is set to a level equal to the signal level of the known vertical synchronization signal, and the second
This becomes the square input of the changeover switch 196. In the switching signal generation circuit 199, a horizontal synchronization period signal is generated during the generation period of the vertical synchronization signal based on the vertical address, and this vertical synchronization period signal becomes a switching signal for switching and controlling the second changeover switch 196. .

By the way, as shown in FIG. 18, the signal (A) before correction
If a dropout occurs in the vertical synchronizing pulse part of ) may cause a positional deviation of the vertical synchronizing pulse (in Fig. 18, a positional deviation of 1/211 occurs between the portions marked with ◯).

If the position f of the vertical synchronizing pulse occurs in this manner, there is a possibility that a field error will occur in subsequent video equipment. However, if dropout correction of vertical synchronization pulses is inhibited, synchronization loss may occur.

Therefore, as shown in FIG. 17, if a dropout occurs in the vertical synchronization pulse portion, the vertical synchronization level generator 11 circuit 198 outputs a signal instead of the signal from 1H earlier.
By supplying a correction signal with a level equal to the signal level of the vertical synchronization signal to the first changeover switch 190 and replacing the digitized video signal, the vertical synchronization pulse can be dropped without causing a position shift. Correction of tj
can become.

Note that at J3 in FIG. 17, dropout correction is performed using the signal from one day ago, but at this time, the phase of the chroma signal will become reversed if left unchanged. Therefore, the phase of the chroma signal is inverted by the circuit surrounded by the broken line in FIG. 17, thereby making it possible to colorize the drop error 1 to correction signals. Therefore, when dropout correction is performed only on luminance signals (monochrome), 21
In the case of a signal before -1 (the clock signals are in phase), the circuit shown in the broken line above is excluded. Address generation 1-circuit 197
, vertical synchronization level generation circuit 198 and switching signal generation circuit 1
99 may be included in system controllers 1 to []-ra 18,
111 counter 183° gate circuit 1 in Fig. 31
82A, 1 frame counter 189° gate circuit 182
It may be replaced with B, etc.

The seven drops 1 to the detection circuit 17 in FIG. 1(A) have a level comparator configuration, and as shown in FIG.
That is, it detects that the signal level of the square signal (B) of the envelope component of the digitized FM video signal (Δ) has become below a predetermined value, and outputs the dropout detection signal (C). According to this configuration, a detection circuit can be configured in the dropout amplifier 1 by adding a level comparator to the FM detection circuit 7, so that dropout detection can be reliably performed with a simple circuit configuration, and the detection operation can be performed easily. Since everything is done digitally, stable characteristics can be obtained.

Note that due to the sudden change in the envelope 1]-, the sum of squares circuit 72
Although there is a possibility that the −C detection power is disturbed due to ringing that occurs in the output of By outputting the dropout detection signal (D) at the acid n1 point where the level is below a predetermined value and at the n2 point after the level becomes above the predetermined value as a dropout section, subsequent corrections can be performed reliably. It will be possible. At this time, since ringing may occur due to the delay of the Hilbert converter 70, nl+n2 is set equal to or larger than the delay time n of the delay circuit 71.

The signal separation circuit 14 in FIG. 1(B) separates and extracts control signals such as frame numbers and stop codes along with color burst signals, horizontal synchronization signals, vertical synchronization signals, etc. contained in the digitized video signal. For this signal separation, a first reference level VTI-11 for separating and extracting the control signal @ shown in FIG. 20, and a second reference level for separating and extracting the synchronization signal B. V
TI-12 is set.

The configuration of this signal separation circuit 14 is shown in FIG.

In this figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum level of the digitized video signal within a predetermined period. The configuration of the minimum value detection circuit 20 will be explained in detail later. Based on each detection level of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the first. 2nd Jin level VT
I-11°VTH2 is set, and the reference level generation circuit 140 adds a constant value to the detected level based only on the detection level of the pedestal level detection circuit 13, thereby setting the first reference levels VT and HI. The reference level generation circuit 141 is connected to the pedestal level detection circuit 1.
3 and the detection level of the minimum value detection circuit 20, an intermediate value between both levels is generated as a second reference level VTI-12. The reference level generation circuits 142 and 143 generate the first. Second reference levels VTHI and VTH2 are generated.

Each output of the reference level generation circuits 140 to 143 is supplied to a selector 144, and this selector 144 selects the reference level generation circuit 140 when the synchronization establishment determination signal is supplied from the system controller 18, that is, when the synchronization is stable. The first .141 generated. second reference level V
TI-11 and VTH2 are selected, and in other cases, that is, when the synchronization is unstable, the first. Second reference level VTHI, VT142
Select. Note that the system controller 18 determines whether or not synchronization is established by comparing a reference synchronization pulse based on an internal clock with the extracted synchronization pulse. The first one selected by the selector 144. The second reference levels VTHIIVT)-12 are supplied to a signal detection circuit 145C, which detects these reference levels VT1-11. LPF based on VTH2
A control signal and a synchronization signal B are separated and extracted from the digitized video signal that has passed through the digitized video signal 45a.

That is, in the signal separation circuit 14 configured as described above, when the daily cycle is stable, the first. Second reference level VT1-11. V
Based on TH2, or when the synchronization is unstable such as when the spindle motor 24 starts rotating or during a search or scan of the CLV disk, the pedestal detection position is not determined and its value is not determined, so it is based only on the minimum level. The first set. Second standard L/be/LzVvH+
, VTH2, the control signal A and the synchronization signal B are separated and extracted. According to this, signal separation can be performed stably and reliably not only when synchronization is stable but also when synchronization is unstable. The separated synchronization signal B is HV
input to the separation circuit 145d, and the system controller 1
The horizontal synchronization signal is separated by detecting the fall of the HS gate signal from 8 when it is at high level. Further, the synchronization signal B is subjected to integration processing in a 1-IV separation circuit 145d, and a vertical synchronization signal is separated based on a predetermined reference level. The digitized video signal is converted to f with the LPF 145a.
scBPFl 45b, fscBPF145
A color burst signal containing a color signal component is output from b.

By the way, regarding the detection of the synchronization signal in the signal detection circuit 145G, as shown in FIG. 22, when the digitized video signal is sampled at every predetermined clock (the sample point marked with an x in the figure), the signal level of the synchronization signal is the standard. Level V
The synchronization signal is detected at the time when TI-12 is exceeded.

The configuration of this synchronization signal detection circuit is shown in FIG.

In this figure, a reference level generation circuit 141 (or 143
) A subtracter 146 that receives as input the reference level VTH2 and the digitized video signal that has passed through the LPF 145a.
calculates the level difference between the signal level of the video signal with respect to the reference level VTH2 at each simple point, and detects the Zamble point where the video signal level is lower than the reference level VTH2 as a synchronization signal. The level difference signal calculated by the subtracter 146 is sent to a delay circuit 147, a sign determination circuit 148, and a storage device 1 such as a ROM (read only memory).
49. The delay circuit 147 provides a delay block equivalent to one clock, delays the level difference signal from the subtracter 146, and supplies the delayed signal to the sign determination circuit 148 and the storage device 149. The sign determination circuit 148 is in a state where the output A of the delay circuit 147 is positive and the output B of the subtracter 146 is negative, that is, the level difference at the sample point a of the straight curve where the output A of the delay circuit 147 exceeds the reference level VTH2. and the output B of the subtractor 1/46
It is determined that there is already a level difference at the sample point immediately after exceeding the reference level VTl'2, and the determination signal is stored in the storage device 1.
Supply to 49.

For example, a time table as shown in FIG. 24 is stored in advance in the storage device 149, and the storage device 149 stores the outputs of the delay circuit 147 and the subtracter 146 when the determination signal is generated from the sign determination circuit 148, That is, corresponding time information is output based on the level differences A and B at the two sample points a and b. Input A of the storage device 149;
Both B and the output are, for example, 4-bit data, and the first 1 bit of the 4 bits of input A and 8 is a sign bit, and is expressed as a two's complement number. Storage device 14
The time information that is the output of 9 is the time point C when the signal level of the synchronization signal exceeds the reference level VTH2 and the sample point a or b.
What is the time difference? This makes it possible to accurately detect the position of the falling edge of the synchronization signal even if the time point C does not coincide with the sample point in time.

Next, the minimum value detection circuit 20 in FIG. 21 will be explained. In FIG. 25, the counter 200 counts the clock so that the first
The second period pulse is generated at intervals of a period longer than one day. These period pulses are supplied to the selector 201, and the first period pulse is used in a steady state, and the second period pulse is used in an unsteady state where the disk rotation is unstable, such as when the spindle motor 24 starts rotating, or during a CLV surge or scan. Pulses are selected and provided to register 202 and averaging circuit 2.3. L
The comparator 204, which uses the digitized video signal output from PF1=15a, inputs its input data A and the register 2.
The data B stored in the register 202 is compared with the data B stored in the register 202 every time a clock occurs, and the smaller data is supplied to the register 202. However, the comparator 204 is designed to stop its operation when dropout occurs. Since the register 202 is reset by the first or second period pulse supplied from the selector 201, the smallest value from the previous reset time will be stored in the register 202. The minimum value stored in the register 202 is loaded into an averaging circuit 203 every time a first or second period pulse occurs, and the averaging circuit 203 averages each minimum value of two or more detection periods and finally calculates the minimum value. Output as the minimum value.

In such an ellipse, the minimum value of the video signal usually appears at some point during the synchronization signal period, so a one-day period is set as the detection period (first period pulse generation interval). In an unsteady state such as at startup, CLV serve, or scan, the length of the 11'' period fluctuates because the rotation of the disk is not stable.

At this time, if minimum value detection is performed at normal intervals based on the first period pulse, there may be a case where the synchronization signal is not included within the interval. Therefore, in an unsteady state, by using a second period pulse that is generated every period longer than the period equivalent to one day, the synchronization signal will be included within the detection period, so the minimum level can be reliably detected. This means that the variation in the minimum value level can be reduced. In addition, when a dropout occurs, a value that is temporarily lower than the signal level of the synchronization signal may occur, but the comparator 204 will stop operating during the dropout period and prohibit the detection operation. This makes it possible to prevent erroneous detection of the minimum value.

In addition, the counter 200 is activated by the dropout detection signal.
Since the counter 200 starts counting the predetermined period again after the dropout, even if the synchronization signal part is lost due to a dropout, the level of the synchronization signal part will be reliably detected before the next period pulse is generated. can be done.

The clock generation circuit 21 in FIG. 1(B) operates at 4fsc ('fsc is the subcarrier frequency) based on the reference horizontal synchronization signal from the reference signal generator 22 or the horizontal synchronization signal or color burst signal from the signal separation circuit 14. and 4Nfsc (for example, 12fsc), and P [4-phase locked loop]
It has a circuit configuration. The 4 f s generated here
The clocks of C and 4Nfsc are used as clocks for digital signal processing, and the sampling clock of A/D converter 4 and the clock of signal processing up to video L and P F10 are set to 4Nfsc, and video LPF10
From the output of 4. Downlink to f sc.

The configuration of the clock generation circuit 21 is shown in FIG.

In this figure, a phase comparator 210 which receives a color burst signal as a comparison W semi-input is a limp ring pulse generating circuit 21.
limp ring pulses CK+, C
Phase comparison is performed in response to K2. Note that when locking the PLL to the reference horizontal synchronization signal or the horizontal synchronization signal, the phase comparator 210 is not used, but another phase comparator (not shown) is used to lock the PLL to one of these signals and 2fs.
The phases of c, 1/455 L, and fH signals are compared, and the output thereof is input to the LPF 212.

Hereinafter, only the case of locking to the color burst signal will be explained. The comparison output of the phase comparator 210 is LPF2
The signal is supplied to the D/A converter 213 via 12, is converted into an analog signal, and is converted to VcO (voltage 17118 oscillator) 2
14 f) RIJ control signal tonal. The oscillation frequency of the VGO 214 is set to 12f'sck, and is output as is as a clock of 12fsc, and is divided into 4fsc by the 1/3 frequency divider 215. This clock 4fsc
is output as is, becomes the sole power of the sampling pulse generation circuit 211, and is further outputted to the 1/2 frequency divider 216.
and 217, the frequency is divided to fsc and becomes the comparison input of the phase comparator 210. The gate pulse generated by the gate pulse generation circuit 218 is supplied to the sampling pulse generation circuit 211 as a separate signal, and therefore the phase comparator 21
The sampling pulses OK+ and CK2 are supplied to the sampling pulse 0 only during the generation period of the goo 1- pulse. The gate pulse generation circuit 218 generates 4fsc based on the horizontal synchronization signal.
As shown in FIG. 27, a gate pulse (B) is generated only during a period corresponding to the central portion of the color burst signal (A) where the amplitude is constant.

In the phase comparator 210, as shown in FIG.
The color burst signal becomes the input of the adder/subtractors 219 and 220, and each addition/subtraction output passes through delay circuits 221 and 222 and becomes the other input of the adder and subtractor 219 and 220, and is divided by the divider 223. The addition/subtraction (±) control of the adders/subtractors 219 and 220 is performed using the clock pulse fsc shown in FIG.
Based on (B), sample point S+, addition at 82,
At sample points 83 and 84, brightness is reduced. However, when a track jump is performed during still image playback, etc., the phase of the color burst signal changes by 180 degrees, so the clock pulse fsc changes every time a track jump occurs.
Invert the phase of (B) to maintain PLL lock.

This is controlled by the 1/2 frequency divider 21 by the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).
This is done by controlling 7.

The sampling pulse generation circuit 211 is composed of 70 D-type flips, and the sampling clock GK+
, CK2 are synchronized with 4fsc, and have half the frequency and opposite phases to each other, and only when the gate pulse is at a high level, the delay circuits 221.2 and 221.2 are respectively activated.
22 clock.

As a result, assuming that the amplitude of the color burst signal (A) is A, ΣA sinθ is derived as the output of the delay circuit 221, ΣA CO8θ is derived as the output of the delay circuit 222, and tanθ is derived as the output of the divider 223. Ru. Then, this division output tanθ is converted to tan-' circuit 2.
By passing 24, the phase difference θ is obtained.

is obtained.

That is, the phase difference θ in the phase comparator 2'IO can be calculated from the following equation.

θ=jan-' (Σ[(S+ -8g)/(82
-84) ]) Here, ]5t-A-slnθ52=A-
CO3θ53=-A φ5in084-A vague cosO
By the way, as is clear from the above equation, if the amplitude A of the color burst signal (A) is not constant within 1 to 1, then
A slight error will occur in the detected phase difference θ, and a change in the loop characteristics will occur due to a change in the P I-L loop gain.

However, in the clock generation circuit 21 described above, 81 to
Sampling pulse GK+ for finding S4.

By applying a gate to CK2, the phase comparison is performed only during the period in which the amplitude A of the color burst signal (A> is constant - t), so the above-mentioned problem does not occur.

In the above configuration, the limp ring pulse is gated to perform phase comparison only in the central portion of the color burst signal, but it is of course possible to gate the color burst signal itself. be. In this case, since it is a digital gate, only the central part of the color burst signal can be extracted more accurately than an analog switch or the like. Furthermore, in FIG. 26, the arrangement relationship between the LPF 212 and the D/A converter 213 may be reversed.

51- In FIG. 1(B), the reference signal generator 22 is composed of a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronization signal. The spindle motor circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronization signal from the reference signal generator 22 and the horizontal synchronization signal from the signal separation circuit 14. The chroma inversion circuit 25 performs phase inversion of the chroma (color) signal as necessary to maintain color framing even during special playback such as still and slow playback.

The configuration of this chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is sent to a one-day delay circuit 270.
, are supplied to the adder 271. After the signal level of the output of the adder 271 is halved by the level adjustment circuit 272,
It is supplied to a subtracter 273. The subtractor horn of the subtracter 273 is supplied to an adder 275 via a phase linear acyclic digital BPF 274, and the addition output of the adder 275 is supplied to a changeover switch 276.

The delayed output of the delay circuit 270 is sent to the subtracter 273 and BPF2.
The signal is supplied to a delay circuit 277 having the same delay amount as 74, and is also supplied to an adder 271 via a one-day delay circuit 278. The delayed output of delay circuit 277 is provided to adder 275 and switching switch 276. Changeover switch 27
6 is appropriately switched depending on the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).

With this configuration, a 2.3-line correlation comb filter is configured, and the subtracted output of the subtracter 273 is transmitted to the 1-day delay circuit 2.
For a delayed output of 70 (Y is 10), 2
This results in a chroma signal (-2G) with twice the level. After unnecessary components are removed from this chroma signal by the BPF 274, the delay output (Y+C') whose delay amount has been adjusted by the delay circuit 277 is added to the delay output (Y+C') by the adder 275.
A digitized video signal (b) having a chroma signal inverted with respect to the delayed output (a) of No. 7 is obtained as an addition output. In special playback such as stay or slow, color framing can be maintained by switching the selector switch 276 using the chroma inversion control signal from the system controller 18 in FIG. 1(B).

In FIG. 1B, the output of chroma inversion circuit 25 is supplied to video processing circuit 38. In FIG. The video processing circuit 38 performs character insertion, MCA code suppression, squelch, etc. The digitized video signal that has passed through the video processing circuit 38 is written into three buffer memories using a 4fse clock generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal.

Reading from the buffer memory 39 is performed using a 4fsc reference clock generated by the reference signal generator 22. In this way, by reading from the buffer 1 memory 39 using a stable reference clock that is unrelated to the reproduced signal, jitter in the reproduced signal can be absorbed, eliminating the need for so-called tangential servo and color correction circuits. Become. The digitized video signal read from the buffer memory 39 is converted into an analog signal by a D/A converter 40 and supplied to an output terminal 42 via L and P F 41.

The system controller 18 has the following main functions. That is, 1. The various servo systems are controlled in response to commands from an operation unit such as a panel switch or remote control, and state signals from the servo system, thereby causing the player to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generate signals for compositing frame numbers, chapter numbers, etc. onto the screen.

4. Synchronize the internal counter with the horizontal synchronization signal and vertical synchronization signal, and decode the output of the counter to generate various timing signals.

5. Control the clock generation PL, L, and loop. A specific configuration for realizing the fourth function among the above main functions will be described below.

In FIG. 31, a D-type flip 70 tube 18 which uses a horizontal synchronization signal (-Higurashi () as a data (D) input and a clock signal of 4.fsc as a clock (CK) input)
0 is provided, and the Q of this flip 70 knob 180 is
The output is solely from the NAND gate 181B. NAN
The D gate 181B has the horizontal synchronization signal supplied via the inverter 181A as another input, and its output is 1H.
This becomes the load (L) input point of the counter 183. The gate circuit 182A decodes the output of the one-day counter 183, generates the 1-18 gate signal during a predetermined period, and inputs it to the HV separation circuit '1115d of FIG.
Clock HCK of fH frequency synchronized with horizontal synchronization signal
make it emit. The l-I S gate signal is used in the l-I V separation circuit 145d to detect the fall of the horizontal synchronizing signal excluding the equalization pulse and to separate the horizontal signals. In the initial state, the 1-18 gate signal is always at a high level, and the 1H counter 183 is loaded at the falling edge of the synchronizing signal, and then only for a predetermined period so that the falling edge of the horizontal synchronizing signal is detected every day. Becomes a high level. In the initial state or for some reason, if the 1H counter 183 is loaded due to the falling edge of the equalization pulse and a 1/2H shift occurs, the 1H counter 183 will not be loaded after the vertical blanking period, so the system This state is detected within the controller 18, and the IS gate signal is kept at a high level again. In addition,
The l-IV separation circuit 145d generates a pulse of a predetermined width based on the fall of the horizontal synchronizing signal, and outputs this as a horizontal synchronizing signal. The clock HCK is a signal having a duty ratio of 50%, starting from the falling edge of the synchronization signal, and being at a high level in the first half and a low level in the second half. The gate circuit 182A further generates various timing signals within 1H and supplies them to each circuit.

The positive polarity vertical synchronization signal (VS) becomes each clock input of D-type flip-flops 184 and 185.

The D-type flip-flop 184 uses the VS gate signal output from the gate circuit 182B as a data (D) input, and when the vertical synchronization signal rises while the signal is at a high level, its Q output becomes high level, ◇ The output becomes a low level and remains in that state until the reset signal becomes a low level. When the reset signal becomes a low level, the Q,0 output is inverted.

The D-type flip 70 tube 185 uses the clock (ICK) output from the gate circuit 182A as a data input, and is used to determine whether the vertical synchronization signal is from field 1 or field 2. In field 1, the rising edge of the vertical synchronizing signal arrives when the clock HCK is at a low level, so the Q output becomes a low level and the d output becomes a high level, and in field 2, the rising edge of the vertical syncing signal arrives when the clock HCK is at a high level. Therefore, the Q output is at a high level and the Φ output is at a low level. The D-type flip-flop 186 uses the Q output of the flip-flop 184 as a data input, the clock HCK as a clock input, and the Q output of the flip-flop 185 as a clear input. When the clock HCK rises, the Q output becomes high level, and in field 1, the Q output remains low level.

The Q and Q outputs of the D-type flip-flop 184 are J.

The J-flip 70 tube 187, which uses the clock 1-tcK as the inverted clock input and the 0 output of the flip-flop 185 as the clear input, causes the Q output of the D-type flip-flop 184 to be at a high level in field 1. Then, the Q output becomes high level at the fall of the clock HCK, and in field 2, the Q output remains low level. D type flip 70 knob 186 and J- to flip 7
NOR gate 1 where each Q output of 0tube 187 is powered by two people
88 uses the output to control one frame counter 1 in the next stage.
89 and reset the D-type slip 70 knob 184. Here, the reason why the load pulses are created using seven different lip-flops for each field is that the load pulses, which are wide enough in each field, are
This is to send it to the frame counter 189. The 1-frame counter 189 is a 525-decimal counter that subtracts the clock HCK by 1, and is loaded with the clock HCK when the output of the NOR gate 188 is at a low level.
The D-type flip-flop 1 is loaded so that the number loaded in field 2 is 263 more than that in field 1.
It is controlled by the 0 output of 85.

The gate circuit 182B decodes the output of the one frame counter 189 and generates the above-mentioned VS gate signal in a predetermined period, and also generates a timing signal of H units within one frame and supplies it to each circuit.

Next, the fifth of the above-mentioned five functions of the system controller 18, that is, the function of controlling the Pl of clock generation and the [loop] will be explained based on the diagram 70 in FIG. 32. As mentioned above, this PLL has two phase comparators, one for locking to the reference horizontal synchronizing signal or the reproduced horizontal synchronizing signal and the other for locking to the color burst signal. The configuration is such that three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal input to the input section of the phase comparator, and by switching the phase comparator itself. In FIG. 32, in an initial state such as immediately after the power is turned on or when the spindle motor is forcibly accelerated, the reference signal generator 22 (see FIG.
The PLL loop operates to lock to the reference horizontal synchronization signal obtained in step B) (step 1). When it is determined that it has locked to the reference horizontal synchronization signal (step 2) and the horizontal synchronization signal can be obtained from the reproduced video signal, the loop is switched to the reproduction horizontal synchronization signal (step 3).

At this time, if it is determined that locking is not possible (step 4
), return to step 1 and loop back to the reference horizontal synchronization signal. If it is determined in step 4 that it is locked to the playback horizontal synchronization signal, the presence or absence of a color burst signal is detected in step 5), and if there is no color burst signal, step 4)
Return to and keep locked to the playback horizontal sync signal.

This state occurs during the vertical blanking period for both black and white discs and color discs. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). Here, if it is determined that locking to the color burst signal is not possible, step 7)
Returning to the playback horizontal synchronization signal loop of the stabilizer 3, if lock is achieved, the color burst loop state is maintained.

However, at the same time, the synchronization with the playback horizontal synchronization signal must be monitored (Step 8). If either the lock with the color burst signal or the lock with the playback horizontal synchronization signal is lost, it is assumed that the lock is lost and the playback horizontal synchronization signal is looped. (Step 3
). At this time, if the loop of the reproduced horizontal sync signal cannot lock to the reproduced horizontal sync signal (step 4),
Furthermore, the process returns to the reference horizontal direction II signal loop (step 1).

Note that a NO determination in step 4.7 indicates that the lock cannot be locked within the predetermined period when passing for the first time.
When passing for the second time or later, it indicates that it is not locked.

This system has been explained above by showing the specific configuration of each circuit, but this system includes an A/D converter 4
A major feature is that all signal processing between the D/A converter 40 and the D/A converter 40 is performed digitally. in this way,
By digitizing signals, multi-functionality can be achieved, e.g.
Colorization of the monochrome dropout correction signal,
It becomes easy to perform chroma inversion, increase the precision of Y-C separation by introducing a frame memory, or reproduce still images using CLV.

In FIG. 1B, the circuits are arranged in the order of the adder 12, the dropout correction circuit 19, the chroma inversion circuit 25, the video processing circuit 38, and the buffer memory 39, but the arrangement is not limited to this arrangement. For example, as shown in FIGS. 33(A) and (B), the order of "dropout correction circuit 19 + chroma inversion circuit 25", "video processing circuit 38", and "buffer memory 39" can be changed. It is. However, since writing and reading of the buffer memory 39 are asynchronous, the "buffer memory 39"
If there are two other signals after this (as in the case of FIG. 33(B)), it is necessary to resynchronize or extend the control signals and timing signals for the other two signals. In addition, [video processing circuit 3
8] is followed by "dropout correction circuit 19 + chroma inversion circuit 25" (in the case of FIG. 33(A)),
When a character is inserted by the video processing circuit 38, a control signal is required to inhibit the dropout correction circuit 19 from performing dropout correction in the character portion.

Furthermore, as shown in FIG. 34, R, G, and B separation can also be performed digitally, and the RGB separation circuit
3 is converted into an analog signal by a D/A converter 44 and sent to each analog output terminal 4 via an LPF 45.
By supplying signals to 6R, 46G, and 46B, if you connect these terminals to a monitor TV (television) with RGB input, there is no need to use the RGB separation circuit in the TV, which improves the image quality. It will be possible to achieve this goal.

Furthermore, when using a digital TV that can input RGB as it is digitized, the digital signals separated by the RGB separation circuit 43 are directly input to each digital output terminal 47R, 47G, without going through a D/A converter. 47B.

In this RGB separation, in this system, the clock of the A/D converter 4 is set to 4Nfsc (N is an integer of 2 or more), and the 4fsc clock is locked to the color burst signal of the video signal, so the RGB separation is performed. (demodulation) can be easily performed. Hereinafter, a case will be described in which demodulation is performed using the RY and BY signals, but the demodulation can be similarly performed using the I and Q signals.

In the NTSC system, the phase of the color signal is as shown in FIG. 35, which is quadrature two-phase modulated and frequency multiplexed with the luminance signal. The relationship between the R, G, and B signals and the luminance signal Y is shown in the following equation.

Y= 0.3OR+ 0.59 G+ 0.11 B・
(1) Also, the color signal C in the video signal is expressed by the following equation.

RY B-Y C= -CO8ωct + -stnωct1.14
2.03 ......(2) =) COS(ωc t +33') + Q 5in(ωc i +33") --(3)
Here, ωC is the angular frequency of the color carrier wave, and ωC−2π
X 3.58 M)+2.

When the phase of the 4fsc limp ring frequency is locked to the color burst signal at Oo, Fig. 35 and (2) are obtained.
From the formula, each sample point is ±(R
-Y)/1.14 and ±(BR)/2.03. Also, from equations (1) and (2), R, G, and B signals are obtained. Furthermore, I.

To obtain the Q signal, ±33° relative to the color burst signal.
Alternatively, it is sufficient to turn off at ±57° (f'7 phase).

From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst signal.

In the above embodiment, the case where the system is applied to an NTSC video disc player has been described, but this system is applicable to VTR playback side signal processing, PAL, SEC
It can also be applied to AM video disc players and the like.

As explained above, the present invention includes an analog filter that cuts a predetermined band component including the high frequency range of an FM-modulated video signal, and an analog filter for detecting the video signal from the A/D conversion output. Since the group delay characteristics of each digital filter that extracts only the necessary components are set complementary, the analog of A/D conversion [
Since FM detection can be performed in a state where group delay is eliminated by correcting the group delay caused by the 1-G noi filter, signal processing can be performed satisfactorily without causing waveform distortion after FM detection due to group delay. be able to.

[Brief explanation of drawings]

1(A) and (B) are block diagrams showing an embodiment of the video signal reproducing device according to the present invention, and FIG. 2(A) is a block diagram showing an embodiment of the video signal reproducing device according to the present invention.
The spectrum diagram of the signal, Figure 2 (B) is the analog L-PF amplitude characteristic diagram in Figure 1 (A>), Figure 2 (C)
is a group delay characteristic diagram of the analog LPF, FIG. 2(D) is an iyu spread characteristic diagram of the digital BPF in FIG. 1(A), and FIG. 3A is a diagram of the digital BPF in FIG. 1(A).
The block diagram 1 and Figure 3B are similar to Figure 1 (
A block diagram showing an example of the configuration of the video I-ρ[in B), and FIGS. 4(Δ) to (C) are each part (A) to
The spectrum diagram of (C), Fig. 5 is F in Fig. 3B.
IR filter phase characteristic diagrams, Figures 6 to 8 are 3B
Block diagram showing the specific configuration of the FIR filter, downsampling circuit, and FIR filter shown in the figure, No. 9
Figure 10 is a block diagram showing another configuration of the video LPF.
The figure is a block diagram showing another configuration of the bit reduction process in FIG. 1(B), FIG. 11 is a block diagram showing the configuration of an example of the pedestal level detection circuit in FIG. 1(B),
FIG. 12 is an operation waveform diagram of each part in FIG. 11, and FIG. 13 is a falling detection circuit, a rising detection circuit, and a rising detection circuit in FIG. 11.
FIG. 14 is a block diagram showing the specific configuration of the timing signal generation circuit and the sample period signal generation circuit, FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit, FIG. 15 is an operation waveform diagram of each part of FIG. 14, FIG. 16 is a block diagram showing the specific configuration of the fall detection circuit and timing signal generation circuit in FIG. 14, and FIG. 17 is the same as that shown in FIG. 1(B).
18 is a waveform diagram for explaining the circuit operation of FIG. 17, and FIG. 19 is a block diagram showing the specific configuration of the dropout correction circuit in FIG. 1(A). 20 is a waveform diagram showing the relationship between the video signal and the reference level in the signal separation circuit in FIG. 1(B), and FIG. 21 is a waveform diagram showing the specific configuration of the signal separation circuit. 22 is a waveform diagram for explaining the operation of the signal g detection circuit in FIG. 21, FIG. 23 is a block diagram showing the specific configuration of the signal detection circuit, and FIG. Figure 23 shows [Puru RO]
FIG. 25 is a block diagram showing a specific configuration of the minimum value detection circuit in FIG. 21, and FIG. 26 is a diagram showing an example of the clock generation circuit in FIG. 1(B). A block diagram showing a specific configuration, FIG. 27 is a waveform diagram of each part in FIG. 26, FIG. 28 is a block diagram showing a specific configuration of the phase comparator in FIG. 26, and FIG. 29 is a circuit diagram of FIG. 28. A waveform diagram for explaining the operation, FIG. 30 is a block diagram showing the specific configuration of the chroma inversion circuit in FIG. 1(B), and FIG. A block diagram showing the configuration of a part of the hardware for Song Zume, FIG. 32 is a block diagram showing the predetermined functions of the controller, and FIG.
, (B) is a block diagram showing a modified example of this system.
4 is a block diagram showing still another modification, FIG. 35 is a phase characteristic diagram of a color signal used to explain the principle of RGB separation in FIG. 34, and FIG. 36 is a waveform diagram of a signal at each ripple point. Explanation of symbols of main parts 2...Analog L, PF4...A/D
Converter 6...Digital BPF 7...FM detection circuit 10...Video 1. P F13...Pedestal level detection circuit 14...Signal separation circuit 17...Dropout detection circuit 18...
...System controller 19 ...Dropout correction circuit 21 ...Clock generation circuit 22 ...Reference signal generator 24 ...Spindle motor 25 ... ... Chroma inversion circuit 38 ... Video processing circuit 39 ... Buffer memory 40 ... D/A converter

Claims (1)

[Claims] an analog filter that cuts a predetermined band component including a high frequency band of an FM-modulated video signal; an A/D (analog/digital) converter that digitizes the output of the analog filter; and an output of the A/D converter. a digital filter for extracting only the components necessary for detecting the video signal from the FM video signal, and the group delay characteristics of the analog filter and the digital filter are set to be complementary. processing circuit.