JPS62143267A - Bit reduction circuit in digitized video signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the bit without deteriorating the resolution even at the small signal level by decreasing a high-order bit of the signal while a digitized video signal amplitude is small and decreasing a low-order bit during other period. CONSTITUTION:The digitized video signal passing through a video LPF 10 is fed to a bit reduction circuit 15 through a de-emphasis circuit 11. The bit reduction circuit 15 is to reduce the data having n0(bit/word) of word length into a data of n1(bit/word) in an output of the de-emphasis circuit 11, and includes a high-order bit reduction circuit 151 reducing the high-order bit of the data n0(bit/word) fed via a multiplier 150 and a low-order bit reduction circuit 153 reducing the low-order bit of the data n0(bit/word). In this case, coefficients (a, b) of multiplication of multipliers 150, 152 are set in the relation of 1>=a>=b.

Description

DETAILED DESCRIPTION OF THE INVENTION Flame Opalescence 1 The present invention relates to a bit reduction circuit in a digitized video signal processing circuit.

1. A signal of an FM-modulated video signal (hereinafter referred to as FM video signal) read from a disc in a video disc player that plays back a recording medium, such as a video disc, on which a video signal is FM-modulated and recorded. Regarding processing,
Conventionally, it has been common to perform this in an analog manner.

However, when considering the integration of circuits into ICs (integrated circuits), it is extremely advantageous to perform signal processing digitally rather than analogously, and it is also easier to achieve multifunctionality in the signal processing process. Become.

By the way, when performing digital signal processing, it is advantageous to design a circuit if the number of quantization bits per one signal is small. Therefore, by reducing the number of bits set based on an unstable system in which the DC component of the video signal fluctuates greatly, in a system where the DC component is stable, the subsequent circuit configuration can be simplified. It is possible to aim for However, if the number of bits is uniformly reduced for a video signal, the resolution deteriorates in a portion where the signal level is low, for example, a color burst signal portion, and the S/N ratio of the color burst signal itself deteriorates.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a bit reduction circuit in a digitized video signal processing circuit that can reduce bits without deteriorating the resolution even in portions where the signal level is small. What is the purpose?

The bit reduction circuit according to the present invention reduces the upper bits of the digitized video signal during a period when the amplitude of the signal is small;
In other periods, the configuration is such that the lower bits are reduced.

Yo-ta-wari Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1(A), FMII! is read from a recording medium such as a video disk. II! The image signal is input to input terminal 1.
The signal is supplied to an A/D (analog/digital) converter 4 via an analog LPF (low pass filter) 2. The LPF 2 is for removing aliasing distortion in A/D conversion, but if there are very few components exceeding ωs/2 (ωS is the sampling frequency during A/D conversion) contained in the FM video signal, The LPF2 may be omitted.

The digitized FM video signal output from the A/D converter 4 is supplied to a digital BPF (band pass filter) 6. This digital BPF 6 extracts only the components necessary for detection of the A/D modified output video signal including the FM audio signal, and supplies the extracted components to the FM detection circuit 7 at the next stage.

For example, as shown in FIG. 2, the digital BPF 6 includes delay circuits 601 to 60n connected in series that delay one clock, and input signals of the delay circuit 60+ and output signals of the delay circuits 60+ to 60n. multiplication factor k
It is possible to use an FIR filter (acyclic digital filter) consisting of multipliers 61o to 61n that multiply o-kn, an adder 62 that adds the outputs of each multiplication, and a latch circuit 63 that latches the added output. , multiplier 610~
By appropriately selecting □-kn for each multiplication coefficient of 61n, desired amplitude characteristics and group delay characteristics can be obtained. Therefore, when group delay distortion occurs due to the analog LPF 2, by making the group delay characteristics of the digital BPF 6 inverse to those of the analog LPF 2, the digital FM
A video signal can be supplied. Also, analog LP
If the group delay distortion of F2 is small and can be ignored, or if analog LPF2 is deleted, use digital BPF6.
By using a phase linear filter in the same way, a signal without group delay distortion is
Q FM l-wa I-% Ding:: 7gu”, /y
Il, the coefficient Ko-Kn of OD port C is symmetrical about n (
Ko=Kn.

K+=Kn-+-...), it becomes an ideal phase linear filter.

The FM detection circuit 7, for example, as shown in FIG. 1(A),
A Hilbert transformer 70 that performs Hilbert transform on a digitized FM video signal, a delay circuit 71 that delays the digitized FM video signal by n sample periods, and squares each output signal of the Hilbert transformer 70 and delay circuit 71, respectively. a square sum circuit 72 that adds the sum of squares; a delay circuit 73 that delays the output signal of the delay circuit 71 by one sample period; a multiplier 74 that multiplies the output signals of the delay circuits 71 and 73; and a divider 75 that divides the output signal of the square sum circuit 72 by the output signal of the square sum circuit 72. The Hilbert transformer 70 is composed of a transversal filter and the like.

Also, the delay time of the delay circuit 71 is Hilbel]・Converter 7
This corresponds to a delay time of 0. Regarding the FM detection circuit 7 having such a configuration, the applicant of the present application has disclosed a patent application of 1983-262.
481 - In Figure 1 (8),
Videos L and P to which the detection output of the FM detection circuit 7 is supplied
In F10, only the baseband component of the video signal is extracted from the detected output. For example, the cutoff frequency of the video LP'F10 is 4.2M1 in the case of NTSC system.
- set to IZ. Figure 3 shows videos L, P F
An example configuration of 10 is shown in this video LPF1
0 is a phase-linear acyclic digital signal at the front stage that operates at a clock frequency of 4Nfsc (N is an integer of 2 or more) and removes the carrier component contained in the FM-detected digital video signal and extracts only the baseband component. Filter (F
IR filter) 100, a downsampling circuit 101 that downsamples the output of this FIR filter 100 to a clock frequency of 4fsc, and a subsequent cyclic circuit that operates at a clock frequency of 4fsc and compensates for the phase characteristics of the digitized video signal. Digital filter (II
R filter) 102.

In Fig. 4 (A) to (C), each part (A) in Fig. 3 is shown.
-(C) spectra are shown.

The 1M detection output (A) includes not only the baseband video signal but also its second harmonic component, and the FIR filter 10
By passing through 0, only the baseband video signal @(B) is derived at the output end. This baseband video signal <8) is transmitted to the downsampling circuit 101
The clock frequency of 4Nfsc is downsampled to the clock frequency of 4fsc. The spectrum after downsampling is the same as that in Figure (B).

By lowering the sampling frequency in this way, it becomes possible to reduce the time margin and hardware requirements.

Note that since the band of the digitized video signal is narrowed to approximately 4.2 MH2 by passing through the FIR filter 100, there is no problem even if the sampling frequency is lowered. After down-sampling, the baseband video signal (B) is compensated for its phase characteristics by the ITR filter 102. The spectrum (C) after phase compensation is also the same as that in Figure (B).

In the case of video disks, etc., the signal processing system for the playback signal has traditionally been analog, so the phase distortion of the video LPF is calculated when recording information, assuming that the phase will rotate in a video LPF designed in an analog manner. Information is recorded by distorting it in the opposite direction with reverse compensation. Therefore, when playing back a video disc with such a recording format and digitally processing the playback signal, it is necessary to further compensate for the inverse compensation valve for phase distortion during recording, and compensation for this phase characteristic is necessary. is the IIR filter 102
It is done in In Fig. 5, 11R filter 1
02 phase characteristics are shown.

6 to 8 show examples of specific configurations of the FIR filter 100, the downsampling circuit 101, and the IIR filter 102. First, in Figure 6,
The FIR filter 100 includes delay circuits 103+ to 103n connected in series to each other for delaying by one clock;
Input signal of delay circuit 1031 and delay circuits 1031 to 1
A multiplier 1f"I A --, 1 HAn l-1; LnE, 9 which multiplies each output signal of 03n by a multiplication coefficient ko-kn.
M-h b hn fts + X hn calculator 105
and a latch circuit 106 consisting of a D-type flip-flop or the like that latches this addition output, and a delay circuit 1
The clock frequencies of 031 to 1030 and the latch circuit 106 are set to 4Nfsc. As shown in FIG. 7, the downsampling circuit 101 is constituted by a latch circuit 107 consisting of a D-type flip-flop or the like, and its clock frequency is set to 4 fsc.

As a result, the data input to the latch circuit 107 is N
- Output every other item.

Moreover, as shown in FIG. 8, the IIR filter 102
A multiplier 108o that multiplies an input signal by a multiplication coefficient ko, an adder 109 that uses this multiplication output as one addition input, a latch circuit 110 consisting of a D-type flip 70 tube, etc. that latches this addition output, and an adder. Delay circuits 1111 to 111n connected in series to each other sequentially delay the addition output of 109 by one clock, and these delay circuits 1111 to 1.
A multiplier 1 that multiplies each output of 11n by a multiplication coefficient of 1 to kn.
The clock frequency of the device circuit 110 and the delay circuits 1111 to 111n consisting of 081 to 108n is 4fs.
It is set to c. In this circuit configuration, multiplier 1
By appropriately setting each multiplication coefficient ko-kn of 08o to 108n, phase characteristics as shown in FIG. 5 can be obtained.

In the video LPF 10 described above, the phase straight line FI
By using the R filter 100 at the front stage, all phase compensation can be determined only by the IIR filter 102 at the rear stage, and the amplitude characteristics can be adjusted without changing the phase characteristics.

Note that downsampling is performed before the IIR filter 102, but this is because the IIR filter 102
This is due to the fact that all operations must be completed within a clock period. In order to perform downsampling after the IIR filter 102, pipeline processing is impossible for the above-mentioned reasons, and the number of operations must be reduced or high-speed elements must be used, but there are limits to this as well. On the other hand,
If the downsampling is performed before the IIR filter 102, the clock cycle will naturally become longer, and if the number of resonants is increased accordingly, more accurate characteristics will be obtained and stability will also increase.

In the video L and P F 10 having the above-mentioned configuration,
The previous-stage FIR filter ioo was operated with a 4Nfsc clock, and its output was downsampled to a 4fsc clock by the downsampling circuit 101, but as shown in FIG. It is also possible to perform downsampling at 41'sc and operate the circuit after the arithmetic circuit with a clock of 41'sc. At this time, downsampling circuit 1
01 is not necessary.

That is, in FIG. 9, the FIR filter 100' includes delay circuits 1121 to 112n connected in series that delay one clock, and input signal and delay circuit 1.
latch circuits 1130 to 113n consisting of D-type flip-flops that latch each output signal of 121 to 112n;
Multipliers 114o to 114 multiply each wrap output of these latch circuits 1130 to 113n by multiplication coefficients ko to kn.
n, an adder 115 that adds these multiplication outputs, and a latch circuit 116 consisting of a D-type flip-flop that latches this addition output, and delay circuits 112+ to 112.
The operation of the latch circuits 1130 to 113n in the next stage is performed with the clock of 4Nfsc, and the operation of the latch circuits 1130 to 113n in the next stage is performed in the clock of 4Nfsc.
, adder 115 and latch circuit 116) at 4 fs.
The configuration is such that it is performed using the clock of c.

In the FIR filter 100- having such a configuration, the calculation is 4f.
Since it is performed using the sc clock, unnecessary calculations are omitted,
In addition, since the clock cycle becomes longer, the number of calculations can be increased, and relatively, the FIR filter 10 having the above-mentioned configuration
This means that the circuit scale can be reduced more than 0.

In addition, in FIGS. 6 and 9, in order for the FIR filter to have a phase linear characteristic, the digital BP port CL + Usutou Rinshin 1/ --, I/ nI-) rh-", 1-41
Ding M9r (Ko =) (n, K+ = 'n-+,
--).

Again in FIG. 1(B), the digitized video signal that has passed through the video LPF 10 is sent to the de-emphasis circuit 11.
The signal is then supplied to the bit reduction circuit 15. This bit reduction circuit 15 converts the data output from the de-emphasis circuit 11 and whose imperial length is n o (bit/word) to n 1 (
This is to reduce the data to n o (bit/word), which is supplied through the multiplier 150.
n supplied through a multiplier 152 and a high-order bit reduction circuit 151 that reduces the tenth bit of the data of /word).
It includes a lower bit reduction circuit 153 that reduces lower bits of Q (bit/word) data. Each multiplication coefficient ab of the multipliers 150 and 152 is set to have a relationship of 1≧a≧b. Each bit reduction circuit 151.15
3 performs reduction of the same number of bits (for example, 1 bit) and supplies them to the selector 154 as n+ (bit/word) data.

The selector 154 is normally located on the b side and outputs n + (bit/word) from the lower bit reduction circuit 153.
) is selected and then switched to the a side in response to the burst gate signal output from the system controller 18 to select n H (bit/word) data output from the upper bit reduction circuit 151. Select data. That is, the color television signal (A
), in view of the small amplitude of the color burst signal, the selector 1 is activated in response to the burst gate signal (B).
By switching 54 to side a, the upper bits of the color burst signal are reduced, thereby improving the resolution of the color burst signal when bits are reduced.

To be more specific, if the FM detection output signal having a word length of no (bit/word) after passing through the de-emphasis circuit 11 is expressed as shown in FIG. 19<A),
The resolution S1 of the signal is the dynamic range D of the signal.
Since it is expressed as dividing by the number of steps determined by the number of bits, S+=D/1024. Since this is the resolution of the entire signal, the color burst signal also has the same resolution.

Here, the lower 1 bit of this signal is sent to the bit reduction circuit 15.
If the number of steps is reduced in , the number of steps becomes 512 as shown in FIG. 19(B), and the resolution deteriorates. That is, if the resolution of the signal passed through the lower bit reduction circuit 153 is 82, then 52=D1512. At this time, if we remove the upper 1 bit of the color burst signal part, we get
The resolution S3 of the color burst signal portion remains unchanged, and the waveform of the entire signal becomes as shown in FIG. 19(C).

That is, S+ =83 =D/1024.82 =D
1512, making it possible to reduce bits without deteriorating the resolution of the color burst signal portion.

In other words, the resolution of the color burst signal portion can be improved when bits are reduced.

Next, considering the case where the bit reduction circuit 15 performs 2-bit reduction, the lower 2 bits of the signal shown in FIG.
(bit reduction), the overall waveform becomes as shown in FIG. 20(A). In this case, since the signal amplitude to be transmitted is from O level to 255 levels, the color burst signal will exceed this level. Therefore, as shown in FIG.
An adder 155 is provided at the subsequent stage to apply an offset to the color burst signal portion, and by shifting up the signal level by 64 steps, the color burst signal is adjusted to the above level as shown in FIG. 20(B). It can be contained within. As a result, Sz =83=D/1024
．． 82=D/256, which is the resolution of the color burst signal portion.

In this way, by reducing the upper bits of the color burst signal and the lower bits of the square part, bit reduction can be performed without deteriorating the resolution of the color burst signal, so the color burst signal itself can be reduced. SN ratio worsens, -+? -1jj+Kouzusha r#sukorutnimasa Toria 1m l1fl? ``This means that phase detection based on the color burst signal can be performed more accurately.

Note that in the above configuration, the upper bits are reduced only with respect to the color burst signal, but it is also possible to reduce the upper bits with respect to the horizontal synchronization signal. That is, as shown in FIG.
Adders 1558 and 155k) that apply mutually different offsets to the output signals of 50 and upper bit reduction circuits 151a and 151b that reduce the upper bits of the signals to which offsets have been applied by these adders are provided. Here, the configuration is such that any one of the outputs of the upper bit reduction circuits 151a, 151b and the lower bit reduction circuit 153 is selected. Then, based on the select signal output from the system controller 18, the selector 1
54 is switched and controlled as shown in FIG. 22(B) for the color television signal shown in FIG. 22(A).

Here, the lower 1 bit G- of the signal shown in FIG.
The number of steps becomes 512 as in the case of 11υ and 1q and 1q, and the resolution deteriorates. At this time, the horizontal synchronization signal is 128. By adding an offset by the amount of the step and then reducing the upper 1 bit of each, the resolution of the horizontal synchronization signal and color burst signal remains the same as before the bit reduction, and the waveform of the entire signal is as shown in Figure 23 (A). become. Similarly, when reducing the lower two bits of the signal shown in FIG. 19(A), in order to avoid exceeding the signal amplitude range, the horizontal synchronization signal is reduced by 198 steps, and the color burst signal is reduced by 64 steps. By applying an offset to each signal and then reducing the upper 1 bit of each, the bits can be further reduced without changing the resolution of the horizontal synchronization signal and color burst signal, as shown in Figure 23 (B). This means that it can be transmitted as a waveform. As a result, there is no deterioration in the S/N ratio not only for the color burst signal but also for the horizontal synchronization signal, and synchronization detection in subsequent circuits can be performed more accurately.

The bit reduction circuit 15 calculates no (bit/word) (
7) The data whose bits have been reduced from Qi'1 to data of n + (bits/word) is supplied to the petestal detection circuit 13 and the signal separation circuit 14. If such processing is performed, the signal waveform will be different from the standard NTSC signal waveform, so the lower bits of the color burst portion are reduced through a lower bit reduction circuit 48 at the subsequent stage of the buffer memory 39, which will be described later. I'm trying to return it to a waveform.

When performing digital signal processing, it is clear that a smaller number of quantized bits per word n (bit/word) is advantageous in designing a circuit. However, when considering the FM detection output, the output level is constant in the steady state of the disc player, but it is unsteady due to the rise of rotation of the spindle motor 24, search and scan during CLV (constant linear velocity) disc playback, etc. In the state,
The DC component of the video signal changes significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle motor circuit 23 cannot be locked, and the clock generation circuit 2
1, synchronization becomes impossible and the steady state cannot be maintained forever, so it is necessary to be able to detect the synchronization signal even in the unsteady state. For this purpose, the number of bits n must be set based on the unsteady state.

Therefore, at least the number n of bits from the input of the signal separation circuit 14 to the output of the de-emphasis circuit 11 is set to a number of bits with a wide dynamic range that is sufficient even if the pedestal level changes significantly based on the unsteady state. n
Set to 1 (bit/word). This allows the signal separation circuit 14 to reliably detect the synchronization signal from the FM detection output that has passed through the de-emphasis circuit 11, not only in a steady state but also in an unsteady state.

The pedestal level detection circuit 13 detects the pedestal level V
Detect po and determine the vedestal level from the reference voltage VRF) Lt
Reduce Vpo and generate output (VRF-VP o ),
An adder 12 adds the signal to the digital video signal and clamps the pedestal by canceling the variation in the pedestal level. Pedestal clamped n + (bit/wo
The data of n 2 (
Bits are reduced to (n2 bit/word) data.
<rll). n2 is determined by the dynamic range and resolution required for the video signal in a steady state. This bit reduction facilitates the circuit design of the adder 2 and subsequent parts. Furthermore, by performing pedestal clamping, the signal level of the digitized video signal is n 2 (bit/wor) not only in a steady state but also in an unsteady state.
Since it falls within the guipmic range of d), C
This means that images can be viewed even in an unsteady state such as during LV scanning.

In the above configuration, regarding the dynamic range of each circuit constituting the digital signal processing system, the dynamic range up to the input of the signal separation circuit 14 is set to n+ (bit/word), and regarding video processing, the dynamic range of each circuit constituting the digital signal processing system is After pedestal clamping, n 2 (bit/
bit reduction to word) and dynamic ratio%, M +
-m /-j-I +-21-1+-Ae 1^t
p t= -;, #To, the output of the digital FM detection circuit 7 is separated into two systems: a video processing system and a signal separation system,
It is also possible to make the number n of bits of the platform different.

That is, in FIG. 10, the number of bits n of the signal separation system
is the number of bits n + with a wide dynamic range that is sufficient even if the pedestal level changes significantly in an unsteady state.
(bit/word). This n + (
The data (bit/word) is supplied to the signal separation circuit 14 via the LPF1 6. The L and PF 16 may be any filter that has characteristics that allow the synchronization signal to be detected from its output, and therefore the configuration can be simplified by using simplified filter coefficients. On the other hand, regarding the video processing system, the number of bits n 2 (bit
/word) dynamic range. n2
is determined by the dynamic range and resolution required for the video signal in steady state.

In this way, the digital FM detection output is nl.

By separating the n z (bit/word) into two systems, the circuits after the video LPF 10 can be set up by considering only the steady state case, which simplifies the circuit configuration and also allows the spindle This means that the b synchronization signal can be reliably detected in an unsteady state such as when the uplink 24 rises.

In addition, in such a circuit configuration, in an unsteady state, it may be impossible to see the image (3) due to a change in the pedestal level, but this means that the image can only be seen in a steady state, and it is possible to reliably receive the same picture signal in an unsteady state. This is based on the idea that it is sufficient if it can be detected. However, in the CLV scan, since the clock generation circuit 21 is synchronized to some extent,
Changes in the pedestal level are often small, and in this case you can also see the image.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit 13. In this figure, LPFI
The digitized video signal (a) from which the color burst has been removed in step 17 is supplied to a pedestal sampling circuit 118 and a sync separation circuit 119, respectively. Synchronous separation circuit 1
At step 19, the synchronization signal (b) included in the digital video signal (a) is separated and extracted, and the synchronization signal (b) is supplied to a rise detection circuit 121 and a fall detection circuit 120, respectively. The falling detection circuit 120 receives the first gate signal @(
The rising edge detection circuit 121 detects the fall of the synchronizing signal (b) during the generation period of signal C), and the rise of the synchronizing signal (b) during the generation period of the second signal 1 to signal (d).

The timing signal generation circuit 122 generates a first gate signal (C ), and then generates a dropout detection signal @(q
) is not generated, the second gate signal (d) is generated.

In the sample period signal generation circuit 123, a sample period signal (e) of a certain period is generated in response to the detection output of the rising edge detection circuit 121, and the pulse generation pulse generation control circuit 124 generates a sample period signal (e) from the sample period signal generation circuit 123, for example. a three-man power AND gate 125 which receives as input the ripple period signal (e) and the dropout detection signal 5% (Q);
An SR flip-flop that uses the detection output of the rising edge detection circuit 121 as a set (S) input, the output of an AND gate 125 as a reset (R) input, the clock signal as a clock (CK) input, and its Q output as the output of the AND gate 125. The output pulse of the AND gate 125 is supplied to the pedestal sampling circuit 118 as a sampling pulse (f). The pedestal sampling circuit 118 is composed of a D-type flip-flop or the like, and latches the pedestal level Vpo of the digitized video signal in response to the sampling pulse (f). The sampled pedestal level Vpo is subtracted from the reference level VRF by the arithmetic circuit 127 and averaged among the plurality of tors, resulting in a detection output of the (VRF-VP o ) level.

#r 1 /'l Hill 71- r-1 Ri 111 E
';+ n) amount ri /n th th hair I
n6 mm τ, ; - Figures 1 (a) to (g) correspond to the waveforms of each part (a) to (CJ) in Figure 11, respectively.

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the fall of the horizontal synchronization signal included in the synchronization signal (b) is detected by the first gate signal (C), and this fall is set as 1 to signal the horizontal synchronization signal. After a time corresponding to the width, a second gate signal (d) is generated to detect the rising edge of the horizontal synchronizing signal (b), and the sample period signal (e
), it is possible to reliably capture the horizontal synchronization signal and sample the pedestal level on the back porch during the horizontal blanking period. Further, since the color burst is removed from the digital video signal Q(a) by the LPP1 17, it is possible to generate a sample period signal (e) having a wide period including the portion where the color burst was present.

The sampling pulse (f> is the sampling period signal (
It is generated during the generation period of e) and the non-occurrence period of the dropout detection signal (g), and has a pulse width corresponding to one clock of the clock signal. Therefore, if there is a dropout shorter than the sample period, then Fig. 12 (f
), it is possible to reliably sample one clock per clock without the influence of dropout. Also, 1st. Second gate signal (C).

(d) is generated excluding the part where dropout occurs, so even if a false horizontal synchronization signal is generated due to dropout, a sample period signal will not be generated erroneously based on this horizontal synchronization signal. It is.

Output of pedestal level detection circuit 13 (VRF-Vpo
) is added to the video signal by the adder 12 shown in FIG. 1(B), thereby performing pedestal clamping. Further, the pedestal level Vpo is also supplied to the signal separation circuit 14 in FIG. 1(B), and in this circuit 14, synchronization signals and control signals are separated using the pedestal level Vpo as a reference level.

Note that in the above configuration, the LPF 117 in the input portion can be omitted, but if omitted, it is necessary to generate the limp period signal in a period other than the color burst portion. Furthermore, the configuration of the pulse generation control circuit 124 is not limited to the circuit configuration described above, and various configurations are possible, such as using a microprocessor, for example. Also,
The LPF 117 and the synchronous separation circuit 119 are connected to the second
In FIG. 1, the P F 145·a and the signal detection circuit 145C can each be replaced, and these circuits may be used in common.

FIG. 13 shows the falling detection circuit 12 in FIG.
An example of a specific circuit configuration of the 01 rise detection circuit 121, the timing signal generation circuit 122, and the sample period signal generation circuit 123 is shown. In this figure, the fall detection circuit 120 includes a D-type flip-flop 128 that receives the synchronization signal (b) as a data (D) input and a clock signal as the clock input, and an inverter 129A that receives the synchronization signal (b) as an input. , Q mountain of flip-flop 128-
1-, h nosa 1. 1-PE port 6 μ, opening 100 main ports] 3-man power NAND gate 129B that uses the gate signal (C) of small 1 and the output from the inverter 129A as 3-man power
The Q output of the flip-flop 128 is the synchronizing signal (b) delayed by one clock, and the Q output of the flip-flop 128 is the synchronizing signal (b) delayed by one clock.
In the AND gate 129B, when the synchronization signal (b) falls while the first gate signal (C) is at a high level, that is, the horizontal synchronization signal falls, 3
All human power is at a high level, and a low level detection output is generated.

The timing signal generation circuit 122 includes the falling detection circuit 1
1H counter 130 which takes the detection output of No. 20 as a load (L) input and a clock signal as a clock input, and the output of this counter 130 is decoded and the first.
It is composed of a gate circuit 131 that generates second goo 1 signals (c) and (d). The 1H counter 130 counts the IH period clock in synchronization with the falling edge of the horizontal synchronization signal, and the 1H counter 130 counts the IH period clock in synchronization with the falling edge of the horizontal synchronization signal.
``Kai Hakuguchi'' / 2h< 1 A 5 M l-17=
l f c, r: =, Q10f1((fH is the horizontal scanning frequency) and becomes a 910 progress counter. Also, during the period when dropout occurs, the gate signal Q(C
), (d) will not occur.

Although not shown in the figure, if the 1H counter 130 is not loaded several times in succession, the first gate signal (C) is forced to a high level and the horizontal synchronization signal rises. to be detected. This means that the 1F1 counter 130 is shifted by 1/2H due to the equalization pulse.
This is to prevent loading by the horizontal synchronizing signal from being carried out thereafter and making it impossible to detect the pedestal level.

The rising edge detection circuit 121 is the timing signal generation circuit 1
22 as a data (D) input and a synchronization signal (b) as a clock input, the second gate signal (d)
When the signal (b) rises, that is, the horizontal synchronizing signal rises while the signal (b) is at a high level, a high level detection output is generated from the Q output terminal. Sample Akima signal light cow circuit 1
23 loads the detection output of the rising edge detection circuit 121 (
L) Consists of a 7-bit counter 133 with input and enable (EN) input, which is loaded with ``90'' until just before the rise of the water weight + 111 signal, starts counting at the rise of the horizontal synchronization signal, and is loaded with ``96''. ″～゛127
Sample period signal (e) with the period “ as the ripple period
Output. Callan 1~ exceeds '127' and 'O11'
When this happens, the D-type flip-flop 132 is cleared and the load input and enable input are set to low level, returning to the load state and stopping.

The fall detection circuit 120 and the timing signal generation circuit 122 may be part of the 1-4 separation circuit 145d in FIG. 28 and a timing signal generation section of the system controller 18 in FIG. 38, which will be described later. Detecting the fall of the horizontal synchronizing signal in the HV separation circuit 145d, replacing the D-type flip-flop 180, inverter 181A, and NAND gates 1 to 181B in FIG. may be shared by the 1H counter 183 and the gate circuit 182A in FIG. 38, respectively.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 13, in which parts equivalent to those in FIG. 11 are designated by the same symbols. In this figure, LPFl
The synchronization signal @(b) separated and extracted by the synchronization separation circuit 119 from the digitized video signal (a) which has passed through the digital video signal (a) through the synchronization signal 17 is supplied to the fall detection circuit 134. The fall detection circuit 134 detects the fall of the synchronization signal (b) during the generation period of the gate signal (C) output from the timing signal generation circuit 135, and supplies the detection output to the timing signal generation circuit 135.

The timing signal generation circuit 135 generates a gate signal (C) based on the clock signal during the period when the drop error/detection signal (f) is not generated, and furthermore, the falling edge detection circuit 134 generates a gate signal (C) based on the falling edge detection timing.
Later horizontal synchronization signal "1 SI +, →', -
:f I-5) IX -r H1/ -t If,
Hatsunday β-eye ``1 /As N's departure,
It is supplied to the pulse generation control circuit 136.

The pulse generation control circuit 136 includes, for example, a three-man power AND game h 137 which inputs the sample period signal (d) and the dropout detection signal (f) from the timing signal generation circuit 135, and a set signal from the timing signal generation circuit 135. Set (S) input, reset (R) input the output of AND gate 137, set the clock signal to the clock (GK
) and an SR flip-flop 138 whose Q output is used as an input to an AND gate 137,
The output pulse of the D gate 137 is converted into a sampling pulse (e
) to the pedestal sampling circuit 118. The subsequent operations are the same as those shown in FIG.

Figure 15 shows the operating waveforms of the circuit in Figure 14, and Figures (a) to (f) show the waveforms of each section (a) to (f) in Figure 14, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 14, the falling of the horizontal 1I11 lip is detected at the gate I/M (C), and a set signal is generated based on this rising edge to inquire the AND gate 137. After that, the ripple period signal (d) is generated corresponding to the front position of 1hNU, so that the pedestal level can be detected during the vertical blanking period. Further, after sampling the pedestal level, if the falling edge of the horizontal synchronizing signal cannot be detected while the gate signal (C) is being generated, the falling edge detection circuit 134 generates a pedestal enable signal to detect the sampled level. It is possible to notify the next stage circuit that the pedestal level is invalid, or to hold the previously detected pedestal level. for example,
By inputting the pedestal enable signal to the performance circuit 127, the circuit 127 previously outputs (VRF
-VP D ) continues to be output.

The gate signal (C) and the ripple period signal (d) are generated except for the part where the dropout occurs, and the pulse generation control circuit 136 generates the sampling pulse (e) for one clock, so the drop error 1 without accidentally generating the sample period signal 1) by
If the quality of dropout during the 4j sample period does not exceed the V sample period, sampling for 1 clock per 1H can be ensured without the influence of the drop error 1~, as shown by the two-dot chain line in Fig. 15(e). can be done.

As for the example of diversion, the same aspect as in the case of the configuration shown in FIG. 11 can be considered.

FIG. 16 shows the falling detection circuit 13 in FIG.
4 and a specific circuit configuration of the timing signal generation circuit 135 are shown. In this figure, the fall detection circuit 134 is a JK flip-flop 1 which receives the synchronization signal (b) as an inverted clock input and receives the gate signal (C) as the J input.
39, when the synchronization signal (b) falls, that is, the horizontal synchronization signal falls during the period when the signal (C) is at high level, the Q output becomes high level, and from then on, the reset signal becomes low. The Q output is held at a high level until it transitions to a high level. When the reset signal goes low, the Q output also goes low.

The timing signal generation circuit 135 includes a D-type flip-flop 140 which uses the Q output of the JK flip-flop 139 as a data (D) input and a clock signal as a clock input, and a D-type flip-flop 140 that uses the Q output of the flip-flop 140 as a D input and a clock signal as a D input. D-type flip-flop 141 as clock input
and load the ○ output of this flip-flop 141 (L
) input, a clock signal as a clock input, and a gate circuit 143 that decodes the output of this 1F1 counter 142 and generates a gate signal and a reset signal in a predetermined period. Immediately after the output becomes high level, a load pulse is generated for one clock from the D-type flip-flops 140 and 141 to load the 1H counter 142, which causes the 11-1 counter 142 to respond to the falling edge of the horizontal dome signal. When the video signal is NTSC, the 1H counter 142 counts the 1H period in synchronization with the NTSC clock.
．． 3MHz = 4fsc = 910fH (f+ is the water gate circuit 143, and the gate signal (C) is not generated during the period when dropout occurs. Also, the reset signal is generated so that the pedestal enable signal is recognized by the next stage circuit. 1H, keeping a sufficient distance from the gate signal (C).
It is generated as one pulse.

Note that in the circuit shown in FIG. 16, the gate signal (C) is reduced to 1/2 due to the loading of the 1H counter 142 by the equalization pulse.
Measures similar to those shown in FIG. 13 are taken to prevent H deviation.

In addition, the circuit in FIG. 16 can be replaced or shared with the HV separation circuit 145d in FIG. 28 and the circuit in FIG. 38, as in the case of FIG. 13.

In each of the embodiments of the pedestal level detection circuit 13 described above, the video signal was described as being digitized, but the application is limited to digital video signals and is not applicable to analog video signals. It can be applied in the same way.

Next, the dropout correction circuit 19 in Figure '5S1 (B) will be explained. This dropout correction circuit 19 corrects the dropout of the digitized video signal output from the filter 12, but regarding the dropout of the vertical synchronization signal portion, it is set to a level equal to the signal level of the vertical synchronization signal in advance. Dropout correction is performed by replacing the set correction signal.
It has become a reality.

The configuration of this dropout correction circuit 19 is shown in FIG. In this figure, the digitized video signal is supplied to the first selector switch 190, and the output of the switch 190 is passed through the first delay circuit 191 to the second delay circuit 1.
92 and 3.58 MHz BPF193.

Here, when the delay amount of the BPF 193 is set to d, the delay amount of the first delay circuit 191 is set to ll-1-d, and the delay m of the second delay circuit 192 is set to d. The output of the BPF 193 is passed through a multiplier 194 with a coefficient of -2 to a filter 1.
95 and added to the output of the second delay circuit 192. The addition output of the adder 195 is sent to the second changeover switch 1.
96, the output of the switch 196 becomes an input other than the first changeover switch 190. The first changeover switch 190 is controlled by a dropout detection signal supplied from the dropout detection circuit 17 (see FIG. 1(A)).

The address generation circuit 197 generates a field identification signal, horizontal address, and vertical address based on the horizontal communication signal 9 and vertical synchronization signal supplied from the signal separation circuit 14, and the vertical synchronization level generation circuit 198 generates a field identification signal, a horizontal address, and a vertical address based on the address information. A correction signal is generated which is set to a level equal to the signal level of the vertical synchronization signal known from
It serves as an input in addition to the changeover switch 196. In the switching signal generation circuit 199, a vertical synchronization period signal is generated during the generation period of the vertical synchronization signal based on the vertical address, and this vertical synchronization period signal becomes a switching signal for controlling the switching of the second changeover switch 196.

By the way, as shown in FIG. 25, the signal (A) before correction
If dropout occurs in the vertical synchronization pulse part of ) may cause a positional deviation of the vertical synchronizing pulse (in FIG. 25, a positional deviation of ``c1/2H'' between the ○ marks has occurred).

If the position of the vertical synchronizing pulse is shifted in this way, there is a possibility that a field error will occur in the subsequent video imager. However, prohibiting vertical synchronization pulse dropout correction may cause synchronization disturbance.

Therefore, as shown in FIG. 24, when a dropout occurs in the vertical synchronization pulse portion, the signal level of the vertical synchronization signal output from the vertical synchronization level generation circuit 198 instead of the previous signal is By supplying a correction signal with a level equal to that of the first selector switch 190 and replacing the digitized video signal with this correction signal, dropout correction can be performed without causing a positional shift of the vertical synchronizing pulse. Gashi: In Fig. 24, dropout correction is performed using the signal of the 1st song, but at this time, the phase of the chroma signal will become reversed if left unchanged. Therefore, the second
The circuit surrounded by the broken line in Figure 4 inverts the phase of the chroma signal, thereby making it possible to colorize the dropout correction signal. Therefore, when dropout correction is performed only on a luminance signal (monochrome), when a signal 2H earlier (clock signal is in phase), etc., the circuit shown in the broken line is excluded. The address generation circuit 197, vertical synchronization level generation circuit 198, and switching signal generation circuit 199 may be included in the system controller 18, and replaced with the 1H counter 183° gate circuit 182A, 1 frame counter 189° gate circuit 182B, etc. in FIG. You may.

The dropout detection circuit 17 in FIG. 1(A) has a level comparator configuration, and as shown in FIG. Association (A)'s T Tsume n
1 m
~Outputs a detection signal <C). According to this ti4 generation,
Since the dropout detection circuit can be configured by adding a level comparator to the FM detection circuit 7, dropout detection can be reliably performed with a simple circuit configuration, and all detection operations are performed digitally. Therefore, stable characteristics can be obtained.

Note that there is a possibility that the detection output will be disturbed due to ringing (the area surrounded by a dashed line in FIG. 26(B)) that occurs in the output of the sum-of-squares circuit 72 due to a sudden change in the envelope. By outputting the dropout detection signal (D) as a dropout section also at 1nn1 point where the signal level of the output signal (B) of 72 becomes below a predetermined value and at n2 points after the level becomes above the predetermined value. , subsequent corrections can be executed reliably. At this time, there is a possibility that ringing will occur due to the delay of the Hilbert transformer 70, so nl.

n2 is set equal to or larger than the delay time n of the delay circuit 71.

In the signal separation circuit 14 in FIG. 1(B), the control signal 11 of the frame number and stop code signal, along with the color verse signal, horizontal sync signal, vertical bright signal, etc. included in the digitized video jq and signal P, is processed. Separation and extraction is performed. For this signal separation, as shown in FIG. 27, the first reference level VTH for separating and extracting the control signal @A is
I and a second 1-level VTH2 for separating and extracting the synchronization signal B are set.

The configuration of this signal separation circuit 14 is shown in FIG.

In this figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum level of the digitized video signal within a predetermined period. The configuration of the minimum value detection circuit 20 will be explained in detail later. Based on each detection level of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the first. Second reference level VTI
-11°VT)-12, the reference level generating circuit 140 adds a constant value to the detected level of the pedestal level detecting circuit 13 to set the first reference level VTHI. The reference level generation circuit 141 is connected to the pedestal level detection circuit 1.
3 and the detection level of the minimum value detection circuit 20, an intermediate value between both levels is generated as a second reference level VTI-12. The reference level generation circuits 142 and 143 generate the first. Second sublevels VTHI and VTH2 are generated.

Each output of the Wl level generation circuits 140 to 143 is supplied to a selector 144, and when the synchronization establishment determination signal is supplied from the system controller 18, that is, when the synchronization is stable, the selector 144 selects the reference level generation circuit 140. , 141. second reference level V
TH1 and VTH2 are selected, and for other cases, that is, when the synchronization is unstable, the first . It is determined whether or not synchronization is established by comparing the extracted synchronization pulse with a reference synchronization pulse based on the second reference level VTHI, VTI-12 based on the internal clock. The first one selected by the selector 144.
The second reference level VTI-11°VTI,z is supplied to the signal detection circuit 145C, and the signal detection circuit 145C detects the LPF based on these reference levels VTH1, VTH2.
The control signal A and the communication signal qB are separated and extracted from the digitized video signal passed through the digitized video signal 145a.

That is, in the signal separation circuit 14 configured as described above, when the daily cycle is stable, the pedestal level and the first . The second reference level VT81, VTI-12 is set to Ml, and when the rotation of the spindle motor 24 starts or C
When synchronization is unstable, such as during LV disk search or scanning, the pedestal detection position is not determined and its value is not determined, so the first. Second reference level VTHI, set VTH2 to Ht
I-'l-11! An J= Q A T1
．． 7f I"1 1ill 1.- 0 0 /
1) 51111t i city '4J zte (y nawareru. According to this, the signal valve 2B will be operated stably and reliably not only when synchronization is stable but also when synchronization is unstable. Separated synchronization Signal B is HV separation circuit 1
45d and H from the system controller 18.
The horizontal synchronization signal is separated by detecting a falling edge when the S game signal is at a high level. Also, synchronization signal B
is subjected to integration processing in the HV separation circuit 145d, and a vertical synchronization signal is separated based on a predetermined reference level. The digitized video signal is sent to fscBPF1 along with LPF145a.
45b, and a color burst signal containing a color signal component is output from fSCBPFl 45b.

By the way, regarding the detection of the synchronization signal in the signal detection circuit 145C, as shown in FIG. 29, the digitized video signal is sampled at every predetermined clock (the X mark in the figure is the sample point), and the signal level of the synchronization signal is at the reference level. The synchronization signal is detected at the time when the difference signal 12 is exceeded.

The configuration of this synchronization signal detection circuit is shown in FIG.

In this figure, a basic i1E level generation circuit 141 (or 1
43) Kara (1) WFjF-Level VTH2 and HiL
, PF 145a, the subtracter 146 calculates the level difference between the signal level of the video signal and the reference level VTI-12 at each sample point, and determines whether the video signal level is equal to the reference level VT.
) -12 is detected as a synchronization signal. The level difference signal calculated by the subtracter 146 is sent to a delay circuit 147, a sign determination circuit 148, and a ROM (read/write).
(only memory) is supplied to the memory device 149 of the memory.

The delay circuit 147 has a delay element corresponding to one clock, and delays the level difference signal from the subtracter 146 and supplies it to the sign determination circuit 148 and the storage device 149. Sign determination circuit 1
48 indicates that the output Δ of the delay circuit 147 is positive and the subtracter 146
The output B of the delay circuit 147 is in a negative state, that is, the level difference at the ripple point a just before the output A of the delay circuit 147 exceeds the reference level VTH2, and the output B of the reduction fliW146 is at the reference level VT.
) It is determined that there is already a level difference at the sample point immediately after exceeding -12, and a determination signal is supplied to the storage device 149.

For example, a time table as shown in FIG. 31 is stored in advance in the storage device 149, and the storage device 149 stores the outputs of the delay circuit 147 and the subtracter 146 when the determination signal is generated from the sign determination circuit 148, That is, corresponding time information is output based on the level differences A and B at the two sample points a and b. Input A of the storage device 149;
B and the output are both 4-bit data, for example, and the first 1 bit of the 4 bits of inputs A and B is a sign bit and is expressed as a two's complement number. Storage device 14
The time information that is the output of 9 is the time point C when the signal level of the synchronization signal exceeds the reference level VTH2 and the sample point a or b.
What is the time difference? This makes it possible to accurately detect the position of the falling edge of the synchronization signal even if the time point C does not coincide with the sample point in time.

Next, the minimum value detection circuit 20 in FIG. 28 will be explained. In FIG. 32, a first period pulse is generated in the middle of the day corresponding to the 21st day of the counter, and a second period pulse is generated every period longer than the period equivalent to one day. These period pulses are supplied to the selector 201, and the first period pulse is used in a steady state, and the second period pulse is used in an unsteady state where the rotation of the disk is unstable, such as when the spindle motor 24 starts rotating, or when a CLV search or scan is performed. Pulses are selected and provided to register 202 and averaging circuit 203. The axis ratio device 204, which uses the digitized video signal output from the LPF 145a, compares its input data A and data B stored in the register 202 every time a clock occurs, and stores the smaller data in the register 202. supply to. However, the comparator 204 is designed to stop its operation when a dropout phrase occurs. register 2
02 is reset by the first or second period pulse supplied from the selector 201, so the register 202
The smallest value from the previous value setting will be stored in . The minimum value stored in register 202 is the first
Or, it is loaded into the averaging circuit 203 at the generation angle of the second period pulse, and the averaging circuit 203 averages each minimum value of two or more detection periods and calculates r? Output as the minimum value.

In such a configuration, in a video signal, a minimum of 1 shift normally appears during the synchronization signal period, so a 1H period is set as the detection period (first period pulse generation interval). Time and CLV
In an unsteady state such as during a search or scan, the rotation of the disk is not stable, so the length of one day period changes.

At this time, if minimum value detection is performed at normal intervals based on the first period pulse, there may be cases where the synchronization signal is not included within the interval. Therefore, in the J1 steady state, by using the second period pulse that is generated every period longer than the 1H light interval, the synchronization signal is included within the detection period, so the minimum level can be reliably detected. This means that the variation in the minimum value level can be reduced. Also, when a dropout occurs, a value that is temporarily lower than the signal level of the synchronization signal may occur;
- section, by stopping the operation of the comparator 204 and prohibiting the detection operation, it is possible to prevent erroneous detection of the minimum value.

In addition, the counter 20 is activated by the drop alarm 1~detection signal.
0 is reset, and the counter 200 starts the predetermined period of clocking l~ again for the dropout pulser 1. Therefore, even if the synchronization signal part is lost due to a dropout, the synchronization signal will be reliably synchronized by the time the next period pulse is generated. The level of the signal part can be detected.

The clock generation circuit 21 in FIG. 1(B) operates at 4 fsc (fsc is the subcarrier frequency) based on the reference horizontal dome signal from the reference signal generator 22 or the horizontal synchronization signal or color burst signal from the signal separation circuit 14. and 4Nf'sc (for example, 12fsc), and has a PL, L (phase locked loop) circuit configuration. The 4fsc and 4NfsC clocks generated here are used as clocks for digital signal processing, and the sampling clock of A/D converter 4 and the clock for signal processing up to video L and PF 10 are set to 4Nfsc, L P F 1
Downsampling is performed from an output of 0 to 4fsc.

The configuration of the clock generation circuit 21 is shown in FIG.

In this figure, a phase comparator 210 that uses a color burst signal as a comparison reference input is connected to a sampling pulse generation circuit 21.
1, the sampling pulses CK+, C
Phase comparison is performed in response to K2. Note that when locking the PLL to the reference horizontal synchronization signal or the horizontal synchronization signal, the phase comparator 210 is not used, and another phase comparator (not shown) is used to lock the PLL to one of these signals at 2fs.
The phase is compared with the signal of f+-+ which is 1/455 of c, and the output thereof is input to the LPF 212.

Hereinafter, only the case of locking to the color burst signal will be explained. The comparison output of the phase comparator 210 is LPF2
The signal is supplied to the D/A converter 213 via the signal line 12, where it is converted into an analog signal and becomes a control signal for the VCO (voltage controlled oscillator) 214. The oscillation frequency of VCO214 is 12fsc
and 4 fs with the 1/3 frequency divider 215.
The frequency is divided into c. This clock 4f'sc is output 42 as it is, serves as the sole power of the sampling pulse generation circuit 211, and is further divided into f'sc by 1/2 frequency dividers 216 and 217, and is used as a comparison input of the phase comparator 210. Become. The sampling pulse generation circuit 211 is supplied with the gate pulses generated by the gate pulse generation circuit 218 as individual inputs, and therefore, the phase comparator 210 receives the υ combining pulses CK+, CK+ only during the generation period of the gate pulses.
CK2 will be supplied. The gate pulse generation circuit 218 synchronizes with 4fSC based on the horizontal synchronization signal, and generates a gate pulse (B) only during a period corresponding to the central portion where the amplitude of the color burst signal (A) is constant, as shown in FIG.
) occurs.

In the phase comparator 210, as shown in FIG.
The color burst signal becomes the output of the adders/subtractors 219 and 220, and each addition/subtraction output is sent to the adders/subtractors 219 and 220 via delay circuits 221 and 222. Adjustment device 219, 220
Addition/subtraction (±) control is performed based on the clock pulse fsc (B) shown in FIG. 36 so that addition occurs at the input points S+ and S2, and decrease occurs at the input points S3 and S4. When a track jump is performed during still image playback, etc., the phase of the color burst signal changes to 180 degrees.
.degree., so the phase of the clock pulse fsc(B) is inverted every time there is a track jump to maintain locking of P L and L. This is done by controlling the 1/2 frequency divider 217 using a chroma inversion control signal supplied from the system controller 18 of FIG. 1(B).

In addition, the sampling pulse generation circuit 211GJ:D is composed of a flip-flop, and the sampling clock CK
+, CK2 are synchronized with 4fsc and have half the frequency and opposite phases to each other, and only when the gate pulse is at a high level, the contraceptive circuits 221 and 22 are activated, respectively.
2 clock.

As a result, assuming that the amplitude of the color burst signal (A) is A, ΣA sinθ is derived as the output of the delay circuit 221, ΣA CO3θ is derived as the output of the delay circuit 222, and tanθ is derived as the output of the divider 223. derived. Then, by passing this basic β output tanθ through the tan-' circuit 224, the phase difference θ is obtained.

That is, the phase difference θ in the phase comparator 210 can be calculated from the following equation.

θ=tan-' (Σ[(S+ -83)/(S2-
34)]) Here, S+=A-3inθ 52=A-
CO3θS3 =-A-sinθ34 =-A-C
05O By the way, as is clear from the above equation, if the amplitude A of the color burst signal (A) is not constant within 1], there will be a slight error in the detected phase difference θ, and the loop characteristics will change due to changes in the PLL loop gain. Change will occur.

However, in the clock generation circuit 21 described above, 81 to
Limp ring pulse CK+ for S4.

By applying a gate to CKz, phase comparison is performed only during a period in which the amplitude A of the color burst signal (A>) is constant, so that the above-mentioned problem does not occur.

In the above configuration, phase comparison is performed only in the central portion of the color burst signal by applying a gate to the sampling pulse, but it is of course possible to apply a gate to the color burst signal itself. . In this case, since it is a digital gate, only the central part of the color burst signal can be handled more accurately than an analog switch or the like. Furthermore, in FIG. 33, the arrangement relationship between the LPF 212 and the D/A converter 213 may be reversed.

In FIG. 1(B), a reference signal generator 22 includes a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronization signal. The spindle motor circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronization signal from the reference signal generator 22 and the horizontal synchronization signal from the signal separation circuit 14. In the chroma inversion circuit 25, the phase of the 1:τ chroma (color) signal is inverted in response to the calyx 1 in order to correct the color 1 norm i even during special playback such as stay (still) or slow play.

The configuration of this chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is sent to a one-day delay circuit 270.
, are supplied to the adder 271. After the signal level of the output of the adder 271 is halved by the level adjustment circuit 272,
It is supplied to a subtracter 273. The subtraction output of the attenuator 273 is supplied to the adder 275 via a phase linear acyclic digital BPF 274, and the addition output of the adder 275 is as follows.
The signal is supplied to the changeover switch 276.

The delayed output of the delay circuit 270 is transmitted through the p reducer 273 and the BPF2.
The signal is supplied to a delay circuit 277 having the same delay m as 74, and is also supplied to an adder 271 via a one-day delay circuit 278. The delayed output of delay circuit 277 is supplied to adder 275 and changeover switch 276. The changeover switch 276 is appropriately switched depending on the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).

With this configuration, a 2.3-line correlation comb filter is configured, and the '6& calculation output of the subtracter 273 is twice in reverse phase with respect to the delay output J (assumed to be Y+C) of the delay circuit 270. It becomes a chroma signal (-20) with a level of . After unnecessary components are removed from this chroma signal by the BPF 274, the delay output (Y+C) whose delay amount has been adjusted by the delay circuit 277 is added to the delay output (Y+C) by the adder 275, and the delay output (a) of the delay circuit 277 is A digitized video signal (b) having an inverted chroma signal is obtained as an additional output. For special playback such as stay and slow, set the changeover switch 276 to the system controller 1-〇- in Fig. 1(B).
Color framing can be maintained by switching the chroma inversion control signal from color 18.

In FIG. 1B, the output of chroma inversion circuit 25 is supplied to video processing circuit 38. In FIG. The video processing circuit 38 performs character insertion, MCA code suppression, squelch, etc. The digitized video signal that has passed through the video processing circuit 38 is written into three buffer memories using a 4fsc clock generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal.

Reading from this buffer memory 39 is performed by the 4fsc base rW clock generated by the reference clock generator 22. In this way, by reading data from the buffer memory 39 using a supplementary clock unrelated to the reproduced signal, jitter in the reproduced signal can be absorbed, and so-called tangential servo and color correction circuits can be used. No longer needed. The digitized video signal read out from the buffer memory 39 is converted into one analog word by the D/A converter 40 and sent to the output terminal 42 via the LPF 41.
is supplied to

The system controller 18 has the following main functions. That is, 1. Various servo systems are controlled in response to commands from operating units such as panel switches and remote controls, and state signals from the servo system, to cause the player to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generate signals for compositing frame numbers, chapter numbers, etc. onto the screen.

4. Synchronize the internal counter with the horizontal synchronization signal and vertical synchronization signal, and decode the output of the counter to generate various timing signals.

5. Control the PLL loop for clock generation. A specific configuration for realizing the fourth function among the above main functions will be described below.

In FIG. 38, the horizontal synchronization signal (H8) is converted to data (D
) input and the clock signal of 4f'sc as a clock (
A D-type flip-flop 180 is provided as input (CK), and the Q output of this flip-flop 180 is NA.
ND Gate 181B is the one-man power. The NAN'D gate 181B has the horizontal open signal (ji) supplied via the inverter 181A as another input, and its output becomes the load (L) input of the 11" counter 183. Gate circuit 1
82A decodes the output of the 1H counter 183 and generates the HS gate signal in a predetermined period,
nm/l'% l I l l C4IIInW1A RoA
+-1ヰ+ 廿IL-J+ 1-Generates a clock HCK having a frequency of fH synchronized with the horizontal synchronizing signal. The HS gate signal is used in the +-+V separation circuit 145d to detect the fall of the horizontal synchronization signal excluding the equalization pulse and to separate the horizontal signals. In the initial state, the HS gate signal is always at high level, and the HS gate signal goes to 1H at the fall of the synchronization signal.
The counter 183 is loaded and becomes high level only for a predetermined period so that the falling edge of the horizontal synchronizing signal is detected every day thereafter. In the initial state or for some reason,
If the 1H counter 183 is loaded due to the fall of the equalization pulse and a 1/2H shift occurs, the 1H counter 183 is not loaded after the vertical blanking period, so this state occurs in the system controller 18. This is detected and the HS gate signal is kept at a high level again. Note that the HV separation circuit 145d generates a pulse of a predetermined width based on the fall of the horizontal synchronizing signal, and outputs this as a horizontal synchronizing signal. Clock HCK
is the falling edge of the Domei signal (IP)-l, 7r
Spear master p6 1st novel 'II, f diagonally upward wart I no 1be'
11. , a signal with a duty ratio of 50%. The gate circuit 182A further generates various timing signals within 1('' and supplies them to each circuit.

The positive polarity vertical synchronization signal (VS) becomes each clock input of D-type flip-flops 184 and 185.

The D-type flip-flop 184 receives the S gate signal outputted from the gate circuit 182B as a data (D) input, and when the vertical synchronization signal rises while the signal is at a high level, its Q output goes to a high level. The Φ output becomes a low level and maintains that state until the reset signal becomes a low level. When the reset signal becomes a low level, the Q9 output is inverted.

The D-type flip-flop 185 receives the clock HCK output from the gate circuit 182A as a data input, and is used to determine whether the vertical synchronization signal is from field 1 or field 2.
Then, when the clock HCK is at a low level, the rising edge of the vertical synchronization signal arrives, so the Q output becomes a low level, the 0 output becomes a high level, and in field 2, the clock HCK is at a high level. ! I] <Since the rising edge of the M signal has arrived, the Q output becomes a high level and the ○ output becomes a low level. The Q output of the flip-flop 184 is used as data input, and the clock H
A D-type flip-flop 186 which uses CK as a clock input and uses the Q output of the flip-flop 185 as a clear input.
is the Q of flip-flop 184 in field 2.
When the output becomes high level, the Q
The output goes to high level, and in field 1, the Q output remains at low level.

The Q and C1 outputs of the D-type flip-flop 184 are J.

J- with K input, clock HCK as inverted clock input, and d output of flip-flop 185 as clear input.
The flip-flop 187 is D when field 1
When the Q output of the type flip-flop 184 becomes high level, the Q output becomes high level at the fall of the clock HCK.
During field 2, the Q output remains at a low level.

A NOR gate 188 that makes each Q output of the D type flip-flop 186 and the J- flip-flop 187 two-man power.
The next stage 1 frame counter 189
is loaded and the D-type flip-flop 184 is reset. Here, the reason why a load pulse is generated using a separate flip-flop for each field is to send a sufficiently wide load pulse to the one frame counter 189 in any field. 1 frame counter 189 counts clock HCK 52
It is a quinary counter and is loaded with the clock HCK when the output of the NOR gate 188 is at a low level.
It is controlled by the 0 output of the D-type flip-flop 185 so that the number is increased by the same amount.

The gate circuit 182B decodes the output of the one-frame counter 189 and generates the above-mentioned VS gate signal in a predetermined period, and also generates a timing signal for one unit within one frame and supplies it to each circuit.

Next, the above-mentioned 5A/I+ of the system controller 18
l Neryu (p, C 蓼(5nn4-hrv, t+h
The function for controlling the room/7'1Dl111°-p will be explained based on the flowchart of FIG. 39.

As mentioned above, these P L and L have two phase comparators, one for locking to the reference horizontal synchronizing signal or the reproduced horizontal synchronizing signal and the other for locking to the colorverse 1~ signal. The configuration is such that three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal at the input section of the former phase comparator, and by switching the phase comparator itself. In FIG. 39, in an initial state such as immediately after the power is turned on or when the spindle motor is forcibly accelerated, the reference horizontal synchronization signal obtained from the reference signal generator 22 (see FIG. 1 (B)), which serves as the reference for the spindle revolution, is first PLL to lock to
The loop operates (step 1). When it is determined that the loop is locked to the reference horizontal synchronization signal (step 2) and the horizontal synchronization signal becomes 17 times the reproduction video signal, the loop is switched to the reproduction horizontal synchronization signal (step 3). At this time, if it is determined that locking is not possible (step 4), the process returns to step 1 and the loop is returned to the reference horizontal circumference iV] signal. If it is determined in step 4 that it is locked to the playback horizontal synchronization signal, step 5) detects the presence or absence of the colorverse 1 signal. If there is no colorverse 1 signal, the process returns to step 4 and the playback horizontal synchronization signal is detected. Leave it locked. This state occurs during the vertical blanking period for both black and white discs and color discs. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). Here, if it is determined that it cannot lock to the colorverse 1 to signal, step 7
), returning to the playback horizontal synchronization signal loop in step 3,
If it can be locked, it will maintain the color burst loop state. However, at the same time, the synchronization with the playback horizontal synchronization signal must be monitored (Step 8). If either the lock with the color burst signal or the lock with the playback horizontal synchronization signal is lost, it is assumed that the lock is lost and the playback horizontal synchronization signal is looped. Return to (step 3). At this time, if the loop of the reproduced horizontal synchronization signal cannot be locked to the reproduced horizontal synchronization signal (step 4
), and then return to the 1m horizontal domei signal loop (step 1).

Note that a No determination in step 4.7 indicates that the lock cannot be locked within the predetermined period when passing for the first time.
When passing for the second time or later, it indicates that it is not locked.

°This system has been explained above while showing the specific configuration of each circuit.
A major feature is that all signal processing between the D/A converter 40 and the D/A converter 40 is performed digitally. in this way,
By digitizing signals, multi-functionality can be achieved, e.g.
Colorization of the monochrome dropout correction signal,
It becomes easy to perform chroma inversion, increase the precision of Y-C separation by introducing a frame memory, or reproduce still images using CLV.

In FIG. 1B, the circuits are arranged in the order of the adder 12, the dropout correction circuit 19, the chroma inversion circuit 25, the video processing circuit 38, and the buffer 7 memory 39, but the arrangement is not limited to this arrangement. For example, as shown in FIGS. 40(A) and 40(B), the order of "dropout correction circuit 19 + chroma inversion circuit 25", "video processing circuit 38" and "buffer memory 39" can be changed. It is. However, since the loading and reading of the buffer memory 39 are asynchronous, ['buffer memory 39
” followed by two other words (in the case of Figure 40 (B))
requires resynchronization or delay of the control and timing signals for the other two. In addition, if there is "1 dropout correction circuit 19 + chroma inversion circuit 25" after "video processing circuit 38" (in the case of FIG. 40 (A)), dropout occurs when characters are inserted in video processing circuit 38. A control signal is required to prohibit dropout correction using a single correction circuit for character parts.

Further, as shown in FIG. 41, R, G, and B separation can also be performed digitally, and the RGB separation circuit
3 is converted into an analog signal by a D/A converter 44 and sent to each analog output terminal 4 via an LPF 45.
6R, 46G, 46B [If you connect these terminals to the RGB input monitor TV (television), you can use the RGB branching and shunting circuit in the TV. Since this is not necessary, the image quality can be improved.

In addition, when using a digital TV that can input RGB as it is digitized, the digital signals separated by the RGB separation circuit 43 are directly input to each digital output terminal 47R, 47G, without going through a D/A converter. 47B.

In this RGB separation, in this system, the clock of A/D converter 4 is set to 4Nfsc (N is an integer of 2 or more).
Since the 4fsc clock is locked to the color burst signal of the video signal, RGB separation (demodulation)
can be done easily. Hereinafter, a case will be described in which demodulation is performed using the RY and BY signals, but the demodulation can be similarly performed using the I and Q signals.

In the NTSC system, the phase of the color signal is as shown in Fig. 42, and the phase of the color signal is quadrature two-phase modulated and multiplexed with the luminance signal. It is shown in the following formula.

Y= 0.30 R+ 0.59 G+ 0111B・
・(1>Also, the color signal C in the video signal is expressed by the following equation.

...(2) =iCO3(ωCt-1-33@) + Q 5in(ωct+33°)...(3) Here,
ωC is the angular frequency of the color carrier, ωC−2πx 3.
58 Ml-IZ.

When the phase of the sampling frequency of 4fsc is locked to the color burst signal at 06, Fig. 42 and (2) are obtained.
From the formula, each simple point is ±(R
-Y)/1.14, ±(BR)/2.03. Also, from equations (1) and (2), R, G, and B signals are obtained by 19. Furthermore, I.

±336 to the color burst signal to obtain the Q signal.
Alternatively, it is sufficient to lock the phase at ±576.

From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst (ji number).

In the above embodiment, the case where the system is applied to an NTSC video disc player has been described, but this system is applicable to VTR playback side signal processing, PAL, SEC
It can also be applied to AM video disc players and the like.

As explained above, according to the present invention, the FM video signal is digitized and all signal processing is performed digitally, so most of the circuits are digitized and L
Since it is suitable for SI, it is possible to reduce costs by employing workers for production, and the number of adjustment points is also significantly reduced, resulting in a reduction in manufacturing costs. Furthermore, by digitizing the FtVNIJl signal, various signal processing becomes possible, making multi-functionality and high image quality easy.

[Brief explanation of drawings]

1(A) and (B) are block diagrams showing one embodiment of the video signal reproducing device according to the present invention, FIG. 2 is a block diagram showing the specific configuration of the digital BPF in FIG. 1 (A>, FIG. 3 is a block diagram showing an example of the configuration of the video LPF in FIG. 1(B), FIGS. Figure 5 is the third
6 to 6 are block diagrams showing specific configurations of the amplifying circuit and IIR filter, FIG. 9 is a block diagram showing other configurations of video L and PF, and FIG. 10 is a block diagram showing the specific configuration of the IIR filter. FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit in FIG. 1(8); FIG. FIG. 13 is a block diagram showing the specific configurations of the falling detection circuit, rising detection circuit, timing signal generation circuit, and sample period signal generation circuit in FIG. 11.
Figure 14 is a block diagram showing another configuration of the pedestal level detection circuit, Figure 15 is an operation waveform diagram of each part in Figure 14, and Figure 16 is a falling detection circuit and timing signal generation in Figure 14. A block diagram showing the specific configuration of the circuit, and FIG. 17 is a diagram showing the burst gate signal Q (B) and selector switching state (C) for the color television signal (A) in the bit reduction circuit in FIG. 1(B). , 18th
The figure is a block diagram showing a modified example of the bit reduction circuit, a waveform diagram for explaining the circuit operation, FIG. 20 is a waveform diagram for explaining the circuit operation of FIG. 18, and FIG. 21 is the bit reduction circuit. 22 is a dimensional diagram showing the selector switching state (B) for the color video signal (Δ) in FIG. 21, and FIG. 23 is for explaining the circuit operation of FIG. 21. The waveform diagram of Fig. 24 is Fig. 1 (B)
25 is a waveform diagram for explaining the circuit operation of FIG. 24, and FIG. 26 is a block diagram showing the specific configuration of the dropout correction circuit in FIG. 1 (A>). FIG. 27 is a waveform diagram showing the relationship between the video signal and the reference level in the signal separation circuit in FIG. 1(B), and FIG. 28 shows the specific configuration of the signal separation circuit. FIG. 29 is a waveform diagram for explaining the operation of the signal detection circuit shown in FIG. 28, FIG. 30 is a block diagram showing the specific configuration of the signal detection circuit, and FIG. ROM in Figure 30
FIG. 32 is a diagram showing an example of a time table stored in the time table, and FIG. 32 is a diagram showing a specific f? 33 is a block diagram showing the specific configuration of the clock generation circuit in FIG. 1(B), FIG. 34 is a waveform diagram of each part in FIG. 33, and FIG. 36 is a waveform diagram for explaining the circuit operation of FIG. 35, and FIG. 37 is a block diagram showing the specific configuration of the chroma inversion circuit in FIG. 1(B). FIG. 38 is a block diagram showing the configuration of a part of the hardware for performing the predetermined functions of the system controller J3 in FIG. 1(B), and FIG. 39 is a flowchart of the predetermined functions of the controller. , Figure 40 (A
), (B) are block diagrams showing a modification of this system, FIG. 41 is a block diagram showing another modification, and FIG. 42 is a diagram of color signals used to explain the principle of RGB separation in FIG. 41. The phase characteristic diagram, FIG. 43, is a waveform diagram of the signal at each ripple point. Explanation of symbols of main parts 2...Analog LPF 4...A/D converter 6...Digital BPF 7...FM detection circuit 10...Video 1. P F13
... Pedestal level detection circuit 14 ... Signal separation circuit 15 ... Bit reduction circuit 17 ... Dropout detection circuit 18 ... System controller 19 ... Dropout correction circuit 21 ... Clock generation circuit 22 ... Reference signal generator 24...Spindle eater 25...Chroma inversion circuit 38...Video processing circuit 39...Buffer memory 40...D/A converter Applicant Pioneer Corporation

Claims (2)

[Claims] (1) A high-order bit reduction circuit that reduces the high-order bits of a digitized video signal subjected to digital FM detection; a low-order bit reduction circuit that reduces the low-order bits of the digitized video signal; A digitized video signal, comprising: a selection means for selectively outputting the output of the upper bit reduction circuit during a period when the amplitude of the video signal is small, and selectively outputting the output of the lower bit reduction circuit during a period other than the period. Bit reduction circuit in processing circuit. (2) A bit reduction circuit in a digitized video signal processing circuit according to claim 1, further comprising means for applying an offset to the digitized video signal input to the upper bit reduction circuit. .