JPS62271578A - Minimum value detection circuit in video signal reproducing device - Google Patents

Abstract

PURPOSE:To stably and surely detect a minimum level even in an unsteady state by setting a detection period longer in the unsteady state than in a steady state and detecting the level at every detection period. CONSTITUTION:A counter 200 counts clocks, generates the 1st period pulse at every period of about 1H and further generates the 2nd period pulse at every longer period than the period of about 1H. These period pulses are supplied to a selector 201, which selects the 1st period pulse in the steady state at the time of the rise of the rotation of a spindle motor, a CLV search, and a scan, and the 2nd period pulse in the unsteady state where the rotation of a disk is unstable. The selected period pulses are supplied to a register 202 and an averaging circuit 203. A minimum value stored in the register 202 is loaded to the circuit 203 whenever the 1st 2nd period pulse is generated. The circuit 203 averages the minimum values and outputs the mean as a final minimum value.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Technical Field The present invention relates to a minimum value detection circuit in a video signal reproducing device.

Background Art In recorded information reproducing devices such as video disc players, various control signals and synchronization signals contained in a video signal are separated, and various signal processing is performed based on the separated and extracted control signals and synchronization signals. It is done. This signal separation is performed by setting a reference level based on the bed scale level or minimum level of the video signal, and using this level as a reference. In a video signal, the minimum value usually appears during the horizontal synchronization period, so the detection period is set to IH (1
By setting the horizontal scanning period), the minimum level can be detected.

By the way, in a video disc player, etc., in an unsteady state such as when the spindle motor starts to rotate or when searching or scanning a CLV disc, the rotation of the disc is not stable, so the 1H period, which is the detection period, fluctuates. may not include the horizontal synchronization signal,
In this case, the minimum value cannot be detected accurately.

Further, when a dropout occurs, a value temporarily smaller than the signal level of the horizontal synchronizing signal may occur, resulting in an error.

SUMMARY OF THE INVENTION The present invention has been made in view of the following two points, and an object of the present invention is to provide a minimum value detection circuit for a video signal reproducing device that can stably and reliably detect the minimum value level even in an unsteady state. .

In the minimum value detection circuit according to the present invention, the detection period is set longer in an unsteady state than in a steady state, and a detection signal is generated for each detection period, and when dropout occurs, the time point at which the dropout ends The configuration is such that the detection period is set again based on the standard.

Example Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1(A), an FM video signal read from a recording medium such as a video disc is passed through an input terminal 1, an analog LPF (low pass filter) 2, and an A/D converter.
(analog/digital) converter 4. The LPF 2 removes aliasing distortion in A/D conversion, but the LPF 2 removes aliasing distortion in A/D conversion.
(ωS is the sampling frequency during A/D conversion) If the following two components are very small, the LPF 2 may be omitted.

The digital FM video signal output from the A/D converter 4 is supplied to a digital BPF (band pass filter) 6. This digital BPF 6 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM audio signal, and supplies the extracted components to the FM detection circuit 7 at the next stage.

For example, as shown in FIG. 2, the digital BPF 6 includes delay circuits 601 to 60n connected in series that delay one clock, and input signals of the delay circuit 601 and output signals of the delay circuits 601 to 60n. multiplication factor k
Multiplier 61 for multiplying O~kn. o to 61n, an adder 62 that adds the multiplication outputs, and a latch circuit 63 that latches the addition output.
By appropriately selecting each multiplication coefficient ko−kn of ˜61n, desired amplitude characteristics and group delay characteristics can be obtained. Therefore, when group delay distortion is caused by the analog LPF 2, by making the group delay characteristics of the digital BPF 6 inverse to those of the analog LPF 2, the digital BPF 6 can be converted into a digital F
M video signals can be supplied. Also, analog L
If the group delay distortion of PF2 is small and can be ignored, or if analog LPF2 is deleted, use digital BPF.
By using a phase linear filter for 6, a signal without group delay distortion can be obtained. In Figure 2,
The coefficient Ko-Kn of the digital BPF 6 is symmetrical about n (Ko = Kn).

Kl-KH)...), it becomes an ideal phase linear filter.

The FM detection circuit 7, for example, as shown in FIG. 1(A),
A Hilbert transformer 70 that performs Hilbert transform on the Digimolized FM video signal, a delay circuit 71 that delays the Digimolized FM video signal by n sample periods, and squares of the output signals of the Hilbert converter 70 and the delay circuit 71, respectively. A sum-of-squares circuit 72 for adding, a delay circuit 73 for delaying the output signal of the delay circuit 71 by one sample period, a multiplier 74 for multiplying each output signal of the delay circuits 71 and 73, and the output of this multiplier 74. A divider 75 divides the signal by the output signal of the square sum circuit 72. The Hilbert transformer 70 is composed of a transversal filter and the like.

Furthermore, the delay time of the delay circuit 71 is determined by the Hilbert transformer 70.
This corresponds to the delay time of The FM detection circuit 7 having such a configuration is disclosed in Japanese Patent Application No. 59-2624 by the applicant of the present application.
Proposed in No. 81.

In FIG. 1B, in the video LPFIO to which the detection output of the FM detection circuit 7 is supplied, only the baseband component of the video signal is extracted from the detection output. video LP
The cutoff frequency of the FIO is set to, for example, 4.2 MHz in the case of the NTSC system. Figure 3 shows the video LPF
An example configuration of IO is shown and shown in this video LPFI
O is a phase linear acyclic circuit in the previous stage that operates at a clock frequency of 4Nfsc (N is an integer greater than or equal to 2) and removes the carrier wave component contained in the FM-detected digital video signal and extracts only the baseband component. type digital filter (FIR filter) 100 and this FIR filter 10
A downsampling circuit 101 that downsamples the output of 0 to a clock frequency of 4 fsc, and a subsequent cyclic digital filter that operates at a clock frequency of 4 fsc and compensates for the phase characteristics of the digital video signal.
IIR filter) 102.

In Fig. 4 (A) to (C), each part (A) in Fig. 3 is shown.
-(C) spectra are shown.

The FM detection output (A) includes not only the baseband video signal but also its second harmonic component, which is passed through the FIR filter 10.
By passing through 0, only the baseband video signal (B) is derived at the output end. This baseband video signal (B) is transmitted to the downsampling circuit 101
The clock frequency of 4Nfsc is downsampled to the clock frequency of 4fsc. The spectrum after downsampling is the same as that in Figure (B).

By lowering the sampling frequency in this way, it is possible to save time and reduce the amount of hardware.

Note that since the band of the digitized video signal is narrowed to approximately 4.2 MHz by passing through the FIR filter 100, there is no problem even if the sampling frequency is lowered. After downsampling, the baseband video signal (B) is compensated for its phase characteristics by an IIR filter 102. The spectrum (C) after phase compensation is also the same as that in Figure (B).

In the case of video disks, etc., the signal processing system for the playback signal has traditionally been analog, so the phase distortion of the video LPF is calculated when recording information, assuming that the phase will rotate in a video LPF designed in an analog manner. Information is recorded by distorting it in the opposite direction with reverse compensation. Therefore, when digitally processing the playback signal when playing back a video disc with such a recording format, it is necessary to further compensate for the inverse compensation of phase distortion during recording, and compensation for this phase characteristic is required. is the IIR filter 102
It is done in In FIG. 5, IIR filter 1
02 phase characteristics are shown.

6 to 8 show examples of specific configurations of the FIR filter 100, the downsampling circuit 101, and the IIR filter 102. First, in Figure 6,
The FIR filter 100 includes delay circuits 1031 to 103n connected in series to each other for delaying one clock;
Input signal of delay circuit 1031 and delay circuits 1031 to 1
Multipliers 104o to 104n that multiply each output signal of 03n by a multiplication coefficient ko-kn, an adder 105 that adds each multiplication output, and a latch circuit 106 consisting of a D-type flip-flop or the like that latches this addition output. The clock frequency of the delay circuits 1031 to 103n and the latch circuit 106 is set to 4Nfsc. As shown in FIG. 7, the downsampling circuit 101 is constituted by a latch circuit 107 consisting of a D-type flip-flop or the like, and its clock frequency is set to 4 fsc.

As a result, the data input to the latch circuit 107 is N
- Output every other item.

Moreover, as shown in FIG. 8, the IIR filter 102
A multiplier 108o that multiplies an input signal by a multiplication coefficient ko, an adder 109 that uses this multiplication output as one addition input, a latch circuit 110 consisting of a D-type flip-flop or the like that latches this addition output, and an adder 109. Delay circuits connected in series]]11 to 111n and these delay circuits 1111 to 1 that sequentially delay the addition output by one clock.
Multiplier 1 that multiplies each output of 11n by a multiplication coefficient of 1 to kn.
081 to 108n, a latch circuit 110 and a delay circuit 111. + ~1.1-1. The clock frequency of n is set to 4fsc. In this circuit configuration, each multiplication coefficient ko- of the multipliers 1080 to 108n is
By appropriately setting kn, phase characteristics as shown in FIG. 5 can be obtained.

In the video LPF 10 described above, the phase straight line FI
By using the R filter 100 at the front stage, all phase compensation can be determined only by the IIR filter 102 at the rear stage, and the amplitude characteristics can be adjusted without changing the phase characteristics.

Note that downsampling is performed before the IIR filter 102, but this is because the iIR filter 102 is
This is due to the fact that all operations must be completed within a clock period. In order to perform downsampling after the IIR filter 102, pipeline processing is impossible for the above-mentioned reasons, and the number of operations must be reduced or high-speed elements must be used, but there are limits to this as well. On the other hand,
If downsampling is performed before the IIR filter 102, the clock period will naturally become longer, and if the number of operations is increased accordingly, more accurate characteristics will be obtained and stability will also increase.

In the video LPFIO configured as described above, the front stage F
The IR filter 100 is operated with a 4Nfsc clock, and its output is processed by a downsampling circuit 101 at 4fsc.
However, as shown in FIG. 9, downsampling is performed before the arithmetic circuit in the FIR filter 100', and the clock after the arithmetic circuit is downsampled at 4fs.
It is also possible to configure it to operate with the clock of c. At this time, the downsampling circuit 101 is not necessary.

That is, in FIG. 9, the FIR filter 100' includes delay circuits 112I to 12n connected in series that delay one clock, and an input signal and a delay circuit 112n connected in series.
latch circuits 1130 to 113n consisting of D-type flip-flops that latch each output signal of 121 to 112n;
Multipliers 114o to 114 multiply each latch output of these latch circuits 1130 to 113n by a multiplication coefficient ko-kn.
n, an adder 115 that adds these multiplication outputs, and a latch circuit 116 consisting of a D-type flip-flop that latches this addition output, and delay circuits 1, 12+ to 1.
The operation of the latch circuits 1130 to 113n in the next stage is performed at 4 fs.
c clock, and the final stage arithmetic circuit (multiplier 114
0 to 114ns adder 1]5 and latch circuit 116)
The configuration is such that the operation is performed using a 4fsc clock.

In the FIR filter 100' having such a configuration, the calculation is 4f.
Since it is performed using the sc clock, unnecessary calculations are omitted,
In addition, since the clock cycle becomes longer, the number of calculations can be increased, and relatively, the FIR filter 10 having the above-mentioned configuration
This means that the circuit scale can be reduced more than 0.

In addition, in order for the FIR filter to have a phase linear characteristic in FIGS. 6 and 9, the coefficient Ko−Kn must be symmetrical about the center (Ko = Kn,
K+ = KIh, ......).

Again in FIG. 1(B), the digitized video signal that has passed through the video LPFIO is sent to the de-emphasis circuit 11.
an adder 12 through which the pedestal clamping means is constituted;
, pedestal level detection circuit 13 and signal separation circuit 14
supplied to

By the way, when performing digital signal processing, it is clear that a smaller number of quantization bits per word n (bit/word) is advantageous in designing a circuit.

However, when considering the FM detection output, the output level is constant in the steady state of the disc player, but it is unsteady due to the rise of rotation of the spindle motor 24, search and scan during CLV (constant linear velocity) disc playback, etc. In this state, the DC component of the video signal changes significantly. If the synchronization signal becomes undetectable in an unsteady state, the spindle servo circuit 23 cannot be locked, and the clock generation circuit 21 cannot be synchronized, so the steady state cannot be achieved forever, so the synchronization signal can be detected even in the unsteady state. You need to be able to do it. For this purpose, the number of bits n must be set based on the unsteady state.

Therefore, at least the number n of bits from the input of the signal separation circuit 14 to the output of the de-emphasis circuit 11 is set to a number of bits with a wide dynamic range that is sufficient even if the pedestal level changes significantly based on the unsteady state. n
+ (bit/word). As a result, not only in a steady state but also in an unsteady state, the signal separation circuit 14
This means that the synchronization signal can be reliably detected.

The pedestal level detection circuit 13 detects the pedestal level v
po is detected and the pedestal level vp is determined from the reference voltage VRF.
The video signal is digitally pedestally clamped by generating an output (VRF - Vp D ) obtained by subtracting o and adding it to the digitized video signal in an adder 12 to cancel the variation in the pedestal level. The pedestal-clamped n + (bit/word) data is output from the adder 12 as n 2 (bit/word).
bits are reduced to data of word) (nl<n+
). nl is determined by the dynamic range and resolution required for a video signal in a steady state. This bit reduction facilitates the circuit design of the adder 2 and subsequent parts. Furthermore, by performing pedestal clamping, the signal level of the digitized video signal will be within the dynamic range of n 2 (bit/word) not only in the steady state but also in the unsteady state, so when scanning the CLV. This means that images can be viewed even in unsteady conditions such as.

In the above configuration, regarding the dynamic range of each circuit constituting the digital signal processing system, the dynamic range up to the input of the signal separation circuit 14 is n+ (bH/word), and regarding video processing, a pedestal clamp is used digitally. After that, n 2 (bit/wo
However, as shown in Figure 10, digital FM
It is also possible to separate the output of the detection circuit 7 into two systems, a video processing system and a signal separation system, and make the number of bits n for each prefecture different.

That is, in FIG. 10, the number of bits n of the signal separation system
is the number of bits n + with a wide dynamic range that is sufficient even if the pedestal level changes significantly in an unsteady state.
(bit/word). This n 1(b
(it/word) data is supplied to the signal separation circuit 14 via the LPF 16. The LPF 16 may be any filter that has characteristics that allow the synchronization signal to be detected from its output, and therefore the configuration can be simplified by using simplified filter coefficients. On the other hand, regarding the video processing system, the number of bits n 2 (bit/wo
rd) dynamic range. nl is determined by the dynamic range and resolution required for a video signal in a steady state.

In this way, the digital FM detection output is nl+n 2
By separating into two systems (bit/word),
Since the circuit after the video LPFIO can be designed by considering only the steady state case, the circuit configuration can be simplified, and the synchronization signal can be reliably detected even in an unsteady state such as when the spindle motor 24 starts up. Become.

In addition, in such a circuit configuration, in an unsteady state, there may be cases where the image cannot be seen due to changes in the pedestal level, but this is only possible if the image can be seen in the steady state, and the synchronization signal can be reliably detected in the unsteady state. It is based on ideas. However, in the CLV scan, since the clock generation circuit 21 is synchronized to some extent, changes in the pedestal level are often small, and in this case, the image can also be viewed.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit]3. In this figure, LPF11
The digitized video signal (a) from which the color burst has been removed in step 7 is supplied to a pedestal sampling circuit 118 and a sync separation circuit 119, respectively. Synchronous separation circuit 11
At step 9, the synchronizing signal (b) included in the digital video signal (a) is separated and extracted, and the synchronizing signal (b) is supplied to the rising/falling detection circuit 121 and the falling detection circuit 120, respectively. The falling detection circuit 120 receives the first gate signal (
The rising edge detection circuit 121 detects the fall of the synchronizing signal (b) during the generation period of c), and the rise of the synchronizing signal (b) during the generation period of the second gate signal (d).

The timing signal generation circuit 122 generates a first gate signal (c) based on a clock signal during a period in which a dropout detection signal (g) from a dropout detection circuit 17 (see FIG. 1(A)), which will be described later, is not generated. The dropout detection signal (g
) is not generated, the second gate signal (d) is generated.

The sample period signal generation circuit 123 generates a sample period signal (e) of a certain period in response to the detection output of the rising edge detection circuit 121, and supplies it to the pulse generation control circuit 124.

The pulse generation control circuit 124 is, for example, a three-way AND circuit that receives the sample period signal (e) and dropout detection signal (g) from the sample period signal generation circuit 123.
The gate 125 and the detection output of the rising edge detection circuit 121 are set (S) input, the output of AND gate 125 is reset (R) input, the clock signal is input as clock (CK), and its Q output is input to AND gate 125. It consists of an SR flip-flop 126 and an AND game)
The output pulse of 125 is supplied to the pedestal sampling circuit 118 as a sampling pulse (f). The pedestal sampling circuit 118 is composed of a D-type flip-flop or the like, and latches the pedestal level VPD of the digitized video signal in response to the sampling pulse (f). The sampled pedestal level VρD is subtracted from the reference level VRF by the arithmetic circuit 127 and averaged among a plurality of H, resulting in a detection output of the (VRr−−Vpo) level.

Figure 12 shows the operating waveforms of the circuit in Figure 11, and Figures (a) to (g) show the waveforms of each part (a) to (g) in Figure 11, respectively. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the first gate signal (C) detects the falling edge of the horizontal synchronizing signal included in the synchronizing signal (b), and uses this falling edge as a reference. The second gate signal (d) is generated after a time equivalent to the width of the horizontal synchronization signal, the rise of the horizontal synchronization signal (b) is detected, and the sample period signal (e) is generated based on this rise, so it is reliable. It is possible to capture the horizontal synchronization signal and sample the pedestal level on the back porch during the horizontal blanking period. Moreover, the digitized video signal (a) is transmitted through the LPF 117.
Since the color burst has been removed in , the sample period signal (
e) can be generated.

The sampling pulse (f) is the sampling period signal (
It is generated during the generation period of e) and the non-occurrence period of the dropout detection signal (g), and has a pulse width corresponding to one clock of the clock signal. Therefore, if there is a dropout shorter than the sample period, then Fig. 12 (f
), one clock worth of sampling can be reliably performed on the IH without the influence of dropout. Also, 1st. Second gate signal (C).

(d) is generated excluding the part where dropout occurs, so even if a false horizontal synchronization signal is generated due to dropout, a sample period signal will not be generated erroneously based on this horizontal synchronization signal. It is.

Pedestal level detection circuit】3 output (Vp F-Vp
Pedestal clamping is performed by adding 0) to the video signal in the adder 12 in FIG. 1(B). In addition, the pedestal level VPD is shown in Figure 1 (B).
It is also supplied to the signal separation circuit 14 in the circuit 14 .
In this case, synchronization signals and control signals are separated using the pedestal level VPD as a reference level.

Note that in the above configuration, the LPF 117 in the input section can be omitted, but if it is omitted, it is necessary to generate the sampling period signal in a period other than the color burst section. Furthermore, the configuration of the pulse generation control circuit 124 is not limited to the circuit configuration described above, and various configurations are possible, such as using a microprocessor, for example. Also,
The LPF 117 and the synchronization separation circuit 119 can be respectively replaced with an LPF 145a and a signal detection circuit 145c in FIG. 21, which will be described later, and these circuits may be used in common.

FIG. 13 shows the falling detection circuit 12 in FIG.
An example of a specific circuit configuration of the 0, 0, 0, 2, 2, 22, and 22 timing signal generation circuits, and the sample period signal generation circuit 123 is shown. In this figure, the fall detection circuit 120 converts the synchronization signal (b) into data (D).
A D-type flip-flop 128 that receives a clock signal as an input, an inverter 129A that receives a synchronization signal (b), a Q output of the flip-flop 128, and a first gate signal ( C) and a 3-man power NAND gate 129B that outputs from the inverter 129A with 3 man power,
The Q output of the flip-flop 128 is 1 when the synchronizing signal (b) is 1.
The clock is delayed and the NAND gate 129
In B, if the synchronization signal (b) falls while the first gate signal (c) is at a high level, that is, the horizontal synchronization signal falls, all three input signals become high level at the moment of the fall. , a low level detection output is generated.

Timing signal generation circuit] 22, falling detection circuit 1
20 as a load (L) input and a clock signal as a clock input, and the output of this counter 130 is decoded and the first .
The gate circuit 131 generates second gate signals (c) and (d). IH counter 130
is to count the IH period clock in synchronization with the falling edge of the horizontal synchronization signal, and if the video signal is NTSC, the clock is 14.3MHz = 4fsc = 91Of+
(fH is the horizontal scanning frequency) and becomes a 910 progress counter. Further, the gate signals (c) and (d) are not generated during the period when dropout occurs.

Although not shown in the figure, if the IH counter 130 is not loaded several times in succession, the first gate signal (C) is forcibly set to a high level and the horizontal synchronizing signal is Detect the falling edge. This means that the IH counter 130 is shifted by 1/2H due to the equalization pulse.
This is to prevent loading by the horizontal synchronizing signal from being carried out thereafter and making it impossible to detect the pedestal level.

The rising edge detection circuit 121 is the timing signal generation circuit 1
It consists of a D-type flip-flop 132 which takes the second gate signal (d) from 22 as the data (D) input and the synchronization signal (b) as the clock input, and the second gate signal (d)
If the signal (b) rises while the signal (b) is at a high level, that is, the horizontal synchronizing signal rises or falls, a high level detection output is generated from the Q output terminal. The sample period signal generation circuit 123 consists of a 7-bit counter 133 which uses the detection output of the rising/two-point detection circuit 121 as a load (L) input and an enable (EN) input. " is loaded, the count starts at the rising edge of the horizontal synchronization signal, and the sample period signal (e) is output with the period from 96" to "127" as the sample period. When the count exceeds "127" and becomes "0" Then, the D-type flip-flop 132 is cleared, the load input and the enable input are set to low level, and the load state is returned to and stopped.

Note that the fall detection circuit 120 and the timing signal generation circuit 122 are similar to the HV separation circuit 1 in FIG. 21, which will be described later.
45d and a part of the timing signal generation section of the system controller 18 in FIG.
The D-type flip-flop 180, inverter 181A, and NAND gate 181B in FIG.
] to the IH counter 183 and gate circuit 182 in FIG.
They may be shared with A.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 3, in which the same parts as in FIG. 11 are designated by the same symbols. 26-, the synchronization signal (b) separated and extracted by the synchronization separation circuit 119 from the digitized video signal (a) that has passed through the LPF'l 17 is supplied to the fall detection circuit 134. The fall detection circuit 134 generates a synchronization signal (C) during the generation period of the gate signal (C) output from the timing signal generation circuit 135.
b) is detected, and the detection output is supplied to the timing signal generation circuit 135.

The timing signal generation circuit 135 generates a gate signal (c) based on the clock signal during the non-generation period of the dropout detection signal (f), and also generates the gate signal (c) based on the clock signal during the period when the dropout detection signal (f) is not generated.
34 generates a sample period signal (d) at the front porch of the horizontal synchronizing signal after IH using the falling detection timing as a reference, and supplies it to the pulse generation control circuit 136.

The pulse generation control circuit 136 includes, for example, a three-man power AND gate 137 inputting the sample period signal (d) and the dropout detection signal (f) from the timing signal generation circuit 135, and a set signal from the timing generation circuit 35. Set (S) input, reset (R) input the output of AND gate 137, set the clock signal to the clock (CK
) and an SR flip-flop 138 whose Q output is used as an input to an AND gate 137,
The output pulse of the D gate 137 is converted into a sampling pulse (e
) to the pedestal sampling circuit 118. The subsequent operations are the same as those shown in FIG.

Figure 15 shows the operating waveforms of the circuit in Figure 14, and Figures (a) to (f) show the waveforms of each section (a) to (f) in Figure 14, respectively. .

Pedestal level detection circuit configured as shown in FIG. 14] 3 detects the falling edge of the horizontal synchronizing signal using the gate signal (c), generates a set signal using this falling edge as a reference, and opens the AND gate 137. , the sample period signal (d) is generated corresponding to the front porch after IH, so
The pedestal level can be detected even during the vertical blanking period. Further, after sampling the pedestal level, if the falling edge of the horizontal synchronizing signal cannot be detected while the gate signal (c) is being generated, the falling edge detection circuit 134
By generating a pedestal enable signal from
It is possible to inform the next circuit that the sampled pedestal level is invalid, or to hold the previously detected pedestal level. For example, by inputting the pedestal enable signal to the arithmetic circuit 127, the circuit 127 previously outputs (VRt: -Vp
D) will continue to be output.

The gate signal (c) and the sampling period signal (d) are generated except for the part where the dropout occurs, and the pulse generation control circuit 136 generates the sampling pulse (e) for one clock. without accidentally generating the sample period signal (d);
If the length of the dropout during the sample period does not exceed the sample period, it is possible to reliably sample one clock worth of IH without the influence of dropout, as shown by the two-dot chain line in Fig. 15(e). can.

As for the example of diversion, the same aspect as in the case of the configuration shown in FIG. 11 can be considered.

FIG. 16 shows the falling detection circuit 13 in FIG.
4 and a specific circuit configuration of the timing signal generation circuit 135 are shown. In this figure, the fall detection circuit 134 is a JK flip-flop 1 which receives a synchronization signal (b) as an inverted clock input and a gate signal (c) as a J input.
39, when the synchronization signal (b) falls while the gate signal (C) is at high level, that is, the horizontal synchronization signal falls, the Q output becomes high level, and thereafter the reset signal becomes low level. The Q output is held high until the transition occurs. When the reset signal goes low, the Q output also goes low.

The timing signal generation circuit 135 receives the Q output of the JK flip-flop 139 as data (D) input.

A D-type flip-flop 140 that receives a clock signal as a clock input, and a Q output of this flip-flop 140 that is set to 0.
A D-type flip-flop 141 that uses a clock signal as a clock input, and an IH counter 142 that uses the Q output of this free flop 141 as a load (L) input and a clock signal as a clock input.
A gate circuit 1 decodes the output of this IH counter 142 and generates a gate signal and a reset signal in a predetermined period.
43, and immediately after the Q output of the JK flip-flop 139 becomes high level, the D-type flip-flop 14
A load pulse is generated for one clock from 0,141 to load the IH counter 142, which causes the IH counter 142 to synchronize with the falling edge of the horizontal synchronization signal]H
Count the period. The IH counter 142 has a clock of 14.3MHz=4fs when the video signal is NTSC.
c=910f+-+ (f+-+ is horizontal scanning frequency)
Therefore, it becomes a 910-decimal counter.

In the gate circuit 143, the gate signal (c) is not generated during the period when dropout occurs. Further, the reset signal is generated as one pulse at IH with a sufficient interval from the gate signal (C) so that the pedestal enable signal is recognized by the next stage circuit.

Note that in the circuit shown in FIG. 16, the gate signal (C) is reduced to 1/2 due to the loading of the IH counter 142 by the equalization pulse.
Measures similar to those shown in FIG. 13 are taken to prevent H deviation.

Further, the circuit in FIG. 16 can be replaced or shared with the HV separation circuit 145d in FIG. 21 and the circuit in FIG. 31, as in the case of FIG. 13.

In addition, in each of the embodiments of the bedscale level detection circuit 13 described above, the video signal has been described as being digitized, but the application is not limited to digital video signals, and can be applied to analog video signals. It can be applied in the same way.

Next, the dropout correction circuit 1 in FIG. 1(B)
9 will be explained. This dropout correction circuit 19
corrects the dropout of the digitized video signal output from the adder 12, but regarding the dropout of the vertical synchronization signal part, it is replaced with a correction signal set in advance to a level equal to the signal level of the vertical synchronization signal. By doing so, the dropout is corrected.

The configuration of this dropout correction circuit 19 is shown in FIG. In this figure, the digitized video signal is supplied to the first selector switch 190, and the output of the switch 190 is sent to the second delay circuit 1 via the first delay circuit 19.
92 and 3.58 MHz BPF193.

Here, when the delay amount of the BPF 193 is set to d, the delay amount of the first delay circuit 191 is set to IH-d, and the delay amount of the second delay circuit 192 is set to d. The output of BPF 193 is sent to adder 195 via multiplier 194 with a coefficient of -2.
and is added to the output of the second delay circuit 192. The addition output of the adder 195 is sent to the second changeover switch 196.
The output of the switch 196 becomes the output of the first changeover switch 190. Switching of the first changeover switch 190 is controlled by a dropout detection signal supplied from the dropout detection circuit 17 (see FIG. 1(A)).

The address generation circuit 197 generates a field identification signal, horizontal address, and vertical address based on the horizontal synchronization signal and vertical synchronization signal supplied from the signal separation circuit 14, and generates a field identification signal, a horizontal address, and a vertical address based on the address information from the vertical synchronization level generation circuit 198. A correction signal is generated which is set to a level equal to the signal level of the known vertical synchronization signal, and the second
The changeover switch 196 is controlled by someone else. In the switching signal generation circuit 199, a vertical synchronization period signal is generated during the generation period of the vertical synchronization signal based on the vertical address, and this vertical synchronization period signal becomes a switching signal for controlling the switching of the second changeover switch 196.

By the way, as shown in FIG. 18, the signal (A) before correction
If a dropout occurs in the vertical synchronization pulse part of , if the dropout is corrected by replacing this part with the pre-IH signal (B), the corrected signal (C ) may cause a positional deviation of the vertical synchronizing pulse (in FIG. 18, a positional deviation of 1/2H occurs between the portions marked with ◯).

If the vertical synchronization pulse is misaligned in this way, there is a possibility that field errors will occur in subsequent video equipment. However, prohibiting the drop-out correction of the vertical synchronization pulse may cause synchronization disturbance.

Therefore, as shown in FIG. 17, if dropout occurs in the vertical synchronization pulse portion, the signal level is equal to that of the vertical synchronization signal output from the vertical synchronization level generation circuit 198 instead of the signal before IH. The level correction signal is
By supplying the signal to the changeover switch 190 and replacing it with a digitized video signal, dropout can be corrected without causing a positional shift of the vertical synchronizing pulse.

Note that in FIG. 17, dropout correction is performed using the signal before IH, but at this time, the phase of the chroma signal will become reversed if left unchanged. Therefore, the first
The circuit surrounded by the broken line in FIG. 7 inverts the phase of the chroma signal, thereby making it possible to colorize the dropout correction signal. Therefore, when dropout correction is performed only on a luminance signal (monochrome), when a signal 2H earlier (clock signal is in phase), etc., the circuit shown in the broken line is excluded. The address generation circuit 197, vertical synchronization level generation circuit 198, and switching signal generation circuit 199 may be included in the system controller 18, and replaced with the IH counter 183° gate circuit 182A, 1 frame counter 189° gate circuit 182B, etc. in FIG. You may.

The dropout detection circuit 17 in FIG. 1(A) has a level comparator configuration, and as shown in FIG. When it is detected that the signal level of the squared signal (B) of the envelope component of A) has become below a predetermined value, a dropout detection signal (C) is output. According to this configuration, the dropout detection circuit can be configured by simply adding a level comparator to the FM detection circuit 7, so that dropout detection can be reliably performed with a simple circuit configuration, and all detection operations can be performed. Since this is done digitally, stable characteristics can be obtained.

Note that there is a possibility that the detection output is disturbed by ringing that occurs in the output of the sum-of-squares circuit 72 (the area surrounded by a dashed line in FIG. 19(B)) due to a sudden change in the envelope. A dropout detection signal (D) is also output as a dropout section at nl points before the signal level of the output signal (B) of 72 becomes below a predetermined value and at n2 points after the level becomes above a predetermined value. This allows subsequent corrections to be performed reliably. At this time, there is a possibility that ringing will occur due to the delay of the Hilbert transformer 70, so nl+02 is the delay circuit 70.
The delay time n is set to be equal to or larger than the delay time n of 1.

The signal separation circuit 14 in FIG. 1(B) separates and extracts control signals such as frame numbers and stop codes along with color burst signals, horizontal synchronization signals, vertical synchronization signals, etc. contained in the digitized video signal. For this signal separation, as shown in FIG. 20, a first reference level VTI-11 for separating and extracting the control signal A;
Second reference level VT for separating and extracting synchronization signal B
H2 is set.

The configuration of this signal separation circuit 14 is shown in FIG.

In this figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum level of the digitized video signal within a predetermined period. . The configuration of the minimum value detection circuit 20 will be explained in detail later. This pedestal level detection circuit 13 and minimum value detection circuit 20
Based on each detection level of the first. second reference level V
T HI +VTH2 is set, but the reference level generation circuit 140 generates the first reference level VTI-11 by adding a constant value to the detected level based only on the detection level of the pedestal level detection circuit 13. Based on the detection levels of the pedestal level detection circuit 13 and the minimum value detection circuit 20, the reference level generation circuit 141 generates an intermediate value between both levels as a second reference level VTI-12. The reference level generation circuits 142 and 143 generate the first. A second reference level VT)-11 and VTI-12 are generated.

Each output of the reference level generation circuits 140 to 143 is supplied to a selector 144, and this selector 144 selects the reference level generation circuit 140 when the synchronization establishment determination signal is supplied from the system controller 18, that is, when the synchronization is stable. , 141. second reference level V
THI and VTH2 are selected, and in other cases, that is, when the synchronization is unstable, the first. Select a second reference level VTHI, VTI-12. Note that the system controller 18 determines whether or not synchronization is established by comparing a reference synchronization pulse based on an internal clock with the extracted synchronization pulse. The first one selected by the selector 144. Second
reference level vTH+.

VTI-12 is supplied to a signal detection circuit 145C, which detects these reference levels vTH+, V
The control signal A and the synchronization signal B are separated and extracted from the digitized video signal that has passed through the LPF 145a based on T)-12.

That is, in the signal separation circuit 14 configured as described above, the IH
When the synchronization is stable, the pedestal level and the first level set based on the pedestal level and the minimum level. Based on the second reference level VT)-11, VTI-12, or when the synchronization is unstable such as when the spindle motor 24 starts rotating or during a search or scan of the CLV disk, the pedestal detection position is not determined and its value is is not determined, so the first value is set based only on the minimum level. Second reference level VTI-11, VTI-1
The control signal A and the synchronization signal B are separated and extracted based on the reference signal A and the synchronization signal B. According to this, signal separation can be performed stably and reliably not only when synchronization is stable but also when synchronization is unstable. The separated synchronization signal B is sent to the HV separation circuit 1.
45d and H from the system controller 18.
The horizontal = 40- synchronization signal is separated by detecting a falling edge when the S gate signal is at a high level. Further, the synchronization signal B is subjected to integration processing in the HV separation circuit 145d, and a vertical synchronization signal is separated based on a predetermined reference level. The digitized video signal is input to the fscBPF 145b together with the LPF 145a, and a color burst signal containing color signal components is output from the fscBPF 145b.

By the way, regarding the detection of the synchronization signal in the signal detection circuit 145C, as shown in FIG. 22, the digitized video signal is sampled at every predetermined clock (the X mark in the figure is the sample point), and the signal level of the synchronization signal is at the reference level. VT
The synchronization signal is detected at the time when H2 is exceeded.

The configuration of this synchronization signal detection circuit is shown in FIG.

In this figure, a reference level generation circuit 141 (or 143
) and the digitized video signal passed through the LPF 145a.
6 calculates the level difference between the signal level of the video signal and the reference level VTI-12 at each sample point, and detects a sample point where the video signal level is smaller than the reference level VTI-12 as a synchronization signal. The level difference signal calculated by the subtracter 146 is supplied to a delay circuit 147, a sign determination circuit 148, and a storage device 149 such as a ROM (read only memory). The delay circuit 147 has a delay amount equivalent to the clock, and delays the level difference signal from the subtracter 146 to send it to the sign determination circuit 148 and the storage device 1.
Supply to 49. The sign determination circuit 148 is a delay circuit 147
the output A of is positive and the output B of the subtracter 146 is negative,
That is, the level difference at the sample point a immediately before the output A of the delay circuit 147 exceeds the reference level VTH2, and the subtracter 14
It is determined that the output B of No. 6 is already a level difference at the sample point immediately after exceeding the reference level VTH2, and a determination signal is supplied to the storage device 149.

For example, a time table as shown in FIG. 24 is stored in advance in the storage device 149, and the storage device 149 stores the outputs of the delay circuit 147 and the subtracter 146 when the determination signal is generated from the sign determination circuit 148, That is, based on the level differences A and B at the two sample points a and b, corresponding time information is output. The inputs A, B and the output of the storage device 149 are both 4-bit data, for example, and the first bit of the 4 bits of the inputs A, B is a sign bit, which is expressed as a two's complement number.

The time information that is the output of the storage device 149 is the time difference between the time point C when the signal level of the synchronization signal exceeds the reference level VTI-12 and the sample point a or b. Even if they do not match, it is possible to accurately detect the position of the falling edge of the synchronization signal.

Next, the minimum value detection circuit 20 in FIG. 21 will be explained. In FIG. 25, the counter 200 counts the clock so that the first
A second period pulse is generated every period longer than the IH equivalent period. These period pulses are supplied to the selector 201, and the first period pulse is used in a steady state, and the second period pulse is used in an unsteady state where the rotation of the disk is unstable, such as when the spindle motor 24 starts rotating, or when a CLV search or scan is performed. Pulses are selected and provided to register 202 and averaging circuit 203. L
The comparator 204, which uses the digitized video signal output from the PF 145a, inputs its input data 8 and the register 20.
The data B stored in the register 202 is compared with the data B stored in the register 202 every time a clock occurs, and the smaller data is supplied to the register 202.

However, the comparator 204 is designed to stop its operation when dropout occurs. Since the register 202 is reset by the first or second period pulse supplied from the selector 201, the smallest value from the previous reset time will be stored in the register 202. The minimum value stored in register 202 is the first or second
The average value is loaded into the averaging circuit 203 every time a period pulse occurs, and the averaging circuit 203 averages each minimum value of two or more detection periods and finally outputs it as the minimum value.

In such a configuration, since the minimum value of the video signal usually appears during the synchronization signal period, a 1H period is set as the detection period (first period pulse generation interval). In an unsteady state such as during a CLV search or scan, the length of the IH period fluctuates because the rotation of the disk is not stable.

At this time, if minimum value detection is performed at normal intervals based on the first period pulse, there may be cases where the synchronization signal is not included within the interval. Therefore, in an unsteady state, by using a second period pulse that is generated every period longer than the 1H period, the synchronization signal will be included within the detection period, so the minimum level can be detected reliably. This means that fluctuations in the minimum level can be reduced. In addition, when a dropout occurs, a value that is temporarily lower than the signal level of the synchronization signal may occur, but by stopping the operation of the comparator 204 and inhibiting the detection operation during the dropout period, the minimum value This means that false detections can be prevented.

Also, the counter 200 is activated by the dropout detection signal.
By resetting the counter 200, the counter 200 starts counting for a certain period again from the point at which the dropout ends, so even if the synchronization signal part is missing due to a dropout, the counter 200 will wait until the next period pulse is generated. The level of the synchronizing signal portion can be detected reliably.

The clock generation circuit 21 in FIG. 1(B) generates 4 fsc (fsc is the subcarrier frequency) based on the reference horizontal synchronization signal from the reference signal generator 22 or the horizontal synchronization signal or color burst signal from the signal separation circuit 14. It generates a clock of 4Nfsc (for example, 12fsc) and is a PLL (phase locked loop).
It has a circuit configuration. The 4fsc and 4NfsC clocks generated here are used as clocks for digital signal processing, and the sampling clock of the A/D converter 4 and the clock for signal processing up to the video LPFIO are set to 4Nfsc, and the output from the video LPFIO is 4f
Downsample to se.

The configuration of the clock generation circuit 21 is shown in FIG.

In this figure, a phase comparator 210 that uses a color burst signal as a comparison reference input is connected to a sampling pulse generation circuit 21.
Sampling pulses CK+, CK supplied via 1
Phase comparison is performed in response to 2. Note that when locking the PLL to the reference horizontal synchronization signal or the horizontal synchronization signal, the phase comparator 210 is not used, and another phase comparator (not shown) is used to lock one of these signals and 2fsc.
The phase is compared with the fH signal obtained by multiplying by 1/455, and the output is inputted to the LPF 212.

Hereinafter, only the case of locking to the color burst signal will be explained. The comparison output of the phase comparator 210 is LPF2
The signal is supplied to the D/A converter 213 via the signal line 12, where it is converted into an analog signal and becomes a control signal for the CO (voltage controlled oscillator) 214. The oscillation frequency of VCO214 is 12fsc
The clock is set to 12fsc, and is output as is as a clock of 12fsc, and the frequency is divided to 4fsc by the 1l3 frequency divider 215. This clock 4fsc is output as it is, serves as the sole power of the sampling pulse generation circuit 211, and is further divided into fSC by the 1l2 frequency dividers 216 and 217, and becomes the comparison input of the phase comparator 210. The sampling pulse generation circuit 211 is supplied with the gate pulse generated by the gate pulse generation circuit 218 as an external power, and therefore the phase comparator 210 is supplied with the sampling pulses CK, CK2 only during the gate pulse generation period. It turns out. The gate pulse generation circuit 218 generates a gate pulse (B) in synchronization with 4 fsc based on the horizontal synchronization signal, as shown in FIG. 27, only for a period corresponding to the central portion where the amplitude of the color burst signal (A) is constant. do.

In the phase comparator 210, as shown in FIG.
The color burst signal becomes the output of the adders/subtractors 219 and 220, and each addition/subtraction output passes through delay circuits 221 and 222 and becomes the output of the adders/subtractors 219 and 220, and is divided by the divider 223. The addition/subtraction (±) control of the adders/subtracters 219 and 220 is performed using the clock pulse fsc shown in FIG.
Based on (B), sample point S1. In S2, addition,
Sample point S3. In S4, subtraction is performed. However, when a track jump is performed during still image playback, etc., the phase of the color burst signal changes by 180 degrees, so the clock pulse fsc changes every time a track jump occurs.
Invert the phase of (B) to maintain PLL lock.

This is controlled by the 1l2 frequency divider 21 by the chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).
This is done by controlling 7.

Further, the sampling pulse generation circuit 211 is composed of a D-type flip-flop, and has a sampling clock CK+
, CR2 is synchronized with 4fsc, and 1 of that frequency
/2 and have opposite phases to each other, and serve as clocks for the delay circuits 221 and 222, respectively, only when the gate pulse is at a high level.

As a result, assuming that the amplitude of the color burst signal (A) is A, ΣA sinθ is derived as the output of the delay circuit 221, ΣA cosθ is derived as the output of the delay circuit 222, and tanθ is derived as the output of the divider 223. Ru. Then, this divided output tan θ is calculated as tan″1 circuit 2
24, the phase difference θ can be obtained.

−49= That is, the phase difference θ in the phase comparator 210 can be calculated from the following equation.

θ−jan/V (Σ[(St S3) S2
-8a)]lwhere, 5l-A-sinθ 52
-A-cos θS3 --A 11 sin θ
S 4--A Φ cos θ.

By the way, as is clear from the above equation, if the amplitude A of the color burst signal (A) is not constant within the IH, a slight error will occur in the detected phase difference θ, and a change in the loop characteristics will occur due to a change in the loop gain of the PLL. It turns out.

However, in the clock generation circuit 21 described above, 81 to
Sampling pulse CK for obtaining S4.

By applying a gate to CR2, the phase comparison is performed only during the period in which the amplitude A of the color burst signal (A) is constant, so that the above-mentioned problem does not occur.

In the above configuration, phase comparison is performed only in the central portion of the color burst signal by applying a gate to the sampling pulse, but it is of course possible to apply a gate to the color burst signal itself. . In this case, since it is a digital gate, only the central part of the color burst signal can be extracted more accurately than an analog switch or the like. Furthermore, in FIG. 26, the arrangement relationship between the LPF 212 and the D/A converter 213 may be reversed.

In FIG. 1(B), a reference signal generator 22 includes a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronization signal. The spindle servo circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronization signal from the reference signal generator 22 and the horizontal synchronization signal from the signal separation circuit 14. The chroma inversion circuit 25 adjusts the chroma (color) as necessary to maintain color framing even during special playback such as still playback and slow playback.
A phase inversion of the signal is performed.

The configuration of this chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is sent to the IH delay circuit 270.
, are supplied to the adder 271. After the signal level of the output of the adder 271 is halved by the level adjustment circuit 272,
It is supplied to a subtracter 273. The subtraction output of the subtracter 273 is supplied to the adder 275 via a phase linear acyclic digital BPF 274, and the addition output of the adder 275 is as follows.
The signal is supplied to the changeover switch 276.

The delayed output of the delay circuit 270 is sent to the subtracter 273 and BPF2.
The signal is supplied to a delay circuit 277 having the same delay amount as 74, and is also supplied to an adder 271 via an IH delay circuit 278. The delayed output of delay circuit 277 is supplied to adder 275 and changeover switch 276. The changeover switch 276 is appropriately switched by a chroma inversion control signal supplied from the system controller 18 in FIG. 1(B).

With this configuration, a 2- and 3-line correlation comb filter is configured, and the subtracted output of the subtracter 273 is transmitted to the IH delay circuit 2.
A chroma signal (-2C) with an opposite phase and twice the level of the delayed output of 70 (assumed to be Y+C) is obtained. After unnecessary components are removed from this chroma signal by the BPF 274, the delay amount is adjusted by the delay circuit 277 and the delay output (
A digitized video signal (b) having a chroma signal inverted with respect to the delayed output (a) of the delay circuit 277 is obtained as an addition output. For special playback such as stay and slow, selector switch 27
Color framing can be maintained by switching the chroma inversion control signal from the system controller 18 of FIG. 1(B).

In FIG. 1B, the output of chroma inversion circuit 25 is supplied to video processing circuit 38. In FIG. The video processing circuit 38 performs character insertion, MCA code suppression, squelch, etc. The digitized video signal that has passed through the video processing circuit 38 is generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal.
is written into the buffer memory 39 by the clock. Reading from the buffer memory 39 is performed using a 4fsc reference clock generated by the reference signal generator 22. In this way, by reading data from the buffer memory 39 using a stable reference clock that is unrelated to the reproduced signal, jitter in the reproduced signal can be absorbed, eliminating the need for so-called tangential servo or color correction circuits. Become. The digitized video signal read out from the buffer memory 39 is converted into an analog signal by the D/A converter 1ii 40, and then sent to the output terminal 4 via the LPF 41.
2.

The system controller 18 has the following main functions. That is, 1. Various servo systems are controlled in response to commands from operating units such as panel switches and remote controls, and state signals from the servo system, to cause the player to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generate signals for compositing frame numbers, chapter numbers, etc. onto the screen.

4. Synchronize the internal counter with the horizontal synchronization signal and vertical synchronization signal, and decode the output of the counter to generate various timing signals.

5. Controls the PLL loop for clock generation. A specific configuration for realizing the fourth function among the above main functions will be described below.

In Fig. 31, the horizontal synchronizing signal (π or not) is
) input and a 4fsc clock signal as a clock (C
K) A D-type flip-flop 180 is provided as an input, and the Q output of this flip-flop 180 is NAN.
It will be the sole strength of D Gate 181B. NAND gate 18
1B uses the horizontal synchronizing signal supplied via the inverter] 81A, and its output is sent to the IH counter 18.
3 load (L) input. The gate circuit 182A is
The output of the IH counter 183 is decoded to generate the HS gate signal during a predetermined period and inputted to the HV separation circuit 145d in FIG. Ru. The HS gate signal is used in the HV separation circuit 145d to detect the fall of the horizontal synchronization signal excluding the equalization pulse and to separate the horizontal signals. In the initial state, the Is agate signal is always at a high level, loads the IH counter 183 at the falling edge of the synchronizing signal, and thereafter remains at a high level only for a predetermined period so as to detect the falling edge of the horizontal synchronizing signal in the IH cycle. In the initial state or for some reason, if the IH counter 183 is loaded due to the fall of the equalization pulse and a 1/2H shift occurs, the IH counter 183 will not be loaded after the vertical blanking period.
This state is detected within the system controller 18 and the HS gate signal is kept at a high level again. Note that the HV separation circuit 145d generates a pulse of a predetermined width based on the fall of the horizontal synchronizing signal, and outputs this as the horizontal synchronizing signal. The clock HCK is a signal having a duty ratio of 50%, starting from the falling edge of the synchronization signal, and being at a high level in the first half and a low level in the second half.

The gate circuit 182A further generates various timing signals within the IH and supplies them to each circuit.

The positive polarity vertical synchronization signal (VS) becomes each clock input of D-type flip-flops 184 and 185.

The D-type flip-flop 184 receives the VS gate signal output from the gate circuit 182B as a data (D) input, and when the vertical synchronization signal rises while the signal is at a high level, its Q output becomes high level and 0. The output goes to low level and remains in that state until the reset signal goes to low level. When the reset and reset signals go to low level, the Q and Q outputs are inverted.

The D-type flip-flop 185 receives the clock HCK output from the gate circuit 182A as a data input, and is used to determine whether the vertical synchronization signal is from field 1 or field 2.
In field 2, the rising edge of the vertical synchronizing signal arrives when the clock HCK is at a low level, so the Q output becomes a low level, and the 0 output becomes a high level.In field 2, the rising edge of the vertical synchronizing signal arrives when the clock HCK is at a high level, so the Q The output is at a high level and the Q output is at a low level. A D-type flip-flop 186 uses the Q output of the flip-flop 184 as a data input, the clock HCK as a clock input, and the Q output of the flip-flop 185 as a clear input. When the clock HCK rises, the Q output becomes high level, and in field 1, the Q output remains low level.

The Q and Q outputs of the D-type flip-flop 184 are J.

J- with K input, clock HCK as inverted clock input, and Q output of flip-flop 185 as clear input.
The flip-flop 187 is D when field 1
When the Q output of the type flip-flop 184 becomes high level, the Q output becomes high level at the fall of the clock HCK.
During field 2, the Q output remains at a low level.

A NOR gate 188 that makes each Q output of the D type flip-flop 186 and the J- flip-flop 187 two-man power.
The next stage 1 frame counter 189
is loaded and the D-type flip-flop 184 is reset. Here, the reason why a load pulse is created using a separate flip-flop for each field is that a sufficiently wide load pulse is generated in each field. This is to send it to the frame counter 189. 1 frame counter] 89 counts the clock HCK 5
It is a 25-decimal counter and is loaded with the clock HCK when the output of the NOR gate 188 is at a low level.
D type flip-flop 185 so that the number is increased by 3
It is controlled by the 0 output of

The gate circuit 182B decodes the output of the one frame counter 189 and generates the above-mentioned VS gate signal in a predetermined period, and also generates a timing signal of H units within one frame and supplies it to each circuit.

Next, the fifth of the above-mentioned five functions of the system controller 18, ie, the function of controlling the clock generation PLL loop, will be explained based on the flowchart of FIG. 32. As mentioned above, this PLL has two phase comparators: one for locking to the reference horizontal synchronizing signal or the reproduced horizontal synchronizing signal, and the other for locking to the color burst signal. The configuration is such that three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal at the input section of the phase comparator and by switching the phase comparator itself. In FIG. 32, in an initial state such as immediately after the power is turned on or when the spindle motor is forcibly accelerated, the reference signal generator 22 (FIG. 1(B)), which is the reference for the spindle servo,
P to lock to the reference horizontal synchronization signal obtained in
The loop of LL operates (step]). When it is determined that it has locked to the reference horizontal synchronization signal (step 2) and the horizontal synchronization signal can be obtained from the reproduced video signal, the loop is switched to the reproduction horizontal synchronization signal (step 3). At this time, if it is determined that locking is not possible (step 4),
Return to step 1 and loop back to the reference horizontal synchronization signal. If it is determined in step 4 that it is locked to the playback horizontal synchronization signal, the presence or absence of a color burst signal is detected in step 5), and if there is no color burst signal, step -60
= 4 to keep it locked to the playback horizontal synchronization signal. This state occurs during the vertical blanking period for both black and white discs and color discs. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). Here, if it is determined that locking to the color burst signal is not possible (step 7)
, returns to the reproduction horizontal synchronization signal loop in step 3, but if locking is achieved, the color burst loop state is maintained. However, at the same time, the synchronization with the playback horizontal synchronization signal must be monitored (Step 8). If either the lock with the color burst signal or the lock with the playback horizontal synchronization signal is lost, it is assumed that the lock is lost and the playback horizontal synchronization signal is looped. Return to (step 3). At this time, if the playback horizontal synchronization signal loop cannot be locked to the playback horizontal synchronization signal (step 4)
, and then returns to the reference horizontal synchronization signal loop (step 1).

Note that a No determination in step 4.7 indicates that the lock cannot be locked within the predetermined period when passing for the first time.
When passing for the second time or later, it indicates that it is not locked.

This system has been explained above while showing the specific configuration of each circuit, but the point of this system is that all signal processing is performed digitally between the A/D converter 4 and the D/A converter 40. It has great characteristics. In this way, by digitizing the signal, it is possible to make it multi-functional, such as converting the monochrome dropout correction signal to color, chroma inversion, increasing the accuracy of Y-C separation by introducing frame memory, or increasing the accuracy of Y-C separation by introducing frame memory. Still image playback becomes easier.

In FIG. 1B, the circuits are arranged in the order of the adder 12, the dropout correction circuit 19, the chroma inversion circuit 25, the video processing circuit 38, and the buffer memory 39, but the arrangement is not limited to this arrangement. For example, as shown in FIGS. 33(A) and 33(B), the order of "dropout correction circuit 19 + chroma inversion circuit 25J, r video processing circuit 38" and "buffer memory 39" can be changed. be. However, since writing and reading of the buffer memory 39 are asynchronous, the "buffer memory 39"
If there are two other signals after the first one (as in the case of FIG. 33(B)), it is necessary to resynchronize or delay the control signals and timing signals for the other two signals. In addition, “Video processing circuit 3
8" is followed by "dropout correction circuit 19 + chroma inversion circuit 25" (in the case of FIG. 33(A)),
When a character is inserted by the video processing circuit 38, a control signal is required to inhibit the dropout correction circuit 19 from performing dropout correction in the character portion.

Furthermore, as shown in FIG. 34, R, G, and B separation can also be performed digitally, and each digital signal separated by the RGB separation circuit 43 is sent to the D/A converter 4.
4 to analog output terminals 46R, 46G, and 46B via LPF 45. If these terminals are connected to an RGB input monitor TV (television), the RGB separation circuit in the TV can be used. Since there is no need to use , image quality can be improved.

Furthermore, when using a digital TV that can input RGB as it is digitized, the digital signals separated by the RGB separation circuit 43 are directly input to each digital output terminal 47R, 47G, without going through a D/A converter. 47B.

In this RGB separation, in this system, the clock of the A/D converter 4 is set to 4Nfsc (N is an integer of 2 or more), and the color burst signal of the video signal is set to 4Nfsc.
Since the clock of c is locked, RGB separation (demodulation) can be easily performed. Below, R-Y, B-
The case of demodulating using the Y signal will be explained, but I,
Demodulation can be similarly performed using the Q signal.

In the NTSC system, the phase of the color signal is as shown in FIG. 35, which is quadrature two-phase modulated and frequency multiplexed with the luminance signal. The relationship between the R, G, and B signals and the luminance signal Y is shown in the following equation.

Y-0,1OR+0.59 G+ 0.11.8...
...(1) Also, the color signal C in the video signal is expressed by the following equation.

= I cos(ωc t +33°)+Qsin(
ωc t +33°)・・・−・−(3) Here, ω
C is the angular frequency of the color carrier, ωC=2πX 3.
It is 58 MHz.

4 When the phase of the sampling frequency of fsc is locked at 0° with respect to the color burst signal, Fig. 35 and (2
) formula, each sample point is ±(
R-Y) / 1.14, ±(B-R) / 2
．． It can be seen that the value is 03. Also, from equations (1) and (2), R, G, and B signals are obtained. Furthermore, I.

To obtain the Q signal, ±33° relative to the color burst signal.
Alternatively, the phase may be locked at ±57°.

From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst signal.

In the above embodiment, the case where the system is applied to an NTSC video disc player has been described, but this system is applicable to VTR playback side signal processing, PAL, SEC
It can also be applied to AM video disc players and the like.

As described in detail, the minimum value detection circuit according to the present invention has a configuration in which the detection period is set longer in an unsteady state than in a steady state, so that the minimum value detection circuit according to the present invention is set to have a longer detection period in an unsteady state than in a steady state. Even when the rotation of the disk is unstable, such as when the rotation of the disk is unstable, the horizontal synchronization signal is included within the detection period, so the minimum level can be detected stably and reliably.

In addition, when a dropout occurs, the detection period is set again based on the point at which the dropout ends, so even if the synchronization signal part is missing due to a dropout, a pulse will be generated in the next period. By this time, the level of the synchronizing signal portion can be reliably detected, and the influence of dropout can be eliminated.

[Brief explanation of the drawing]

FIGS. 1(A) and 1(B) are block diagrams showing an embodiment of the video signal reproducing apparatus according to the present invention, and FIG.
), FIG. 3 is a block diagram showing an example of the configuration of the video LPF in FIG. 1(B), and FIGS. Spectrum diagrams of each part (A) to (C), Figure 5 is a phase characteristic diagram of the IIR filter in Figure 3, and Figures S6 to Figure 8 are specifics of the FIR filter, downsampling circuit, and IIR filter in Figure 3. FIG. 9 is a block diagram showing another structure of the video LPF. The NIO diagram is a block diagram showing another configuration of the bit reduction process in Figure 411 (B), Figure 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit in Figure 1 CB), and Figure m12 is a block diagram showing the configuration of an example of the pedestal level detection circuit in Figure 1 (CB). 13 is a block diagram showing the specific configuration of the falling detection circuit, rising detection circuit, timing signal generation circuit, and sample period signal generation circuit in FIG. 11, and FIG. 14 is a pedestal level diagram. 15 is a block diagram showing another configuration of the detection circuit, FIG. 15 is an operation waveform diagram of each part of FIG. 14, and FIG. 16 is a block diagram showing the internal configuration of the fall detection circuit and timing signal generation circuit in FIG. 14. 17 is a block diagram showing the specific configuration of the dropout correction circuit in FIG. 1(B), FIG. 18 is a waveform diagram for explaining the circuit operation of FIG. 17, and FIG. Waveform diagram 2 for explaining the circuit operation of the dropout detection circuit in Figure 1 (A).
0 is a waveform diagram showing the relationship with the video signal 4 reference level in the signal separation circuit in FIG. 1(B), FIG. 21 is a block diagram showing the specific configuration of the signal separation circuit, and FIG. FIG. 21 is a waveform diagram for explaining the operation of the signal detection circuit, FIG. 23 is a block diagram showing the specific configuration of the signal detection circuit, and FIG. 24 is an example of the time table stored in the ROM in FIG. 23. Figure 25 shows the second
FIG. 26 is a block diagram showing the specific configuration of the minimum value detection circuit in FIG. 1, FIG. 26 is a block diagram showing the specific configuration of the clock generation circuit in FIG. 1(B), and FIG. 27 is a waveform of each part in FIG. 28 is a block diagram showing the specific configuration of the phase comparator in FIG. 26, FIG. 29 is a waveform diagram for explaining the circuit operation of FIG. 28, and FIG. 30 is the same as that shown in FIG. 1(B). FIG. 31 is a block diagram showing a specific configuration of the chroma inversion circuit in FIG. Flowchart of predetermined functions of the controller, FIG. 33(A). (B) is a block diagram showing a modified example of this system, No. 34
The figure is a block diagram showing another modification, and FIG. 35 is a block diagram showing another modification.
FIG. 4 is a phase characteristic diagram of a color signal used to explain the principle of RGB separation, and FIG. 36 is a waveform diagram of a signal at each sample point. Explanation of symbols of main parts 2...Analog LPF 4...A/
D converter 6... Digital BPF 7... FM detection circuit 10... Video LPF 13... Pedestal level detection circuit 14
... Signal separation circuit 17 ... Dropout detection circuit 18 ...
... System controller 19 ... Dropout correction circuit 21 ... Clock generation circuit 22 ... Reference signal generator 24 ... Spindle motor 25 ... ... Chroma inversion circuit 38 ... Video processing circuit 39 ... Buffer memory 40 ... D/A converter

Claims (1)

[Claims] A minimum value detection circuit in a video signal reproducing device that detects a minimum level within a predetermined section of a video signal, wherein in a steady state of the reproducing device, the first detection signal is detected every first predetermined period equal to the length of the predetermined section. detection signal generating means for generating a second detection signal every second period which is longer than the first predetermined period in an unsteady state; detecting means for detecting the minimum level of the video signal at , and the detection signal generating means detects the first and second predetermined periods with reference to the point in time when the dropout detection signal disappears when a dropout occurs. A minimum value detection circuit in a video signal reproducing device, characterized in that: