JPH0746858B2 - Signal separation circuit in video signal reproducing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a signal separation circuit in a video signal reproducing apparatus, and more particularly to a signal separation circuit that separates and extracts a control signal and a synchronization signal included in a video signal.

2. Description of the Related Art In a recorded information reproducing apparatus such as a video disc player, a control signal and a sync signal included in a video signal are separated, and various signal processing is performed based on the separated and extracted control signal and sync signal. . This signal separation is
Conventionally, it is performed by setting a reference level based on the pedestal level and using the level as a reference.

However, for example, in a disc player, when synchronization is unstable such as when the spindle motor starts up or during CLV disc search or scan, the pedestal level detection position is not fixed and the value is not fixed. As a result, the reference level cannot be set and the separation of synchronization cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a signal separation circuit capable of performing stable and reliable signal separation not only when synchronization is stable but also when synchronization is unstable.

A signal separating circuit according to the present invention sets a first reference level for separating a control signal based on a pedestal level when synchronization is stable and a second reference level for separating a synchronizing signal based on a pedestal level and a minimum value level. Is set, and when synchronization is unstable, the first and second reference levels are set based on only the minimum value level.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1 (A), an FM video signal read from a recording medium such as a video disk passes through an input terminal 1 and an analog LPF (low-pass filter) 2 and then A / D (analog / analog).
Digital) converter 4. The LPF2 removes aliasing distortion in A / D conversion.
If there are very few components above ωs / 2 (ωs is the sampling frequency for A / D conversion) included in the video signal,
You may omit LPF2. The digitized FM video signal output from the A / D converter 4 is supplied to a digital BPF (bandpass filter) 6. This digital BPF 6 extracts only the components necessary for the detection of the video signal from the A / D conversion output that also includes the FM audio signal and supplies it to the FM detection circuit 7 in the next stage.

As the digital BPF 6, for example, as shown in FIG.
Delay circuits 60 _{1 to} 60 n connected in series for delaying one clock, an input signal of the delay circuit 60 ₁ and the delay circuit 6
Multiplier 6 for multiplying each output signal of 0 _{1 to} 60 n by multiplication coefficient ko to kn
An FIR filter (non-recursive digital filter) consisting of 1o to 61n, an adder 62 that adds each multiplication output, and a latch circuit 63 that latches this addition output can be used, and each of the multipliers 61o to 61n can be used. By properly selecting the multiplication coefficients ko to kn, desired amplitude characteristics and group delay characteristics can be obtained. Therefore, when the group delay distortion is caused by the analog LPF2, the digitized FM video signal is supplied to the FM detection circuit 7 by eliminating the group delay distortion by making the group delay characteristic of the digital BPF6 the reverse characteristic of the analog LPF2. can do. When the group delay distortion of the analog LPF2 is small and can be ignored, or when the analog LPF2 is deleted, a signal without group delay distortion can be obtained by using a phase linear filter for the digital BPF6. In Fig. 2, the coefficient Ko of the digital BPF6
If ˜Kn is symmetric with respect to n (Ko = Kn, K ₁ = K _n-1 ...), an ideal phase linear filter is obtained.

As shown in FIG. 1A, for example, the FM detection circuit 7 includes a Hilbert converter 70 for Hilbert converting the digitized FM video signal, a delay circuit 71 for delaying the digitized FM video signal by n sample periods, Square each output signal of the Hilbert transformer 70 and the delay circuit 71 and add 2
The multiply-add circuit 72, the delay circuit 73 that delays the output signal of the delay circuit 71 by one sample period, the multiplier 74 that multiplies the output signals of the delay circuits 71 and 73, and the output signal of this multiplier 74 It is composed of a divider 75 that divides the output signal of the multiply-add circuit 72. The Hilbert transformer 70 is composed of a transversal filter or the like. Also, the delay circuit
The delay time of 71 corresponds to the delay time of the Hilbert transformer 70. The FM detection circuit 7 having such a structure has been proposed by the applicant of the present application in Japanese Patent Application No. 59-262481.

In FIG. 1 (B), in the video LPF 10 to which the detection output of the FM detection circuit 7 is supplied, only the baseband component of the video signal is extracted from the detection output. The cutoff frequency of the video LPF 10 is set to, for example, 4.2 MHz in the case of the NTSC system. FIG. 3 shows an example of the structure of the video LPF 10, which operates at a clock frequency of 4Nfsc (N is an integer of 2 or more) and is a carrier wave included in the digitized video signal FM-detected. The phase linear non-recursive digital filter (FIR filter) 100 in the previous stage that removes the component and extracts only the baseband component, and this FIR filter 100
Down-sampling circuit 101 for down-sampling the output of 4 fsc to a clock frequency of 4 fsc, and a recursive digital filter (IIR filter) 102 in the latter stage which operates at a clock frequency of 4 fsc and compensates the phase characteristics of the digitized video signal. Has been done.

4 (A) to (C), each part (A) in FIG.
The spectra of (C) are shown. The FM detection output (A) contains not only the baseband video signal but also its second harmonic component, and only the baseband video signal (B) is derived at its output end by passing through the FIR filter 100. Will be done. The baseband video signal (B) is downsampled by the downsampling circuit 101 from the clock frequency of 4Nfsc to the clock frequency of 4fsc. The spectrum after downsampling is the same as that in FIG. In this way, by reducing the sampling frequency, it is possible to reduce the time margin and the amount of hardware. Since the band of the digitized video signal is narrowed to about 4.2 MHz by passing through the FIR filter 100, there is no problem even if the sampling frequency is lowered. After the baseband video signal (B) is down-sampled, the IIR filter 102 compensates the phase characteristic. The spectrum (C) after phase compensation is also the same as that in FIG.

In the case of video discs, etc., the signal processing system of the reproduced signal has been analog in the past, so on the assumption that the phase will rotate in the video LPF designed in analog,
At the time of recording information, the information is recorded by distorting it in the opposite direction so as to inversely compensate the phase distortion of the video LPF. Therefore, when the reproduced signal is digitally processed during reproduction of a video disk of such a recording form, it is necessary to further compensate the inverse compensation of the phase distortion at the time of recording. Is performed by the IIR filter 102. FIG. 5 shows the phase characteristic of the IIR filter 102.

6 to 8 show examples of specific configurations of the FIR filter 100, the downsampling circuit 101, and the IIR filter 102. First, in FIG. 6, the FIR filter 100
Is 1 and the delay circuit 103 ₁ ～103N connected in series with each other perform clocks of delay, multiplier for multiplying the multiplication factor ko~kn to each output signal of the input signal of the delay circuit 103 ₁ and the delay circuit 103 ₁ ～103N Adder 10 for adding 104o to 104n and each multiplication output
5 and a latch circuit 106 including a D-type flip-flop for latching the added output, and the delay circuit 103.
The clock frequencies of _{1 to} 103n and the latch circuit 106 are set to 4Nfsc. The down sampling circuit 101 has a seventh
As shown in the figure, it is composed of a latch circuit 107 such as a D-type flip-flop, and its clock frequency is 4fs.
It is set to c. As a result, the data input to the latch circuit 107 is output every N-1 data.

Further, as shown in FIG. 8, the IIR filter 102 includes a multiplier 108o that multiplies an input signal by a multiplication coefficient ko, an adder 109 that uses this multiplication output as one addition input, and a D that latches this addition output. Type latch circuit 11 consisting of flip-flops, etc.
0, delay circuits 111 _{1 to} 111 n connected in series that sequentially delay the addition output of the adder 109 by one clock, and multiplication by multiplying each output of these delay circuits 111 _{1 to} 111 n by multiplication coefficients k _{1 to} kn is composed of a vessel 108 ₁ ~108n, the clock frequency of the latch circuit 110 and the delay circuit 111 ₁ ~111n is set to 4 fsc. In this circuit configuration, the phase characteristics as shown in FIG. 5 can be obtained by appropriately setting the multiplication coefficients ko to kn of the multipliers 108o to 108n.

In the video LPF10 described above, the phase linear FIR filter 100 is used in the front stage, so that the phase compensation is performed in the rear stage I
It can be determined only by the IR filter 102, and the amplitude characteristic can be adjusted without changing the phase characteristic.

Although the downsampling is performed before the IIR filter 102, this is because the IIR filter 102 must complete all operations within one clock cycle. In order to perform downsampling after the IIR filter 102, pipeline processing is impossible for the above reason, and it is necessary to reduce the number of operations or use a high-speed element.
There are also limits. On the other hand, if downsampling is performed before the IIR filter 102, the clock cycle naturally becomes longer, and if the number of calculations is increased accordingly, more accurate characteristics can be obtained and stability can be increased.

In the video LPF 10 having the above-described configuration, the FIR filter 100 in the previous stage is operated with a clock of 4Nfsc, and the output thereof is downsampled to the clock of 4fsc by the downsampling circuit 101. However, as shown in FIG. FIR
It is also possible to perform down-sampling before the arithmetic circuit in the filter 100 ′ and to operate the subsequent arithmetic circuit with a clock of 4 fsc. At this time, the downsampling circuit 101 is not necessary.

That is, in FIG. 9, the FIR filter 100 'is a delay circuit connected in series for delaying one clock.
112 _{1 to} 112n, latch circuits 113o to 113n formed of D-type flip-flops for latching the input signals and the output signals of the delay circuits 112 _{1 to} 112n, and the latch outputs of these latch circuits 113o to 113n multiplied by the multiplication coefficient ko to. Multiplier multiplied by kn 114o to 114n
And an adder 115 for adding these multiplication outputs, and a latch circuit 116 composed of a D-type flip-flop for latching the addition output, and the operation of the delay circuits 112 _{1 to} 112n is 4Nfsc.
The operation of the latch circuits 113o to 113n at the next stage is performed at the clock of 4fsc, and the operation circuit at the final stage (multiplier
114o ~ 114n, adder 115 and latch circuit 116) operation 4f
It is configured to be performed by the clock of sc.

In the FIR filter 100 ′ having such a configuration, since the computation is performed with the clock of 4 fsc, unnecessary computation is omitted, and since the clock cycle becomes long, the number of computations can be increased. The circuit scale can be reduced as compared with the filter 100.

Note that in FIG. 6 and FIG. 9, in order for the FIR filter to have a phase linear characteristic, the coefficient Ko to
Kn must be symmetric about the center (Ko ＝ Kn, K ₁ ＝ K _n-1 ,…).

Referring again to FIG. 1B, the digitized video signal that has passed through the video LPF 10 passes through the de-emphasis circuit 11 and is supplied to an adder 12, a pedestal level detection circuit 13 and a signal separation circuit 14 which constitute pedestal clamp means. It

By the way, when performing signal processing digitally, it is obvious that a smaller number of quantization bits n (bit / word) per word is advantageous in designing a circuit. However, considering the FM detection output, the output level is constant in the steady state of the disc player, but the rotation of the spindle motor 24 rises, and the CLV (constant linear velocity) search and scan during non-steady state during disc playback etc. In the state, the DC component of the video signal changes greatly. If the sync signal becomes undetectable in the non-steady state, the spindle servo circuit 23 cannot lock and the clock generation circuit 21 also becomes unsynchronizable and cannot be permanently in the steady state, so the sync signal is detected even in the non-steady state. Need to be able to. For that purpose, the number of bits n is based on the non-steady state.
Must be set.

Therefore, at least the number of bits n up to the input of the signal separation circuit 14, that is, the output of the de-emphasis circuit 11 has a wide dynamic range so that the pedestal level is sufficiently changed even if the pedestal level changes significantly with reference to the non-steady state. n ₁ (bit /
word)). As a result, the FM that has passed through the de-emphasis circuit 11 not only in the steady state but also in the non-steady state.
The signal separation circuit 14 can reliably detect the synchronization signal from the detection output.

The pedestal level detection circuit 13 has a pedestal level V _PD
Is detected and the pedestal level V _PD is subtracted from the reference voltage V _RF to generate an output (V _RF −V _PD ), which is added to the digitized video signal by the adder 12 to cancel the fluctuation in the pedestal level. , Digitally pedestal clamp the video signal. Pedestal clamped n
The data of ₁ (bit / word) is n ₂ (b
Bits are reduced to (it / word) data (n ₂ <n ₁ ). n ₂
Is determined by the dynamic range and resolution required for the steady state video signal. This bit reduction facilitates the circuit design after the adder 2. Also, by performing pedestal clamp, the signal level of the digitized video signal will be within the dynamic range of n ₂ (bit / word) not only in the steady state but also in the non-steady state. The image can be viewed even in a non-steady state such as.

In the above configuration, regarding the dynamic range of each circuit that constitutes the digital signal processing system, the dynamic range of n ₁ (bit / word) up to the input of the signal separation circuit 14 is set, and the pedestal is digitally applied for video processing. After clamping, the bit was reduced to n ₂ (bit / word) to narrow the dynamic range. However, as shown in FIG. 10, the output of the digital FM detection circuit 7 is divided into a video processing system and a signal separation system. It is also possible to separate into two systems and make the number of bits n of each system different.

That is, in FIG. 10, the number of bits of the signal separation system n
Is a bit number with a wide dynamic range n ₁ (bi
t / word). This n ₁ (bit / word) data is
The signal is supplied to the signal separation circuit 14 via the LPF 16. The LPF 16 may be any filter as long as it has a characteristic such that a sync signal can be detected from its output, and thus the LPF 16 has a simple configuration by using a simplified filter coefficient. On the other hand, regarding the video processing system, the number of bits n ₂ (bit / wor smaller than n ₁
It is set to the dynamic range of d). n ₂ is determined by the dynamic range and resolution required for the video signal in the steady state.

In this way, the digital FM detection output is changed to n ₁ , n ₂ (bit / wor
By separating it into two systems of d), the circuit after the video LPF10 can be designed by considering only the steady state, so that the circuit configuration can be simplified and the spindle motor 24 does not start up. The synchronization signal can be reliably detected even in the steady state.

It should be noted that in such a circuit configuration, the image may not be seen in a non-steady state due to a change in the pedestal level, but this is only required to be able to see the image in the steady state and to reliably detect the synchronization signal in the non-steady state. It is based on an idea. However, in the CLV scan, since the clock generation circuit 21 is synchronized to some extent, the change in the pedestal level is often small, and at this time, the image can be viewed.

FIG. 11 is a block diagram showing an example of the configuration of the pedestal level detection circuit 13. In the figure, the digitized video signal (a) from which the color burst has been removed by the LPF 117 is supplied to the pedestal sampling circuit 118 and the sync separation circuit 119, respectively. The sync separation circuit 119 separates and extracts the sync signal (b) included in the digitized video signal (a), and the sync signal (b) is supplied to the rising edge detection circuit 121 and the falling edge detection circuit 120, respectively. The fall detection circuit 120 generates the synchronization signal (b) during the generation period of the first gate signal (c) output from the timing signal generation circuit 122.
The rising edge detection circuit 121 detects the rising edge of the synchronizing signal (b) during the generation period of the second gate signal (d).

The timing signal generation circuit 122 generates a first gate signal (c) based on a clock signal in a non-generation period of a dropout detection signal (g) from a dropout detection circuit 17 (see FIG. 1A) described later. Further, the second gate signal (d) is generated in a non-occurrence period of the dropout detection signal (g) after a predetermined time, with reference to the fall detection timing of the fall detection circuit 120. In the sample period signal generation circuit 123, a sample period signal (e) for a fixed period is generated in response to the detection output of the rising edge detection circuit 121 and is supplied to the pulse generation control circuit 124.

The pulse generation control circuit 124 has, for example, a 3-input AND gate 1 to which the sample period signal (e) and the dropout detection signal (g) from the sample period signal generation circuit 123 are input.
25 and the detection output of the rise detection circuit 121 are set (S)
Input, AND gate 125 output is reset (R) input, clock signal is clock (CK) input, and its Q output is AN
The output pulse of the AND gate 125 is supplied to the pedestal sampling circuit 118 as a sampling pulse (f). The pedestal sampling circuit 118 is composed of a D flip-flop or the like, and latches the pedestal level V _PD of the digitized video signal in response to the sampling pulse (f). Sampled pedestal level V
_{The PD} is subtracted from the reference level V _RF by the arithmetic circuit 127 and averaged among a plurality of Hs, and becomes a detection output of the (V _RF −V _PD ) level.

FIG. 12 shows the operation waveforms of the circuit of FIG. 11, and FIGS. (A) to (g) respectively show the waveforms of the parts (a) to (g) of FIG. .

In the pedestal level detection circuit 13 having the configuration shown in FIG. 11, the falling edge of the horizontal synchronizing signal included in the synchronizing signal (b) is detected by the first gate signal (c), and the horizontal synchronizing signal is referenced with this falling edge as a reference. After the time corresponding to the width, the second gate signal (d) is generated to detect the rising edge of the horizontal synchronizing signal (b), and the sampling period signal (e) is generated based on this rising edge. Catch the signal,
The pedestal level can be sampled on the back porch during the horizontal blanking period. Further, since the color burst is removed by the LPF 117 in the digitized video signal (a), it is possible to generate the sample period signal (e) of a wide period including the portion where the color burst was present.

The sampling pulse (f) is the period during which the sampling period signal (e) is generated and the dropout detection signal (g).
Has a pulse width corresponding to one clock of the clock signal. Therefore, if there is a dropout shorter than the sampling period, as shown by the chain double-dashed line in FIG. 12 (f), sampling for one clock can be reliably performed for 1H without the influence of the dropout. Also, the first and second gate signals (c),
Since (d) is generated excluding the portion where the dropout occurs, even if a false horizontal sync signal is generated due to the dropout, the sample period signal is not erroneously generated with reference to this horizontal sync signal. Of.

A pedestal clamp is performed by adding the output (V _RF -V _PD ) of the pedestal level detection circuit 13 to the video signal by the adder 12 in FIG. 1 (B). The pedestal level V _PD is also supplied to the signal separation circuit 14 in FIG. 1B, and the circuit 14 separates the synchronization signal and the control signal with the pedestal level V _PD as the reference level.

In the above configuration, the LPF 117 in the input part can be omitted, but if omitted, it is necessary to generate the sampling period signal in a period other than the color burst part. Further, the configuration of the pulse generation control circuit 124 is not limited to the above-described circuit configuration, and various conceivable examples are possible such as using a microprocessor. Also, LPF117
The sync separation circuit 119 can be replaced with the LPF 145a and the signal detection circuit 145c in FIG. 21, which will be described later, and these circuits may be commonly used.

FIG. 13 shows an example of a specific circuit configuration of the fall detection circuit 120, the rise detection circuit 121, the timing signal generation circuit 122, and the sample period signal generation circuit 123 in FIG. In this figure, the fall detection circuit 120
Is a D-type flip-flop 128 that receives the synchronizing signal (b) as data (D) and the clock signal as clock input.
And an inverter 129A that receives the synchronization signal (b), a Q output of the flip-flop 128, and a timing signal generation circuit 1
It is composed of a first gate signal (c) from 22 and a 3-input NAND gate 129B having 3 inputs of the output from the inverter 129A, and the Q output of the flip-flop 128 is delayed by one clock of the synchronization signal (b). NAND gate
In 129B, when the synchronizing signal (b) falls during the period when the first gate signal (c) is at a high level, that is, when the horizontal synchronizing signal falls, all three inputs become high level at the moment of falling. , A low level detection output is generated.

The timing signal generation circuit 122 receives a detection output of the fall detection circuit 120 as a load (L) input and a clock signal as a clock input, and a 1H counter 130, which decodes the output of this counter 130 to make a first interval within a predetermined period. And a gate circuit 131 for generating the second gate signals (c) and (d). 1H counter 130 is intended to count the 1H period clock in synchronization with the falling of the horizontal synchronizing signal, a clock if the video signal is of the NTSC is 14.3MHz = 4fsc = 910f _H
(F _H is the horizontal scanning frequency) and becomes the 910 progress counter. Further, the gate signals (c) and (d) are not generated during the dropout period.

Although not shown in the figure, when the 1H counter 130 is not continuously loaded several times, the first gate signal (C) is forcibly set to a high level and the horizontal synchronizing signal rises. Try to detect the fall. This is to prevent the pedestal level from being undetectable because the 1H counter 130 is loaded with a 1 / 2H shift due to the equalization pulse and the horizontal sync signal is no longer loaded. .

The rising edge detection circuit 121 is composed of a D-type flip-flop 132 which receives the second gate signal (d) from the timing signal generation circuit 122 as data (D) input and the synchronization signal (b) as clock input. When the signal (b) rises, that is, the horizontal synchronizing signal rises while the gate signal (d) is at a high level, a high level detection output is generated from the Q output terminal. The sample period signal generation circuit 123 is composed of a 7-bit counter 133 which uses the detection output of the rising edge detection circuit 121 as a load (L) input and an enable (EN) input, and loads “90” until just before the rising edge of the horizontal synchronizing signal. Then, counting is started at the rising edge of the horizontal synchronizing signal, and the sample period signal (e) is output with the period "96" to "127" as the sample period. When the count exceeds "127" and becomes "0", the D-type flip-flop 132 is cleared, the load input and the enable input are set to the low level, the state returns to the load state again, and stops.

The fall detection circuit 120 and the timing signal generation circuit 1
22 may be a part of the timing signal generation unit of the HV separation circuit 145d shown in FIG. 21 and the system controller 18 shown in FIG. 31, which will be described later. In the figure, the D-type flip-flop 180, the inverter 181A, and the NAND gate 181B are replaced by the fall detection circuit 120, and the 1H counter 130 and the gate circuit 131 are replaced.
May be shared by the 1H counter 183 and the gate circuit 182A in FIG. 31, respectively.

FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit 13, in which the same parts as those in FIG. 11 are designated by the same reference numerals. In the figure, the sync signal (b) separated and extracted by the sync separation circuit 119 from the digitized video signal (a) passed through the LPF 117 is supplied to the fall detection circuit 134. The fall detection circuit 134 detects the fall of the synchronization signal (b) during the generation period of the gate signal (c) output from the timing signal generation circuit 135, and supplies the detection output to the timing signal generation circuit 135.

The timing signal generation circuit 135 generates the gate signal (c) based on the clock signal in the non-generation period of the dropout detection signal (f), and further the fall detection circuit 134.
A sample period signal (d) is generated in the front porch of the horizontal synchronizing signal after 1H based on the fall detection timing, and is supplied to the pulse generation control circuit 136.
The pulse generation control circuit 136 receives, for example, the sample period signal (d) and the dropout detection signal (f) from the timing signal generation circuit 135 as a 3-input AND gate 137.
And a set signal from the timing generation circuit 135 as a set (S) input, an output of the AND gate 137 as a reset (R) input, a clock signal as a clock (CK) input, and its Q
SR flip-flop whose output is one input of AND gate 137
138 and the pedestal sampling circuit 11 using the output pulse of the AND gate 137 as a sampling pulse (e).
Supply to 8. The subsequent operation is the same as that of FIG.

FIG. 15 shows the operation waveforms of the circuit of FIG. 14, and FIGS. 15A to 15F respectively show the waveforms of the parts (a) to (f) of FIG. 14 correspondingly. .

In the pedestal level detection circuit 13 configured as shown in FIG. 14, the falling edge of the horizontal synchronizing signal is detected by the gate signal (c), and a set signal is generated with this falling edge as a reference to generate the AN signal.
After the D gate 137 is opened, the sample period signal (d) is generated corresponding to the front porch after 1H, so that the pedestal level can be detected even during the vertical blanking period.
In addition, after the pedestal level is sampled, if the falling edge of the horizontal synchronizing signal cannot be detected during the generation of the gate signal (c), the falling edge detection circuit 134 generates a pedestal enable signal for sampling. The next stage circuit can be notified that the pedestal level is invalid, or the previously detected pedestal level can be retained. For example, inputting the pedestal enable signal to the arithmetic circuit 127 causes the circuit 127 to continuously output (V _RF −V _PD ).

The gate signal (c) and the sampling period signal (d) are generated except for the portion where the dropout occurs, and since the pulse generation control circuit 136 generates the sampling pulse (e) for one clock, the dropout causes If the sample period signal (d) is not generated by mistake and the length of the dropout during the sample period does not exceed the sample period, as shown by the chain double-dashed line in FIG. Without this, sampling for 1 clock can be reliably performed for 1H.

As for the diversion example, the same mode as in the case of the configuration of FIG. 11 can be considered.

FIG. 16 shows an example of a specific circuit configuration of the fall detection circuit 134 and the timing signal generation circuit 135 in FIG. In this figure, the fall detection circuit 134
Is composed of a JK flip-flop 139 having a sync signal (b) as an inverted clock input and a gate signal (c) as a J input, and the falling edge of the sync signal (b) during the high level period of the gate signal (c), that is, When the horizontal synchronizing signal falls, the Q output becomes high level, and thereafter, the Q output is held at high level until the reset signal transits to low level.
When the reset signal goes low, the Q output goes low.

The timing signal generation circuit 135 includes a JK flip-flop 139.
A D-type flip-flop 140 having the Q output as a data (D) input and a clock signal as the clock input, and a D-type flip-flop 141 having the Q output of the flip-flop 140 as a D input and the clock signal as the clock input, A 1H counter 142 that receives the output of the flip-flop 141 as a load (L) input and a clock signal as a clock input, and a gate circuit 143 that decodes the output of the 1H counter 142 and generates a gate signal and a reset signal in a predetermined period. Immediately after the Q output of the JK flip-flop 139 becomes high level, a load pulse is generated for one clock from the D-type flip-flops 140 and 141 to load the 1H counter 142, which causes the 1H counter 142 to be horizontally synchronized. 1H counter 14 that counts the 1H period in synchronization with the falling edge of the signal
2 is 14.3MHz = 4fsc when the video signal is NTSC
= 910f _H (f _H is the horizontal scanning frequency) and becomes a 910 base counter. In the gate circuit 143, the gate signal (c) is not generated during the dropout period. Further, the reset signal is generated as a pulse once every 1H with a sufficient interval from the gate signal (c) so that the pedestal enable signal can be recognized by the circuit at the next stage.

Even in the circuit shown in Fig. 16, the 1H counter using the equalization pulse
To prevent the gate signal (c) from being shifted by 1 / 2H due to loading 142, the same measures as in FIG. 13 are taken.

In addition, the circuit of FIG. 16 and the HV separation circuit 145d of FIG.
Also, the circuit can be replaced or shared with the circuit of FIG. 31 as in the case of FIG.

In each of the embodiments of the pedestal level detection circuit 13 described above, the video signal is described as being digitized, but the invention is not limited to the application to a digital video signal, and is also applicable to an analog video signal. The same applies.

Next, the dropout correction circuit 19 in FIG.
Will be described. This dropout correction circuit 19
The dropout of the digitized video signal output from the adder 12 is corrected, but the dropout of the vertical synchronizing signal portion should be replaced with a correction signal set to a level equal to the signal level of the vertical synchronizing signal in advance. Due to this, the dropout is corrected.

The configuration of the dropout correction circuit 19 is shown in FIG.
In the figure, the digitized video signal is one input of the first changeover switch 190, and the output of the switch 190 is the first
2nd delay circuit 192 and 3.58MHz via the delay circuit 191 of
Supplied to BPF193. Here, when the delay amount of the BPF 193 is d, the delay amount of the first delay circuit 191 is set to 1H-d and the delay amount of the second delay circuit 192 is set to d. The output of the BPF 193 is supplied to the adder 195 via the multiplier 194 having a coefficient of −2, and is added to the output of the second delay circuit 192. The addition output of the adder 195 becomes one input of the second changeover switch 196, and the output of the switch 196 concerned is the first changeover switch 190.
Other input. The changeover control of the first changeover switch 190 is performed by the dropout detection signal supplied from the dropout detection circuit 17 (see FIG. 1A).

In the address generation circuit 197, a field identification signal, a horizontal address and a vertical address are generated based on the horizontal synchronization signal and the vertical synchronization signal supplied from the signal separation circuit 14, and from the vertical synchronization level generation circuit 198 based on these address information. A correction signal set to a level equal to the signal level of the known vertical synchronizing signal is generated, and becomes the other input of the second changeover switch 196. In the switching signal generation circuit 199, a vertical synchronization period signal is generated based on the vertical address during the generation period of the vertical synchronization signal, and this vertical synchronization period signal becomes a switching signal for controlling the switching of the second changeover switch 196.

By the way, as shown in FIG. 18, when dropout occurs in the portion of the vertical synchronizing pulse in the signal (A) before correction, this portion is replaced with the signal (B) 1H before, and the dropout If correction is performed, the vertical sync pulse may be displaced in the corrected signal (C) because there is no horizontal correlation (in Fig. 18, the position of 1 / 2H in the circle marked with ○). There is a gap). When the vertical sync pulse is displaced as described above, a field error may occur in the subsequent video equipment. However, if the dropout correction of the vertical sync pulse is prohibited, there is a possibility that the sync disturbance will occur.

Therefore, as shown in FIG. 17, when the dropout occurs in the vertical synchronizing pulse portion, it is equal to the signal level of the vertical synchronizing signal output from the vertical synchronizing level generating circuit 198 instead of the signal 1H before. By supplying a level correction signal to the first changeover switch 190 and replacing the digitized video signal with this, dropout correction can be performed without causing a positional deviation of the vertical synchronizing pulse.

It should be noted that in FIG. 17, dropout correction is performed by the signal 1H before, but at this time, the phase of the chroma signal is opposite in phase as it is. Therefore, the circuit surrounded by the broken line in FIG. 17 inverts the phase of the chroma signal, thereby making it possible to color the dropout correction signal. Therefore, in the case where the dropout correction is only for the luminance signal (monochrome), the signal 2H before (the black signal is in phase), and the like, the circuit indicated by the broken line is excluded. The address generation circuit 197, vertical synchronization level generation circuit 198, and switching signal generation circuit 199 are system controllers.
18 and may be replaced with the 1H counter 183, gate circuit 182A, 1-frame counter 189, gate circuit 182B, etc. in FIG.

The dropout detection circuit 17 in FIG. 1 (A) has a level comparator configuration, and as shown in FIG. 19, the output signal of the square sum circuit 72 of the FM detection circuit 7, that is, the digitized FM video signal ( The dropout detection signal (C) is output by detecting that the signal level of the squared signal (B) of the envelope component of A) has become a predetermined value or less. According to this configuration, the dropout detection circuit can be configured only by adding the level comparator to the FM detection circuit 7,
The dropout can be surely detected by a simple circuit configuration, and the detection operation is performed digitally, so that stable characteristics can be obtained.

Note that the detection output may be disturbed by ringing (the portion surrounded by the alternate long and short dash line in FIG. 19B) that occurs in the output of the square sum circuit 72 due to a sudden change in the envelope, but the square sum circuit The dropout detection signal (D) is also output as a dropout section for n ₁ points before the signal level of the output signal (B) of 72 is below a predetermined value and n ₂ points after the level is above a predetermined value. By doing so, the subsequent correction can be surely executed. At this time, ringing may occur by the delay of the Hilbert converter 70, so that n ₁ and n ₂ are set equal to or longer than the delay time n of the delay circuit 71.

In the signal separation circuit 14 in FIG. 1 (B), control signals such as a frame number and a stop code are separated and extracted together with a color burst signal, a horizontal synchronization signal, a vertical synchronization signal and the like included in the digitized video signal. For this signal separation, as shown in FIG. 20, a first reference level V _TH1 for separating and extracting the control signal A and a second reference level V _TH2 for separating and extracting the synchronization signal B are provided. Is set.

The configuration of this signal separation circuit 14 is shown in FIG. In the figure, the pedestal level detection circuit 13 detects the pedestal level of the digitized video signal as described above, and the minimum value detection circuit 20 detects the minimum value level of the digitized video signal within a predetermined period. The configuration of the minimum value detection circuit 20 will be described in detail later. The first and second reference levels V _TH1 and V _TH2 are set based on the respective detection levels of the pedestal level detection circuit 13 and the minimum value detection circuit 20, and the reference level generation circuit 140 is the pedestal level detection circuit. The first reference level V _TH1 is generated by adding a constant value to the level based on only the detection level of 13 and the reference level generation circuit 141 detects the detection levels of the pedestal level detection circuit 13 and the minimum value detection circuit 20. Then, the intermediate value of both levels is generated as the second reference level V _TH2 . The reference level generation circuits 142 and 143 are based on only the detection level of the minimum value detection circuit 20 and have the first and second reference levels V _TH1 ,
Generates V _TH2 .

The outputs of the reference level generation circuits 140 to 143 are supplied to the selector 144, which is the system controller 18
When the synchronization establishment determination signal is supplied from, that is, when the synchronization is stable, the first and second reference levels V _TH1 and V _TH2 generated by the reference level generation circuits 140 and 141 are selected, and other than that, Reference level generation circuit 14 when synchronization is unstable
The first and second reference levels V _TH1 and V _TH2 generated at 2,143 are selected. The system controller 18 determines whether or not synchronization is established by comparing the reference synchronization pulse based on the internal clock with the extracted synchronization pulse. The first and second reference levels V _TH1 and V _TH2 selected by the selector 144 are supplied to the signal detection circuit 145c, and the signal detection circuit 145c passes the LPF 145a on the basis of these reference levels V _TH1 and V _TH2. The control signal A and the synchronization signal B are separated and extracted from the encoded video signal.

That is, in the signal separation circuit 14 having the above-described configuration, when the 1H synchronization is stable, the pedestal level and the first and second reference levels V _TH1 and V _TH2 set based on the pedestal level and the minimum value level are set. As the reference, or when synchronization is unstable such as when the spindle motor 24 starts rotating or during CLV disk search or scan, the pedestal detection position is not fixed and its value is not fixed, so it is set based on only the minimum value level. The first and second reference levels V
_The control signal A and the sync signal B are separated and extracted based on _TH1 and V _TH2 . According to this, stable and reliable signal separation is performed not only when synchronization is stable but also when synchronization is unstable. The separated sync signal B is input to the HV separation circuit 145d, and HS from the system controller 18 is input.
The horizontal sync signal is separated by detecting the fall when the gate signal is at a high level. Also, the synchronization signal B is HV
The separation circuit 145d performs integration processing and separates the vertical synchronization signal based on a predetermined reference level. The digitized video signal is input to fscBPF145b together with LPF145a.
A color burst signal including a color signal component is output from b.

By the way, regarding the detection of the synchronizing signal in the signal detecting circuit 145c, as shown in FIG. 22, the digitized video signal is sampled at every predetermined clock (the x mark in the figure is a sampling point), and the signal level of the synchronizing signal is a reference The sync signal is detected when the level exceeds V _TH2 . The configuration of this synchronization signal detection circuit is shown in FIG. In the figure, the subtractor 146, which receives the reference level V _TH2 from the reference level generation circuit 141 (or 143) and the digitized video signal that has passed through the LPF 145a, is a signal of the video signal with respect to the reference level V _TH2 at each sample point. The level difference between the levels is calculated, and at the same time, a sample point whose video signal level is lower than the reference level V _TH2 is detected as a synchronization signal. Subtractor
The level difference signal calculated in 146 is supplied to the delay circuit 147, the code determination circuit 148, and the storage device 149 such as a ROM (read only memory). The delay circuit 147 has a delay amount corresponding to one clock, delays the level difference signal from the subtractor 146, and supplies it to the code determination circuit 148 and the storage device 149. The sign determination circuit 148 has the output A of the delay circuit 147 being positive and the subtractor 14
The output B of 6 is in a negative state, that is, the output A of the delay circuit 147 has a level difference at the sample point a immediately before exceeding the reference level V _TH2 , and the output B of the subtractor 146 immediately after exceeding the reference level V _TH2. It is determined that there is a level difference at the sample point b, and a determination signal is supplied to the storage device 149.

A time table as shown in FIG. 24, for example, is stored in advance in the storage device 149, and the storage device 149 stores the code determination circuit 1
The corresponding time information is output based on the outputs of the delay circuit 147 and the subtractor 146 when the determination signal is generated from 48, that is, the level differences A and B at the two sample points a and b. Both the inputs A and B and the output of the storage device 149 are, for example, 4-bit data, and the first 1 bit of the 4 bits of the inputs A and B is a sign bit, which is represented by 2's complement. The time information output from the storage device 149 is the time difference between the time point c at which the signal level of the synchronization signal exceeds the reference level V _TH2 and the sampling point a or b. Even if they do not match with, the position of the falling edge of the sync signal can be accurately detected.

Next, the minimum value detection circuit 20 in FIG. 21 will be described. In FIG. 25, the counter 200 generates a first period pulse every 1H equivalent period by counting a clock, and also generates a second period pulse every longer period than 1H equivalent period. These period pulses are supplied to the selector 201, and in the steady state, the first periodic pulse is
In a non-steady state in which the rotation of the disk is unstable, such as when the spindle motor 24 starts to rotate or during CLV search or scan, the second period pulse is selected and supplied to the register 202 and the averaging circuit 203. The comparator 204, which receives the digitized video signal of the output of the LPF 145a as one input, compares the input data A with the data B stored in the register 202 at every clock generation, and the smaller data is stored in the register 20.
Supply to 2. However, the comparator 204 stops its operation when a dropout occurs. register
Since 202 is reset by the first or second period pulse supplied from the selector 201, the register 202 stores the smallest value from the previous reset time. The minimum value stored in the register 202 is the first or second
Is loaded into the averaging circuit 203 every time a pulse is generated,
The averaging circuit 203 averages the minimum values of two or more detection periods and finally outputs the minimum values.

In such a configuration, since the minimum value normally appears in the video signal during the synchronizing signal period, the 1H period is set as the detection period (generation interval of the first period pulse), but when the rotation of the spindle motor 24 rises. During non-steady state such as CLV search or CLV search, the rotation of the disk is not stable and the length of 1H period varies.
At this time, if the minimum value is detected at the normal interval based on the first period pulse, the sync signal may not be included in the interval. Therefore, in the non-steady state, the synchronization signal is included in the detection period by using the second period pulse generated every period longer than the 1H period, so that the minimum value level can be reliably detected. Therefore, the fluctuation of the minimum value level can be reduced. In addition, when a dropout occurs, a value lower than the signal level of the sync signal may be generated temporarily.However, in the dropout period, the operation of the comparator 204 is stopped and the detection operation is prohibited, so that the minimum value is reached. It is possible to prevent false detection of.

Further, the dropout detection signal resets the counter 200, and the counter 200 starts counting again for a predetermined period after the dropout. Therefore, even if the synchronization signal portion is lost due to the dropout, a pulse for the next period is generated. By this time, the level of the sync signal portion can be surely detected.

The clock generation circuit 21 in FIG. 1B is a reference horizontal synchronizing signal from the reference signal generator 22 or a signal separation circuit 14.
4fsc (fsc is the subcarrier frequency) and 4Nfsc (eg
12fsc) clock is generated and has a PLL (Phase Locked Loop) circuit configuration. The 4fsc and 4Nfsc clocks generated here are used as clocks for digital signal processing. The sampling clock of the A / D converter 4 and the signal processing clock up to the video LPF10 are set to 4Nfsc, and output from the video LPF10. Downsample to 4fsc. The configuration of the clock generation circuit 21 is the 26th
Shown in the figure. In the figure, a phase comparator 210 using a color burst signal as a comparison reference input is provided with sampling pulses CK ₁ , CK supplied through a sampling pulse generation circuit 211.
Phase comparison is performed in response to ₂ . If you want to lock the PLL to the reference horizontal sync signal or horizontal sync signal,
Instead of using the phase comparator 210, another phase comparator (not shown) is used to perform a phase comparison between one of these signals and the signal of f _H obtained by dividing 2fsc by 1/455 and inputting its output to the LPF 212. To do.

Only the case of locking to the color burst signal will be described below. The comparison output of the phase comparator 210 is supplied to the D / A converter 213 via the LPF 212, converted into an analog signal, and becomes a control signal of a VCO (voltage controlled oscillator) 214. VCO214
The oscillation frequency of is set to 12fsc, which is output as it is as the clock 12fsc, and the 1/3 frequency divider 215 outputs 4fs.
divided by c. This clock 4fsc is output as it is, becomes one input of the sampling pulse generation circuit 211, and is further divided into fsc by the 1/2 dividers 216 and 217 and becomes the comparison input of the phase comparator 210. The gate pulse generated by the gate pulse generating circuit 218 is supplied to the sampling pulse generating circuit 211 as another input. Therefore, the sampling pulses CK ₁ and CK ₂ are supplied to the phase comparator 210 only during the generation period of the gate pulse. Will be. The gate pulse generation circuit 218 generates a gate pulse (B) in synchronization with 4fsc based on the horizontal synchronizing signal, as shown in FIG. 27, only during a period corresponding to the central portion where the amplitude of the color burst signal (A) is constant. To do.

In the phase comparator 210, as shown in FIG. 28, the color burst signal becomes one input of the adder / subtractor 219, 220, each adder / subtract output becomes the other input of the adder / subtractor 219, 220 via the delay circuits 221, 222, and the divider 223. Divided by. The addition / subtraction (±) control of the adders / subtractors 219, 220 is performed based on the clock pulse fsc (B) shown in FIG. 29 so that addition is made at the sample points S ₁ and S ₂ and subtraction is made at the sample points S ₃ and S _4. . However, when a track jump is performed during still image playback, the phase of the color burst signal changes by 180 °, so the clock pulse fsc
The phase of (B) is inverted to maintain the PLL lock. This is performed by controlling the 1/2 frequency divider 217 by the chroma inversion control signal supplied from the system controller 18 of FIG. 1 (B).

The sampling pulse generation circuit 211 is composed of a D-type flip-flop, and sampling clocks CK ₁ , CK
Reference numeral ₂ is synchronized with 4fsc and has half the frequency thereof and opposite phases to each other, and becomes the clocks of the delay circuits 221 and 222 only when the gate pulse is at a high level. As a result, assuming that the amplitude of the color burst signal (A) is A,
ΣA sin θ is derived as the output of the delay circuit 221, ΣA cos θ is derived as the output of the delay circuit 222, and tan θ is derived as the output of the divider 223. And this ratio calculation power tan
The phase difference θ is obtained by passing θ through the tan ⁻¹ circuit 224.

That is, the phase difference θ in the phase comparator 210 can be calculated from the following equation.

θ = tan ⁻¹ {Σ [(S ₁ −S ₃ ) / (S ₂ −S ₄ )]} where S ₁ = A · sin θ S ₂ = A · cos θ S ₃ = −A · sin θ S ₄ = -A · cos θ By the way, as is clear from the above equation, if the amplitude A of the color burst signal (A) is not constant within 1H, the loop characteristics due to a slight error in the detected phase difference θ and a change in the loop gain of the PLL. Changes will occur.

However, in the clock generation circuit 21 described above, the gates are applied to the sampling pulses CK ₁ and CK ₂ for determining S _{1 to} S ₄ , so that the phase comparison is performed only during the period when the amplitude A of the color burst signal (A) is constant. Since this is done, the above-mentioned inconvenience does not occur.

In the above configuration, the sampling pulse is gated to perform the phase comparison only in the central portion of the color burst signal. However, it goes without saying that the color burst signal itself may be gated. . In this case, since it is a digital gate, it is possible to accurately extract only the central portion of the color burst signal as compared with an analog switch or the like. Further, in FIG. 26, the arrangement relationship between the LPF 212 and the D / A converter 213 may be reversed.

In FIG. 1B, the reference signal generator 22 is composed of a crystal oscillator or the like, and generates a 4 fsc reference signal and a reference horizontal synchronizing signal. The spindle servo circuit 23 controls the drive of the spindle motor 24 according to the phase difference between the reference horizontal synchronizing signal from the reference signal generator 22 and the horizontal synchronizing signal from the signal separating circuit 14. In the chroma inversion circuit 25, the still (stationary),
The phase of the chroma (color) signal is inverted as necessary to maintain the color framing even during special reproduction such as slow motion.

The structure of the chroma inversion circuit 25 is shown in FIG. In this figure, the digitized video signal is a 1H delay circuit 270, an adder 2
Supplied to 71. The output of the adder 271 is the level adjustment circuit 272.
The signal level is halved at and then supplied to the subtractor 273. The subtraction output of the subtractor 273 is supplied to the adder 275 via the phase linear acyclic digital BPF 274, and the adder 275
The addition output of is supplied to the changeover switch 276.

The delay output of the delay circuit 270 is supplied to the delay circuit 277 having the same delay amount as the subtractor 273 and the BPF 274, and is also supplied to the adder 271 via the 1H delay circuit 278. The delayed output of the delay circuit 277 is supplied to the adder 275 and the changeover switch 276.
The changeover switch 276 is appropriately changed over by the chroma inversion control signal supplied from the system controller 18 of FIG. 1 (B). With such a configuration, a 2- and 3-line correlation comb filter is configured, and the subtraction output of the subtractor 273 is 1
A chroma signal (-2C) having a doubled level in anti-phase with respect to the delayed output of the H delay circuit 270 (denoted as Y + C).
This chroma signal has its unnecessary component removed by the BPF 274 and then the delay output (Y
+ C) is added by the adder 275, and the digitized video signal (b) having the chroma signal inverted with respect to the delay output (a) of the delay circuit 277 is obtained as an addition output. In special reproduction such as still or slow reproduction, color framing can be maintained by switching the changeover switch 276 with the chroma inversion control signal from the system controller 18 in FIG. 1 (B).

In FIG. 1B, the output of the chroma inverting circuit 25 is supplied to the video processing circuit 38. The video processing circuit 38 performs character insertion, MCA code suppression, squelch, and the like.
The digitized video signal passed through the video processing circuit 38 is written in the buffer memory 39 by the 4fsc clock generated by the clock generation circuit 21 based on the color burst signal extracted from the reproduced video signal. This buffer memory
The read from 39 is 4 fsc generated by the reference signal generator 22.
Made by the reference clock of. Thus, by reading from the buffer memory 39 with a stable reference clock that is not related to the reproduced signal, the jitter of the reproduced signal can be absorbed, and so-called tangential servo and color correction circuit are unnecessary. . The digitized video signal read from the buffer memory 39 is converted into an analog signal by the D / A converter 40 and supplied to the output terminal 42 via the LPF 41.

The system controller 18 has the following main functions. That is, 1. The various servo systems are controlled according to the commands from the operation unit such as the panel switch and the remote control and the state signals from the servo system, and the player is caused to perform various operations.

2. Read the frame number and chapter number from the control signal.

3. Generates a signal to synthesize the frame number, chapter number, etc. on the screen.

4. Synchronize the internal counter with the horizontal and vertical sync signals and decode the counter output to generate various timing signals.

5. Controls the PLL loop for clock generation. A specific configuration for realizing the fourth function of the above main functions will be described below.

In FIG. 31, the horizontal synchronizing signal (▲ ▼) is used as the data (D) input, and the 4 fsc clock signal is used as the clock (C
A K-input D-type flip-flop 180 is provided, and the Q output of this flip-flop 180 is a NAND gate 181.
It becomes one input of B. The NAND gate 181B receives the horizontal synchronizing signal supplied via the inverter 181A as another input, and its output becomes the load (L) input of the 1H counter 183. The gate circuit 182A decodes the output of the 1H counter 183 and generates the HS gate signal for a predetermined period to generate the HV of FIG.
The clock is input to the separation circuit 145d and at the same time, a clock HCK having a frequency f _H synchronized with the horizontal synchronization signal is generated. The HS gate signal is used in the HV separation circuit 145d to detect the fall of the horizontal synchronizing signal excluding the equalization pulse and separate the horizontal signal. In the initial state, the HS gate signal is always at a high level, and the 1H counter 183 is loaded at the falling edge of the sync signal, and then goes high only for a predetermined period so as to detect the falling edge of the horizontal sync signal in the 1H cycle. In the initial state or for some reason, if the 1H counter 183 is loaded and the 1 / 2H shift occurs due to the falling edge of the equalization pulse, the 1H counter 183 is not loaded after the vertical blanking period. It is detected in the controller 18 that this state has fallen, and the HS gate signal is constantly set to a high level again. The HV separation circuit 145d generates a pulse having a predetermined width based on the falling edge of the horizontal sync signal and outputs it as a horizontal sync signal. clock
The HCK is a signal with a duty ratio of 50% that becomes high level in the first half and low level in the second half, starting from the falling edge of the synchronization signal. The gate circuit 182A further generates various timing signals within 1H and supplies them to each circuit.

Vertical sync signal (VS) of positive polarity is D-type flip-flop 18
4,185 clock inputs. D flip-flop 1
Reference numeral 84 designates a VS gate signal output from the gate circuit 182B as a data (D) input, and when the vertical synchronizing signal rises during the period when the signal is at a high level, its Q output is at a high level,
The output becomes low level, and then the state is maintained until the reset signal becomes low level, and when the reset signal becomes low level, Q and the output are inverted. D-type flip-flop 18
Reference numeral 5 is for determining whether the vertical synchronizing signal is in the field 1 or in the field 2 by using the clock HCK output from the gate circuit 182A as a data input. When the level is low, the vertical sync signal rises, so the Q output is low and the output is high. In field 2, when the clock HCK is high, the vertical sync signal rises, so the Q output is high. Output goes low.
Q output of flip-flop 184 is data input, clock H
The D-type flip-flop 186, which uses CK as a clock input and the Q output of the flip-flop 185 as a clear input, has a high Q output at the rising edge of the clock HCK when the Q output of the flip-flop 184 becomes a high level in the field 2. In the field 1, the Q output remains low level.

The Q and output of the D-type flip-flop 184 are J and K inputs, the clock HCK is an inverted clock input, and the flip-flop 185
JK flip-flop 187 whose output is clear input
In the field 1, when the Q output of the D-type flip-flop 184 becomes high level, Q is output at the falling edge of the clock HCK.
The output goes high and in field 2 the Q output remains low. D-type flip-flop 186 and J
The NOR gate 188 having each Q output of the -K flip-flop 187 as two inputs loads the one-frame counter 189 of the next stage and resets the D-type flip-flop 184 by its output. Here, the reason why the load pulse is generated by using another flip-flop for each field is that the load pulse having a sufficient width in any field is sent to the 1-frame counter 189. The 1-frame counter 189 is a 525-ary counter that counts the clock HCK, and is loaded by the clock HCK when the output of the NOR gate 188 is low level. It is controlled by the output of the D-type flip-flop 185 so that the number becomes as large as possible.
The gate circuit 182B decodes the output of the 1-frame counter 189 to generate the VS gate signal described above for a predetermined period, and also generates a timing signal of H unit in one frame to supply it to each circuit.

Next, the fifth of the above-mentioned five functions of the system controller 18, that is, the function of controlling the PLL loop for clock generation will be described with reference to the flowchart of FIG. As mentioned above, this PLL has two phase comparators, one for locking the reference horizontal sync signal or the playback horizontal sync signal and the other for the color burst signal. Three loops can be selected by switching between the reference horizontal synchronizing signal and the reproduced horizontal synchronizing signal at the input part of the comparator and the phase comparator itself.
Referring to FIG. 32, in the initial state immediately after turning on the power or during forced acceleration of the spindle motor, first, the reference horizontal synchronizing signal obtained by the reference signal generator 22 (see FIG. 1 (B)) serving as the reference of the spindle servo. The PLL loop operates to lock to (step 1). When it is determined that the reference horizontal synchronizing signal is locked (step 2) and the horizontal synchronizing signal can be obtained from the reproduced video signal, the loop is switched to the reproducing horizontal synchronizing signal (step 3). At this time, if it is determined that the lock cannot be made (step 4), the process returns to step 1 to return the loop to the reference horizontal synchronizing signal again. If it is determined in step 4 that the reproduction horizontal synchronizing signal is locked, the presence or absence of a color burst signal is detected (step 5). If there is no color burst signal, the process returns to step 4 and the reproduction horizontal synchronizing signal remains locked. To do. Even in a black-and-white disc or a color disc, the vertical blanking period is in this state. If it is determined that there is a color burst signal, the PLL loop is switched to the color burst signal (step 6). If it is determined that the color burst signal cannot be locked (step 7), the process returns to the loop of the reproduction horizontal synchronizing signal in step 3, but if locked, the state of the color burst loop is maintained. However, at the same time, the synchronization with the reproduction horizontal sync signal is also monitored (step 8), and if either the lock with the color burst signal or the lock with the reproduction horizontal sync signal is released, it is regarded as out of lock and the reproduction horizontal sync signal is detected. Return to loop (step 3). At this time, if the reproduction horizontal synchronization signal loop cannot lock to the reproduction horizontal synchronization signal (step 4), the process is returned to the reference horizontal synchronization signal loop (step 1).

It should be noted that the determination of NO in steps 4 and 7 indicates that the vehicle cannot be locked within the predetermined period when the vehicle passes the first time, and that the vehicle is not locked when the vehicle passes the second time and thereafter.

The present system has been described above by showing the specific configuration of each circuit, but the present system is not limited to the A / D converter 4 and the D / A.
A major feature is that signal processing is performed digitally with the converter 40. In this way, by digitizing the signal, it becomes multifunctional, for example, colorization of the dropout correction signal that was monochrome, chroma inversion, high accuracy of YC separation by introducing a frame memory, or still image in CLV. Playback etc. becomes easy.

In FIG. 1 (B), the adder 12 and thereafter, the dropout correction circuit 19, the chroma inversion circuit 25, and the video processing circuit.
Each circuit is arranged in the order of 38 and buffer memory 39,
The arrangement is not limited to this arrangement. For example, as shown in FIGS. 33A and 33B, "dropout correction circuit 19 + chroma inversion circuit 25", "video processing circuit 38", and "buffer memory 39". The order of can be changed. However, since writing and reading of the buffer memory 39 are asynchronous, if there are other two after the "buffer memory 39" (in the case of FIG. 33 (B)), control signals for the other two and Timing signal resynchronization or delay is required. Also, if there is a "dropout correction circuit 19 + chroma inversion circuit 25" after the "video processing circuit 38" (33rd
In the case of (A), a control signal is required to inhibit the dropout correction in the dropout correction circuit 19 in the character portion when the video processing circuit 38 inserts a character.

Further, as shown in FIG. 34, RGB separation can also be performed digitally, and each digital signal separated by the RGB separation circuit 43 is analogized by the D / A converter 44 and LPF
By supplying each analog output terminal 46R, 46G, 46B via 45, and connecting these terminals to a monitor TV (television) with RGB input, the RGB separation circuit in the TV is not used. Therefore, the image quality can be improved. Also, when using a digital TV capable of RGB input as it is digitized, each digital signal separated by the RGB separation circuit 43 is directly output to each digital output terminal 47R, 47G without passing through the D / A converter. Can be output via 47B.

In this RGB separation, in this system, the clock of the A / D converter 4 is set to 4Nfsc (N is an integer of 2 or more) and the 4fsc clock is locked to the color burst signal of the video signal. (Demodulation) can be easily performed. Hereinafter, a case will be described where demodulation is performed using RY and BY signals, but demodulation can be similarly performed using I and Q signals.

In the NTSC system, the phase of the chrominance signal is as shown in FIG. 35, which is quadrature quadrature modulated and frequency-multiplexed with the luminance signal. The relationship between the RGB signal and the luminance signal Y is shown in the following equation.

Y = 0.30R + 0.59G + 0.11B (1) Further, the color signal C in the video signal is expressed by the following equation.

Where ωc is the angular frequency of the color carrier, and ωc = 2π
× 3.58MHz.

When the phase of the sampling frequency of 4fsc is locked at 0 ° with respect to the color burst signal, each sampling point is ± (RY) as shown in FIG. 36 from FIG. 35 and equation (2).
It turns out that it becomes /1.14, ± (BR) /2.03. Also,
From equation (1) and equation (2) And an RGB signal is obtained. To obtain the I and Q signals, the color burst signal may be locked in a phase of ± 33 ° or ± 57 °. From the above, it can be seen that RGB demodulation can be easily performed by locking the clock to the color burst signal.

In the above embodiment, the case of application to the NTSC video disc player has been described, but the present system can also be applied to VTR playback side signal processing, PAL, SECAM video disc players and the like. .

As described above, according to the present invention, when the synchronization is stable, the first reference level for separating the control signal is set based on the pedestal level, and the synchronization signal is set based on the pedestal level and the minimum value level. Since a second reference level for separating is set and the first and second reference levels are set based on only the minimum value level when the synchronization is unstable, the pedestal level can be detected when the synchronization is unstable. Since the reference level can be set even without synchronization, it is possible to stably and reliably separate and extract the control signal and the synchronization signal not only when the synchronization is stable but also when the synchronization is unstable.

[Brief description of drawings]

1 (A) and 1 (B) are block diagrams showing an embodiment of a video signal reproducing apparatus according to the present invention, and FIG. 2 is a block diagram showing a concrete configuration of the digital BPF in FIG. 1 (A),
FIG. 3 is a block diagram showing an example of the structure of the video LPF in FIG. 1 (B), and FIGS. 4 (A) to (C) are spectrum diagrams of respective parts (A) to (C) in FIG. FIG. 5 is a phase characteristic diagram of the IIR filter in FIG. 3, and FIGS. 6 to 8 are block diagrams showing the specific configurations of the FIR filter, the downsampling circuit and the IIR filter in FIG.
The figure is a block diagram showing another configuration of the video LPF, FIG. 10 is a block diagram showing another configuration of the bit reduction processing in FIG. 1 (B), and FIG. 11 is the pedestal level detection in FIG. 1 (B). FIG. 12 is a block diagram showing the configuration of an example of the circuit, FIG. 12 is an operation waveform diagram of each part in FIG. 11, and FIG. 13 is a fall detection circuit, a rise detection circuit, a timing signal generation circuit and a sample period signal generation in FIG. FIG. 14 is a block diagram showing a specific configuration of the circuit, FIG. 14 is a block diagram showing another configuration of the pedestal level detection circuit, FIG. 15 is an operation waveform diagram of each part in FIG. 14, and FIG. 16 is a standing waveform in FIG. FIG. 17 is a block diagram showing a specific configuration of the falling detection circuit and the timing signal generation circuit, FIG. 17 is a block diagram showing a specific configuration of the dropout correction circuit in FIG. 1 (B), and FIG. 18 is a circuit of FIG. Waveform to explain the operation FIG. 19 is a waveform diagram for explaining the circuit operation of the dropout detection circuit in FIG. 1 (A), and FIG. 20 is a video signal and reference level in the signal separation circuit in FIG. 1 (B). 21 is a block diagram showing a specific configuration of the signal separation circuit, FIG. 22 is a waveform diagram for explaining the operation of the signal detection circuit in FIG. 21, and FIG. Block diagram showing the specific configuration of the signal detection circuit, FIG. 24 is in FIG.
FIG. 25 shows an example of a time table stored in ROM, FIG. 25 is a block diagram showing a concrete configuration of the minimum value detection circuit in FIG. 21, and FIG. 26 is a concrete view of the clock generation circuit in FIG. 1 (B). FIG. 27 is a block diagram showing a schematic configuration, FIG. 27 is a waveform diagram of each part of FIG. 26, FIG. 28 is a block diagram showing a concrete configuration of the phase comparator in FIG. 26, and FIG. 29 is a circuit operation of FIG. FIG. 30 is a waveform diagram for explaining the above, FIG. 30 is a block diagram showing a concrete configuration of the chroma inverting circuit in FIG.
The figure is a block diagram showing a configuration of a part of hardware for performing a predetermined function of the system controller in FIG. 1 (B), FIG. 32 is a flowchart of the predetermined function of the controller, FIG. 33 (A), (B) is a block diagram showing a modified example of the present system, FIG. 34 is a block diagram showing still another modified example, FIG. 35 is a phase characteristic diagram of a color signal used for explaining the principle of RGB separation in FIG. 34, FIG. 36 is a waveform diagram of the signal at each sample point. Description of main part code 2 …… Analog LPF, 4 …… A / D converter 6 …… Digital BPF 7 …… FM detection circuit, 10 …… Video LPF 13 …… Pedestal level detection circuit 14 …… Signal separation circuit 17 …… Dropout detection circuit 18 …… System controller 19 …… Dropout correction circuit 21 …… Clock generation circuit 22 …… Reference signal generator 24 …… Spindle motor 25 …… Chroma inversion circuit 38 …… Video processing circuit 39 …… Buffer memory 40 …… D / A converter

Claims (1)

[Claims] 1. A signal separation circuit for separating and extracting a control signal and a synchronization signal included in a video signal, wherein a pedestal level detection circuit for detecting a pedestal level of the video signal and at least a synchronization signal period of the video signal are provided. A minimum value detection circuit that detects a minimum value level within a predetermined period including the first reference level based on the detection level of the pedestal level detection circuit, and each of the pedestal level detection circuit and the minimum value detection circuit. A first reference level setting circuit that sets a second reference level based on a detection level, and a second reference that sets the first and second reference levels based only on the detection level of the minimum value detection circuit. The level setting circuit and the first and second reference levels by the first reference level setting circuit when the synchronization is stable, and the second reference level when the synchronization is unstable. The by the level setting circuit 1 and the second
Selecting means for selecting each of the reference levels of the control signal and the control signal based on the first reference level selected by the selecting means.
A signal separation circuit for separating and extracting each of the synchronization signals from the video signal on the basis of the reference level.