JP2570706B2 - Digital color signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital color signal processing circuit, and more particularly to a simple circuit for reducing color noise and time axis fluctuation of a digital color signal reproduced from a recorded recording medium. The present invention relates to a processing circuit that can be stably performed with a configuration.

2. Description of the Related Art With the rapid progress and development of semiconductor circuit element technology and IC manufacturing technology in recent years, a large amount of information such as video signals can be digitally processed at high speed and at low cost. On the other hand, digitization enables accurate temporary storage of signal values, easy implementation of complex filters and time-varying filters that adaptively change parameters, and the ability to significantly reduce the cost of mass-produced ICs. Digital ICs have power supply voltage fluctuations,
It is resistant to noise, temperature changes, changes over time, etc., has a high reliability and can operate stably, and has many features such as non-adjustment by digitizing. For this reason, it is considered that the VTR also digitizes most of the recording / reproducing circuit.

Problems to be Solved by the Invention Like the conventional analog VTR, the above-mentioned digital VTR has an APC circuit for reducing the time axis fluctuation of the reproduced digital color signal, and has a CPC for reducing the color noise.
The configuration includes an NR circuit. Here, in the analog VTR, the phase detector in the APC circuit is connected before the cyclic color noise reduction circuit (CNR circuit) having the feedback comb filter using the 1H delay circuit, so that the CNR circuit is used. The characteristics of the APC circuit do not change.

However, in a digital VTR, an input digital signal of the 1H delay circuit is often subjected to a decimation process in advance in order to reduce the number of elements required for the 1H delay circuit. This decimation process is a resampling process for reducing the number of transmission samples per unit time (decreasing the sampling frequency) by thinning out digital signals. In general, it is often difficult to perform phase detection from a digital signal that has been subjected to such decimation processing (thinning processing).

For this reason, the input digital color signal of the phase detector in the APC circuit in the digital VTR is a digital color signal subjected to an interpolation process (interpolation process) for returning the data decimated by the decimation process to the original frequency. Signal. On the other hand, as described above, the input digital signal of the CNR circuit using the 1H delay circuit in order to reduce the circuit scale is a digital color signal subjected to decimation processing.

Therefore, in general, the digital color signal output from the CNR circuit is interpolated and then supplied to the phase detector in the APC circuit, and is inserted and connected in a loop of the CNR circuit.

However, with such a configuration, the transfer function of the APC circuit changes between when the operation of the CNR circuit is on and when it is off, and the loop filter constant must be changed each time. On the other hand, since the APC circuit operates with a color burst signal, it is conceivable to adopt a configuration in which the CNR circuit is not operated only for the color burst signal. This is performed only for the digital color signal in the video period, and the noise reduction effect is reduced by half.

Accordingly, it is an object of the present invention to provide a digital color signal processing circuit which solves the above problem with a simple circuit configuration.

Means for Solving the Problems The digital color signal processing circuit of the present invention comprises an APC circuit or an APC circuit.
A digital color signal processing circuit having a cyclic color noise reduction circuit using a comb filter in a loop of a CC circuit, comprising: a decimation unit that performs decimation processing on a digital color signal; Adding means for delaying the original first color burst signal in the color signal and adding it as a second color burst signal; and performing color noise reduction processing only on digital color signals other than the second color burst signal. Color noise reduction means for extracting the synthesized digital color signal obtained by interpolation, and combining the synthesized digital color signal having undergone the interpolation processing with both the APC circuit and the ACC circuit or the AP.
An interpolator for supplying a detector in a loop of the C circuit, means for detecting the phase or amplitude of the second color burst signal by the detector, and a switch for removing the second color burst signal and outputting it to an output terminal Circuit.

The digital chrominance signal, which is a digital chrominance signal of the carrier chrominance signal reproduced from the recording medium, is decimated by the decimator, and is added by the adding means next to the horizontal blanking period in which the first color burst signal exists. The first color burst signal is delayed during the horizontal blanking period and added as a second color burst signal to become a composite digital color signal.
The synthesized digital color signal is supplied to a cyclic color noise reduction circuit using a comb filter and subjected to color noise reduction processing. The color noise reduction means performs color noise reduction processing only on the second color burst signal. The synthesized digital color signal not subjected to the above is taken out and supplied to the interpolator.

The synthesized digital color signal having the same frequency as the input digital color signal of the decimator after being subjected to the interpolation processing by the interpolator is supplied to the phase detector and the level fluctuation reduction circuit in the APC circuit provided for reducing the time axis fluctuation. ACC provided for
Among the amplitude detectors in the circuit, the phase is supplied to at least a phase detector, where the phase of the second color burst signal is detected, and the phase is supplied to a switch circuit, where the second color burst signal is removed. The digital color signal is output to the output terminal. Therefore, the added second color burst signal is supplied to the phase detector and the amplitude detector or the phase detector without being subjected to the color noise reduction processing by the CNR circuit, and the phase or the amplitude is detected. .

First Embodiment FIG. 1 is a block diagram showing a first embodiment of the circuit of the present invention. In FIG. 1, an input terminal 1 is a digital signal obtained by performing analog-digital conversion on a reproduced low-frequency conversion carrier color signal separated from an analog color video signal reproduced from a recorded magnetic tape by a rotating head. A signal comes in. This input digital signal is supplied to the frequency converter 2
After being supplied to the NCO 14 and frequency-converted to a signal from a numerically controlled oscillator (NCO) 14, which will be described later.
Then, unnecessary frequency components are removed, and only a digital signal (digital chrominance signal) related to the carrier chrominance signal whose chrominance subcarrier frequency is set to a predetermined high frequency (for example, 3.58 MHz) is extracted.

This reproduced digital color signal is supplied to a thinning-out unit 3, where the sampling data is taken out every N (where N is a predetermined natural number) sampling period, and only one of the N pieces of sampling data is taken out. By thinning out (N-1) pieces of sampling data, the sampling frequency becomes 1 / N
It is converted to a digital color signal which is reduced twice. The digital chrominance signal subjected to the decimating process by the decimator 3 is supplied to the terminal 4 a of the switch circuit 4 and supplied to the memory 5.

The output digital color signal of the decimator 3 is represented by a in FIG.
As shown in, n-th line in the digital data composed of a (horizontal scanning line) in the color burst signal CB _n and carrier chrominance signal C _n, similarly n + 1 th in the line a color burst signal CB _{n + 1} and the carrier chrominance signal C _{n + 1} , and in the (n + 2) th line, the color burst signal CB _{n + 2} and the carrier color signal C _{n + 2}
This is digital data consisting of Although the waveform diagram shown in FIG. 2 is shown as an analog signal waveform for easy understanding, it is actually digital data.

The memory 5 writes only the color burst signal data based on the control signal from the control circuit 6, reads it out at the timing within the next horizontal blanking period, and outputs it to the terminal 4b of the switch circuit 4. Since the memory 5 only needs to have a capacity (the number of words) capable of storing one color burst signal data, a random access memory (RAM) or a shift register having a small storage capacity can be used. Control circuit 6
The horizontal synchronizing signal data separated from the reproduced digital luminance signal is supplied via an input terminal 7 to generate various control signals necessary for each circuit.

The switch circuit 4 normally selects and outputs the input reproduced digital color signal at the terminal 4a based on the switching control signal from the control circuit 6, but is switched to the terminal 4b only during the period when the color burst signal data is read from the memory 5. And selectively outputs the color burst signal data. Therefore, the output signal of the switch circuit 4 becomes as shown by b in FIG. 2 (B). As shown in FIG. 2B, the output digital chrominance signal of the switch circuit 4 is supplied to the first color burst signal during the horizontal blanking period (specifically, the back porch) where the original color burst signal should exist. Is multiplexed, and the first color burst of the line 1H before is also included in a part of the next horizontal blanking period (specifically, the front porch excluding the back porch and a specific position in the horizontal synchronization signal period). The signal becomes a composite digital color signal multiplexed as a second color burst signal.

The synthesized digital color signal is supplied to a CNR circuit 9 and a terminal 10b of a switch circuit 10 through a comb filter 8 for reducing a crosstalk component from an adjacent track. The CNR circuit 9 is a color noise reduction circuit having a feedback comb filter inside. The CNR circuit 9 has a well-known circuit configuration for an analog processing circuit, and is a digital circuit. Therefore, both the comb filter 8 and the CNR circuit 9 have a delay circuit inside, and the delay time is NT
In the case of the SC type color video signal reproducing apparatus, one horizontal operation period (1H) is used, and in the case of the PAL system, two horizontal scanning periods (2H) are used.

The switch circuit 10 is based on the switching control signal from the control circuit 6 and, of the combined digital color signals output from the comb filter 8, an added second color indicated by hatching in FIG. 2 (B). It is connected to the terminal 10b only during the transmission period of the burst signal to selectively output the second color burst signal from the comb filter 8, and during other periods, it is connected to the terminal 10b.
The digital color signal output from the CNR circuit 9 is selectively output by being connected to the 10a side. Therefore, although the composite digital color signal is extracted from the switch circuit 10, only the second color burst signal is a signal that has not been subjected to the color noise reduction processing by the CNR circuit 9.

The interpolator 11 is supplied with the output composite digital color signal of the switch circuit 10 as an input signal, and 1 is a time interval of each sampling data of the input composite digital color signal.
(N-1) zeros are inserted in the sampling period, thereby generating a synthesized digital color signal of the sampling frequency with the sampling frequency substantially converted to N times. The synthesized digital color signal subjected to the above-described interpolation processing by the interpolator 11 is APC
It is supplied to a phase detector 12 in the circuit.

Based on the control signal from the control circuit 6, the phase detector 12
Only the phase of the second color burst signal that has not been subjected to the color noise reduction processing is detected from the input composite digital color signal. The output signal of the phase detector 12 passes through a loop filter 13 and is added to data for determining the free-run frequency of the NCO 14 by an adding circuit (not shown).
4 to variably control the output oscillation frequency. NCO
The output oscillation frequency of 14 is supplied to the frequency converter 2 to perform frequency conversion on the input digital color signal. More than
A digital chrominance signal whose time axis fluctuation is reduced by the APC loop operation is output from the frequency converter 2.

The output digital color signal of the interpolator 11 is supplied to a terminal 15a of the switch circuit 15. The switch circuit 15 is normally connected to the terminal 15a based on the switching control signal from the control circuit 6 to select and output the output composite digital color signal of the interpolator 11, but the period during which the second color burst signal is extracted Only the terminal 15b is switched and connected to prevent transmission to the output terminal 16. As a result, as shown schematically in FIG. 2C, the added second color burst signal is removed from the output terminal 16, and only the digital color signal c is output.

As described above, according to the present embodiment, since the APC operation is performed based on the phase of the second color burst signal irrespective of the ON / OFF operation of the CNR circuit 9, the required time axis reduction operation can be performed accurately. And for digital color signals
Since the CNR circuit 9 operates, the required color noise reduction effect is not halved.

Next, a second embodiment of the circuit of the present invention will be described with reference to FIG. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, a comb filter 18 removes a crosstalk component from an adjacent track of the reproduced digital chrominance signal which has been decimated by the decimator 3 and supplies the same to a memory 19 and a CNR circuit 9, respectively.
The memory 19 is a RAM or a shift register having the same small storage capacity as the memory 5, and writes the first color burst signal in accordance with a control signal from the control circuit 20, and writes the first color burst signal in the next horizontal blanking period. The signal is read out as a burst signal and supplied to the terminal 10a of the terminal 10 of the switch circuit 10.

 This embodiment has a simpler circuit configuration than the first embodiment.

Next, a third embodiment of the circuit of the present invention will be described with reference to FIG. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 4, the input terminal
The reproduced digital luminance signal input to 23 is supplied to a 1H delay circuit 24.
After being converted into difference data between the previous line and the current line by a circuit including a subtractor 25, the difference data is supplied to a detector 26, where the difference is compared with predetermined reference data, and the level of the difference data (analog conversion) When the value is equal to or more than the reference data, it indicates that there is no vertical correlation. On the other hand, when the level is lower than the reference data, it is converted into a detection signal indicating that there is a vertical correlation. The 1H delay circuit 24, the subtractor 25, and the detector 26 constitute a luminance signal vertical correlation detection circuit 27, which outputs a binary detection signal of a high level when there is no vertical correlation and a low level when there is a vertical correlation. It is supplied to one input terminal of a two-input OR circuit 28.

To the other input terminal of the OR circuit 28, a control signal which is at a high level only during the transmission period of the second color burst signal and is at a low level during the other periods is supplied from the control circuit 30. The CNR circuit 29 receives, as an input signal, the synthesized digital color signal which has been subjected to the thinning process from the comb filter 8, and performs a predetermined color noise reduction process on the input signal during a period when the control signal is at a low level from the OR circuit 28. The operation is performed, the color noise reduction processing operation is stopped during the high level period, and the input signal is passed as it is.

As a result, the CNR circuit 29 does not perform the color noise reduction operation on the second color burst signal, and also performs the color correction on the digital color signal having no vertical correlation among the digital color signals in the video signal period. The noise reduction operation is not performed, and only the other digital color signals having a vertical correlation with the first color burst signal are taken out of the synthesized digital color signal subjected to the color noise reduction processing, and are output to the interpolator 11. Supplied to

This embodiment has the same features as the first embodiment, and furthermore, by stopping the color noise reduction processing operation for the digital color signal having no vertical correlation, the color noise can be reduced for the digital color signal having no vertical correlation. It is possible to prevent the occurrence of color bleeding in the vertical direction of the screen which occurs when the reduction processing operation is performed.

Next, a fourth embodiment of the circuit of the present invention will be described with reference to FIG. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 5, a digital signal input to an input terminal 1 is supplied to a frequency converter 2 through a digital multiplier 33. The control circuit 34 generates a control signal similar to that of the control circuit 6 and sends a control signal to the amplitude detector 35 in addition to the control signal to generate a second color burst signal which has not been subjected to color noise reduction processing. Only the amplitude is detected.

The amplitude detector 35 detects the amplitude of the second color burst signal in the synthesized digital color signal subjected to the interpolation processing, and the amplitude detection data is supplied to a subtractor 36, where a reference signal from an input terminal 37 is inputted. After being subtracted from the amplitude data and converted into difference data indicating the amplitude error of the second color burst signal with respect to the reference amplitude, the difference data is supplied to the digital multiplier 33 through the loop filter 38.

A circuit section extending from the input terminal 1 to the interpolator 11, and an amplitude detector
An auto-chroma control circuit (ACC circuit) forms a loop consisting of 35, a subtractor 36, and a loop filter 38.
And operates so that the amplitude of the second color burst signal is always constant.

According to the present embodiment, since the second color burst signal is not subjected to the color noise reduction processing, an accurate ACC operation can be performed regardless of whether the operation of the CNR circuit 9 is on or off. Also, since the second color burst signal is a signal obtained by delaying the first color burst signal, the level fluctuation of the second color burst signal (however, the level fluctuation here is not the digital signal waveform itself, but DA
The level variation of the analog carrier chrominance signal when converted is, of course, reduced by the ACC circuit, so that the level variation of the digital chrominance signal can be substantially reduced. The removed digital color signal is extracted.

It should be noted that the present invention is not limited to the above embodiment, and it is needless to say that the present invention can be applied to, for example, a carrier color signal in a PAL color video signal (in this case, a comb-shaped signal is used). Filters 8, 18, CNR circuits 9, 29
It is necessary to change the 1H delay circuit inside to the 2H delay circuit. ).

Effect of the Invention As described above, according to the present invention, of the APC circuit and the ACC circuit, at least the phase detection of the additional color burst signal that has not been subjected to the color noise reduction processing by the CNR circuit included in the loop of the APC circuit and Since the amplitude detection is performed, the time axis fluctuation and the amplitude fluctuation of the digital color signal can be accurately performed without switching the constant of the loop filter regardless of whether the operation of the CNR circuit is on or off. Since the digital color signal including the color burst signal of the above is subjected to the color noise reduction processing operation by the CNR circuit, the color noise can be sufficiently suppressed.
Furthermore, since a digital color signal subjected to thinning processing is supplied to a circuit having a delay circuit such as a CNR circuit or a comb filter for removing crosstalk, the circuit configuration can be simplified. Has many features, such as being easy to be integrated into an IC, and being small and inexpensive by being integrated into an IC, and being able to improve reliability compared to an analog circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the circuit of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 1, and FIGS. It is a block system diagram which shows 2nd-4th Example. 1 ... Digital signal input terminal, 3 ... Thinning device, 4,10,1
5… Switch circuit, 5,19… Memory, 6,20,30,34…
Control circuit, 8,18… Comb filter, 9, 29… Cyclic color noise reduction circuit (CNR circuit), 11… Interpolator, 12…
… Phase detector, 14 …… Numerically controlled oscillator (NCO), 16 ……
Digital color signal output terminal, 27: luminance signal vertical correlation detection circuit, 35: amplitude detector.

Claims (1)

(57) [Claims] An APC circuit for reducing a time axis variation of a digital chrominance signal which is a digital signal of a carrier chrominance signal reproduced from a recording medium, and an ACC for reducing a level variation.
A digital color signal processing circuit having a cyclic color noise reduction circuit using a comb filter in both circuits or in a loop of the APC circuit, and a thinning device that performs a thinning process on the digital color signal. The first color burst signal is delayed in the horizontal blanking period next to the horizontal blanking period in which the original first color burst signal in the thinned digital color signal exists, and the second color burst signal is delayed by the second blanking period. Adding means for adding a color burst signal as a color burst signal, and supplying the composite digital color signal extracted from the adding means to the color noise reduction circuit, whereby color is applied only to digital color signals other than the second color burst signal. The second color burst signal which has been subjected to noise reduction processing and the second color burst signal is left as it is to obtain a synthesized digital color signal which has not been subjected to color noise reduction. Means, an interpolator for performing an interpolation process on the synthesized digital color signal from the color noise reduction means to convert the same to the same frequency as the input digital color signal of the thinning-out device, and a phase detector in the APC circuit Or means for detecting only the phase or amplitude of the second color burst signal in the output composite digital color signal of the interpolator supplied to the amplitude detector in the ACC circuit, and the output composite digital color of the interpolator. A digital color signal processing circuit, comprising: a switch circuit for removing the second color burst signal from the signal and outputting the signal to an output terminal.