JP2630141B2 - Video signal recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal recording and reproducing apparatus.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram for explaining a main part of a recording system of a conventional VTR, and FIG. 5 is a block diagram for explaining a main part of a color signal reproducing system of the conventional VTR.
In both figures, the same components are denoted by the same reference numerals, and description thereof will be omitted. Hereinafter, a conventional technique will be described with reference to the drawings.

First, a recording system will be described with reference to FIG. 4. In the ADC 1, a video signal 1a supplied from a transmission line (not shown) has a frequency four times that of a carrier chrominance signal related to the video signal 1a. The analog signal is converted into a digital signal using the sampling clock, and the result is supplied to the YC separation circuit A1.

The YC separation circuit A1 separates a video signal 1a into a recording luminance signal 9a and a recording chrominance signal 7a using the line correlation of three lines. The video signal 1a is supplied to a first 1H delay circuit 2, where a 1H delayed video signal 2a obtained by delaying one horizontal scanning period (1H) is supplied to a second 1H delay circuit 3, which further outputs a 1H delay video signal. As with the 1H delay circuit 2, the 1H delay video signal 2a is delayed by one horizontal scanning period to obtain a 2H delay video signal 3a. The video signal 1a, the 1H delayed video signal 2a, and the 2H delayed video signal 3
a denotes BPFs 4, 5, and 6 having a color signal band substantially as a pass band.
, 1st, 2nd, 3rd color signals 4a, 5
a and 6a are supplied to the reproduction operation circuit 7, respectively.

The recording operation circuit 7 supplies a recording color signal 7 a obtained by performing an operation using line correlation to one input of a subtraction circuit 9.

[0006] The other input of the subtraction circuit 9 is 1H
The delayed video signal 8a obtained through a third delay circuit 8 for delaying the delayed video signal 2a substantially equal to the delay time of the BPFs 4, 5, and 6 is supplied, and the recording color signal 7a is subtracted from the delayed video signal 8a. As a result, a recording luminance signal 9a is obtained, and is supplied to a recording luminance signal processing circuit 11 via a DAC 10 for converting this signal from a digital signal to an analog signal. And
A recording luminance signal processing circuit output signal 11 a obtained by performing the FM modulation or the like in the recording luminance signal processing circuit 11 is supplied to one input of an addition circuit 14.

On the other hand, the recording color signal 7a is supplied to a well-known recording color signal processing circuit 13 via the DAC 12, where
A recording color signal processing circuit output signal 13a which has been subjected to so-called low frequency conversion and the like is supplied to the other input of the addition circuit 14.

The output signal 11a of the recording luminance signal processing circuit and the output signal 1 of the recording color signal processing circuit
3a is amplified by a recording amplifier (not shown) and recorded on a magnetic tape via a rotary transformer using a magnetic head disposed on a rotating drum.

Next, a reproducing system will be described with reference to FIG. 5. A reproduced video signal obtained by amplifying a signal reproduced from a magnetic tape (not shown) using a magnetic head by a reproducing amplifier via a rotary transformer is described. 20b is supplied to a well-known reproduced color signal processing circuit 20, where the reproduced color signal 20a that has been subjected to high frequency conversion and the like is supplied to the crosstalk removing filter B1 via the ADC 21.

[0010] This crosstalk removing comb filter B1
Is to remove crosstalk between adjacent tracks by using line correlation of color signals. That is, the reproduction color signal 2
0a, a 1H delay reproduced color signal 2b obtained by delaying the reproduced color signal 20b by 1H in the first 1H delay circuit 2, and 1H
A 2H-delayed reproduction color signal 2c obtained by subjecting the delayed reproduction color signal 2b to 1H delay by a second 1H delay circuit is supplied to a well-known reproduction operation circuit 22, and here, for example, a reproduction color signal 20a and a reproduction color signal 20a. 2H delayed reproduction color signal 2c is added to 1/2
Is added to the inverted 1H-delayed reproduction color signal 2b, and a signal obtained by multiplying the resultant signal by 1/2 is supplied to the reciprocating comb filter B2 as a crosstalk removal color signal 22a. The first and second delay circuits are also used as recording circuits, and are switched and connected using a switch circuit (not shown).

The reciprocating comb filter B2 improves the S / N of the crosstalk removing color signal 22a by using line correlation. That is, the difference between the preceding and succeeding lines having a small amplitude is regarded as noise, and the difference is subtracted from the input signal. First, the crosstalk removing color signal 22
a is supplied to an addition circuit 23, where a noise-removed color signal 26 from which noise has been removed to obtain a difference value between the preceding and following lines
a through the third 1H delay circuit 27 and the third 1H delay circuit output signal 27a and the crosstalk removal color signal 22a
Are added to obtain an addition circuit output signal 23a, which is supplied to the coefficient circuit 24.

A signal obtained by multiplying the addition circuit output signal 23a by a predetermined coefficient for determining the degree of improvement in S / N in the coefficient circuit 24 is obtained via a limiter 25 for limiting the amplitude to a constant value. The limiter output signal 25a is supplied to one input of a subtraction circuit 26. This limiter output signal 25a is a signal in which the difference value between the preceding and following lines is limited to a small amplitude, and is a signal that can be regarded as noise.

The subtraction circuit 26 subtracts the noise removal color signal 26a obtained by subtracting the limiter output signal 25a from the crosstalk removal color signal 22a supplied to the other input into D.
The signal is output via the AC 28, and this is added to the reproduced luminance signal output from the luminance signal reproducing system to which the reproduced video signal 20b is supplied, and supplied to a transmission line (not shown).

As described above, in the conventional VTR, a total of three 1H delay circuits are used for the recording system and the reconstruction system.

[0015]

However, the 1H delay circuit normally requires 910 samples when sampling at 4 fsc.
It is composed of a stage shift register and the like, and when a YC separation circuit A1, a crosstalk elimination filter B1, and a recursive comb filter B2 are added to an IC, a significant configuration is added.

Therefore, the present invention solves such a problem,
It is an object to reduce the configuration of a delay circuit as a whole device.

[0017]

SUMMARY OF THE INVENTION The present invention provides the following structure to solve the above-mentioned problems.

A video signal recording / reproducing apparatus having delay means for delaying a video recording signal and a video reproducing signal, respectively,
Information reducing means for reducing the information of the color signal relating to the video recording or video reproduction signal in synchronization with the carrier color signal; and interpolation for interpolating the reduced information reduced by the information reducing means using the correlation of the color signal. Means for performing a delay operation performed between the information reducing means and the interpolating means by using at least the delay means.

[0019]

FIG. 1 is a block diagram for explaining a main part of a reproducing system according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of an interpolation circuit, and FIG. It is a block diagram for explaining the main part of the reproduction system of the second embodiment, and the same components as those in FIGS. 4 and 5 are denoted by the same reference numerals and description thereof is omitted. Hereinafter, referring to the drawings,
An embodiment will be described. Note that the video recording signal includes, for example, a video signal and all the signals related to the video signal, and the video reproduction signal includes, for example, a reproduced video signal and all the signals related to the reproduced video signal. (First Embodiment) The main part of the recording system of the first embodiment is the same as the main part of the recording system described in the prior art with reference to FIG. The reproduction system will be described.

Here, the difference from FIG. 5 is that the sub-sampling circuit 30 is provided between the ADC 21 and the crosstalk removing comb filter B1, and the difference between the crosstalk removing comb filter B1 and the recursive comb filter B2. The first and second 1/2 delay circuits 31 and 32 related to the first 1H delay circuit 2 are provided in the crosstalk removing comb filter B1 in relation to the point where the interpolation circuit 33 is provided, and the above two points. And the second delay circuit 3 in the cyclic comb filter B2.
Is provided. Hereinafter, these points will be described in detail.

Now, the reproduced color signal 20a is supplied to the sub-sampling circuit 30, where it is sub-sampled. This operation will be described with reference to FIG. The signal shown in FIG. 3A is a carrier chrominance signal, and the signal shown in FIG. 3B is a 4f signal used by the ADC 21 synchronized with the carrier chrominance signal.
SC is a sampling clock, and FIG. 4C is a reproduced color signal 20a. The data in the reproduced color signal 20a is output as two consecutive data per one cycle of the carrier chrominance signal, and the two consecutive data are reduced as shown in FIG. Data C0, D0, C1,
Sub-sampling circuit output signal 30 with D1 etc. reduced
a is supplied to the crosstalk removing comb filter B1.

The sub-sampling circuit output signal 3
0a is respectively delayed by 1H period by the first and second 1/2 delay circuits 31 and 32 in the crosstalk removing comb filter B1. These first and second 1/2 delay circuits 31, 3
Reference numeral 2 denotes a half of the first delay circuit 2 used in the recording system. That is, for example, the first delay circuit 2
, The first and second 遅 延 delay circuits 31 and 32 have 2 fsc.
And a 455-stage shift register operating on
For example, when the first delay circuit 2 is composed of a memory such as a DRAM, the memory capacity of the first and second 1/2 delay circuits 31 and 32 becomes 1/2. Even with such a configuration, since the data amount of the sub-sampling circuit output signal 30a is デ ー タ of the data amount of the reproduced color signal 20a, 1H
The delay time of each period can be obtained, and the crosstalk removing color signal 22a from which the crosstalk has been removed can be output.
The first and second 1/2 delay circuits 31 and 32 are switched between a recording operation and a reproduction operation by a switch circuit (not shown).

The crosstalk removing color signal 22a is supplied to an interpolation circuit 33, where a sub-sampling circuit 30
Is interpolated. Here, FIG.
The interpolation data C0p and D0p shown in FIG.
p, Dnp and A1, B1 are generally An, Bn
, Cnp and Dnp can be obtained from the data before and after, and are determined by, for example, the following formula.

Cnp = − (An + An + 1) / 2, Dnp = − (Bn + Bn + 1) / 2 As described above, the interpolation circuit 33 outputs the interpolation circuit output signal 33
a is obtained and supplied to the reciprocating comb filter B2.
Then, a cyclic comb filter B2 is configured by using the second 1H delay circuit 3 instead of the third 1H delay circuit 27 described in the related art. The second 1H delay circuit 3 is switched between recording and reproduction by a switch circuit (not shown).

In this way, the first and second 1H delay circuits 2 and 3 are used for both recording and reproduction, and the data is reduced by using the sub-sampling circuit 30. Since the interpolation is performed by the interpolation circuit 33, the number of 1H delay circuits used can be reduced.

In the above-mentioned reproducing system, the crosstalk removing comb filter B1 and the reciprocating comb filter B2 are directly connected without the interpolating circuit 33, and the interpolating circuit 3
3 is provided between the cyclic comb filter B2 and the DAC 28, and the second 1H delay circuit 3 in the cyclic comb filter B2 is provided.
Of course, a circuit similar to the first and second 1/2 delay circuits 31 and 32 may be used. (Second Embodiment) The recording system of the second embodiment is the same as the recording system described in the background art, and the description is omitted. Also, in the reproduction system, the crosstalk removing comb filter B1 is used.
And a sub-sampling circuit 30 and an interpolation circuit 33 to further simplify the configuration of the 1H delay circuit of the reproduction system.

Referring to FIG. 3, the reproduction system of the second embodiment will be described. A sub-sampling circuit output signal 30a is supplied to one of the subtraction circuits 40, and a sub-sampling circuit output signal 30a is supplied to the other input. A signal delayed for 1H period is supplied via a 1/2 delay circuit 31 and a subtraction circuit output signal 40a obtained by subtracting the signal delayed for 1H period from the sub-sampling circuit output signal 30a is supplied to a coefficient circuit 41. Supplied. Then, in this coefficient circuit 41,
The crosstalk removing signal 22a obtained by multiplying the subtraction circuit output signal 40a by the coefficient "1/2" is used as a reciprocating comb filter B
Feed to 2.

The reciprocating comb filter B2 uses the second 1/2 delay circuit 32 to generate the crosstalk removal signal 22.
is supplied to the interpolation circuit 33, and the interpolation circuit output signal 33a obtained by interpolating the data reduced by the sub-sampling circuit 30 is converted to a DA signal.
The signal is output to a transmission path (not shown) via C28. In addition, the first,
The second 1/2 delay circuits 31, 32 are switched between recording and reproduction by a switch circuit (not shown).

As described above, 1H used in the reproducing system
The configuration of the delay circuit can be further simplified.

In the above-described embodiment, the sub-sampling circuit 30 and the interpolation circuit 33 have been described as being used in a recording system.

In the above-described embodiment, it goes without saying that the sub-sampling circuit 30 only needs to reduce the information of the chrominance signal in synchronization with the carrier chrominance signal.

In the above-described embodiment, the delay period of the delay circuit that is used for both recording and reproduction is 1H, but it is a matter of course that the present invention is not limited to this.

In the above-described embodiment, the delay circuit used for both recording and reproduction may be one that is used separately for the recording system and the reproduction system.
Of course, the present invention is not limited to the crosstalk removing filter B1 and the cyclic comb filter B2.

In the above embodiment, a VTR is described as an example of a device for recording and reproducing video signals.
The present invention, for example, reduces the capacity of the delay circuit used in a recording system or a reproduction system by reducing information of a color signal by a sub-sampling circuit and interpolating the result by an interpolation circuit via a delay circuit. In addition, since the above-described delay circuit is also used as another delay circuit used for a reproduction system or a recording system, the configuration of the delay circuit of the entire apparatus is reduced. It goes without saying that any device for recording and reproducing may be used.

[0035]

As described above, according to the present invention, the delay operation performed between the information reducing means and the interpolation means is performed by using at least the delay means for delaying the video recording and video reproduction signals, respectively. The configuration related to the delay operation of the entire video signal recording / reproducing apparatus can be reduced in accordance with the reduction information related to the color signal reduced by the information reduction unit.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a main part of a reproducing system according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the interpolation circuit.

FIG. 3 is a block diagram for explaining a main part of a reproducing system according to the first embodiment of the present invention.

FIG. 4 is a block diagram for explaining a main part of a recording system of a conventional VTR.

FIG. 5 is a block diagram for explaining a main part of a color signal reproduction system of a conventional VTR.

[Explanation of symbols]

 1a video signal (video recording signal) 2 first 1H delay circuit (delay means) 3 second 1H delay circuit (delay means) 7a recording color signal (video recording signal) 9a recording luminance signal (video recording signal) 20a reproduction Color signal (video reproduction signal) 20b Reproduction video signal (video reproduction signal) 30 Sub-sampling circuit (information reduction means) 31, 32 First and second 遅 延 delay circuits (delay means) 33 Interpolation circuit (interpolation means)

Claims (1)

(57) [Claims] 1. A video signal recording / reproducing apparatus having delay means for delaying a video recording and a video reproduction signal, respectively, wherein information of a color signal relating to the video recording or the video reproduction signal is reduced in synchronization with a carrier color signal. And an interpolating means for interpolating the reduced information reduced by the information reducing means by using the correlation of the color signals. At least a delay operation performed between the information reducing means and the interpolating means is provided. A video signal recording / reproducing apparatus characterized in that the video signal recording / reproducing apparatus is configured to use the delay means.