JPH04217196A - Picture signal processing circuit - Google Patents

Abstract

PURPOSE:To eliminate an offset from a linear successive color difference signal with offset by digital processing. CONSTITUTION:The pedestal period of a linear successive color difference signal with offset is extracted by a gate circuit 80, and an accumulated addition value of (n)-pieces of sample points is obtained by an adder 82 and a register 84. The accumulated addition value held in the register 84 is turned to be 1/n by a division device 94 to obtain the average value of the pedestal level. A subtracter 96 subtracts the median of the dynamic range from the output of the division device 94, and the subtracter 98 subtracts the output of the subtracter 96 from the linear successive color difference signal with offset. The output of the subtracter 98 becomes the linear successive color difference signal with the offset eliminated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing circuit.

0002

2. Description of the Related Art In a recording/reproducing device (for example, an electronic still camera system) that uses a small magnetic disk called a still video floppy as a recording medium, color components are FM-modulated in the form of a line-sequential color difference signal with an offset. and recorded on a magnetic disk. In the reproduction system, the offset of the line-sequential color difference signal with offset is removed and line-synchronized to form color difference signals R-Y, B-Y, which are modulated to form a chroma signal, which is separately processed for reproduction. A composite video signal is finally obtained by mixing with the luminance signal.

[0003] In addition, when reproducing signals recorded on a magnetic disk, signal dropouts (dropouts) occur due to defects in the electromagnetic conversion system. need to be compensated before synchronization separation. Furthermore, if only one field image signal is recorded, it is necessary to form another field image signal by interpolation and perform skew compensation.

0004

In recent years, as the prices of memories and other digital circuit elements have decreased and their performance has improved, it has become more advantageous to perform image signal processing digitally than with analog circuits. However, since the still video floppy is an analog recording medium, the problem is at what stage clamping and analog-to-digital conversion should be performed. Further, it is necessary to provide an offset removal circuit for a line-sequential color difference signal with an offset to a circuit configuration that is easy to convert into a digital IC.

An object of the present invention is to provide an image signal processing circuit that solves these problems.

[0006]

[Means for Solving the Problems] An image signal processing circuit according to the present invention includes an analog clamp circuit that clamps an analog offset line-sequential color difference signal at its pedestal level at predetermined intervals; a first A/D converter that digitizes the output of the first A/D converter; and an offset removal circuit that adjusts the pedestal level of the pedestal to a predetermined value.

[0007]

[Operation] The above analog clamp circuit converts the line-sequential color difference signal with offset into an analog signal at a single reference level.
Can be clamped. After digitization, the offset removal circuit described above performs a simple digital calculation to dynamically calculate the pedestal level of each horizontal line.
The amount of deviation from the median of the range can be determined, and therefore the pedestal level of each horizontal line can be adjusted to the median of the dynamic range. As a result, the offset of the line-sequential color difference signal with offset can be accurately and completely removed.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the main circuit configuration of an embodiment of the present invention, and FIG. 2 is a block diagram of a still video floppy playback circuit incorporating the circuit of FIG.

First, FIG. 2 will be explained. Reference numeral 10 denotes a magnetic disk called a still video floppy disk, which is rotated at a predetermined number of revolutions by a motor (not shown) during playback. A signal is recorded on the magnetic disk 10, which is a mixture of an FM modulation signal of a luminance signal and an FM modulation signal of a line-sequential color difference signal with an offset. A recording signal on the magnetic disk 10 is converted into an electric signal by a reproducing head 12, and the output of the reproducing head 12 is amplified by a reproducing amplifier 14. The output of the reproduction amplifier 14 is passed through a high pass filter (HPF) 1.
6 and a bandpass filter 18, the signal is separated into an FM modulated luminance signal component and an FM modulated line sequential color difference signal component,
FM demodulation is performed by FM demodulation circuits 20 and 22, respectively.

The output of the FM demodulation circuit 20 is a luminance signal with a composite synchronization signal, which is clamped at the sync chip by a clamp circuit 24, digitized by an A/D converter 26, and sent to a digital signal processing circuit (DSP). 28
is input. Further, the output of the FM demodulation circuit 22 is a line-sequential color difference signal with an offset, and the pedestal level (and amplitude at 100% modulation) is different between the color difference components RY and B-Y. Considering this, the clamp circuit 30
clamps the output of the FM demodulation circuit 22 every 2H at the pedestal portion. The output of the clamp circuit 30 is digitized by an A/D converter 32 and input to a digital signal processing circuit (DSP) 28.

The dropout detection circuit 34 includes a detection circuit and a comparison circuit that compares the output of the detection circuit with a fixed level, and detects the presence or absence of dropout from the output of the HPF 16. If the detection level of the output of the HPF 16 is below a predetermined value, it is determined that dropout has occurred and a dropout (DO) detection signal is output.

36 is a crystal oscillator, 38 is a magnetic disk 1
This is an input terminal for the PG signal indicating a rotational phase of 0, and the DSP
28 forms an operating reference clock based on the output of the crystal resonator 36, and performs digital signal processing to be described later in synchronization with the PG signal from the input terminal 38. The details will be explained later, but D.
The SP 28 performs dropout compensation, synchronization separation, and interlacing (i.e., interpolation of the second field signal) and skew compensation in the case of field reproduction on the luminance signal output from the A/D converter 26. /D converter 2
The line-sequential color difference signal with offset outputted from 6 includes:
Perform offset removal, skew compensation, and line synchronization. When using a two-channel frame head as the playback head 12, the DSP 28 outputs a head switching signal H.
The SW is output to the output terminal 40.

The DSP 28 receives a digital luminance signal with a composite synchronization signal and a line-synchronized digital color difference signal R.
-Y, B-Y, which are outputted by D/A converters 42, 4.
4 and 46, it is converted into an analog signal. Modulation circuit 4
8 modulates the analog color difference signals R-Y and B-Y and outputs a chroma signal. Mixing circuit 50 mixes the output of D/A converter 42 with the output of modulation circuit 48 to form a composite video signal, and outputs the composite video signal to output terminal 52.

FIG. 1 shows details of the internal circuitry of the DSP 28, and FIG. 1 will be described in detail. For the luminance signal input from the A/D converter 26, a dropout compensation circuit 60; in the case of field recording, an interlace circuit 62 that forms another field signal by interpolation from the reproduced field signal and outputs it as an interlace signal; It consists of a skew compensation circuit 64 that compensates for the skew of the field formed by interpolation, and a delay circuit 66 that compensates for the delay time difference between the HPF 16 and the BPF 18. Regarding the line sequential color difference signal with offset inputted from the A/D converter 32, it consists of an offset removal circuit 68, a color difference skew compensation circuit 70, and a line synchronization circuit 72.

The synchronization separation circuit 74 separates a synchronization signal from the luminance signal with a synchronization signal that has been dropout compensated by the dropout compensation circuit 60 and supplies it to a system signal generation circuit (SSG) 76 . Offset removal circuit 68
outputs to the SSG 76 a color discrimination signal indicating which horizontal line is the color difference signal R-Y or B-Y. SSG76 is
A reference clock is formed by the crystal oscillator 36, and a control clock at a predetermined timing is supplied to the circuits 60 to 72 according to the PG signal from the PG input terminal 38, the synchronization signal from the synchronization separation circuit 74, and the color discrimination signal from the offset removal circuit 68. and output switching signals. Since the SSG 76 that generates such timing signals or clocks can be easily configured using a combinational logic circuit, a detailed explanation of the internal circuit of the SSG 76 will be omitted.

The dropout compensation circuit 60 has a 1H (1H)
It consists of a delay circuit (specifically, a FIFO type memory) 60A corresponding to the horizontal scanning period (horizontal scanning period), and a switch 60B that is switched by a DO detection signal from the dropout detection circuit 34. The luminance signal with a synchronization signal output from the A/D converter 26 is input to the a contact of the switch 60B, and the output of the switch 60B is input to the delay circuit 60A.
The output of 0A is input to the b contact of the switch 60B. The switch 60B is normally connected to the a contact, and is connected to the b contact when dropout is detected. That is, when detecting dropout, the signal one horizontal line before is selected.

The interlacing circuit 62 includes a delay circuit 60
Adder 62A that adds the input and output of A, adder 62A
A divider 62B that halves the output of , and a delay circuit 60A.
(contact a) or the output of the divider 62B (contact b). Adder 62A and divider 62B form an average signal between two adjacent horizontal lines. Specifically, the divider 62B can be easily constructed by simply shifting parallel digital lines by 1 bit and connecting them. Under the switching control signal from the SSG 76, the switch 62C is connected to the a contact point to select the output of the delay circuit 60A when outputting the field reproduced image signal as it is, and on the other hand, outputs the second field image signal by interpolation. When output is to be performed, the output of the divider 62B is selected by connecting to the b contact except during the vertical retrace period.

The skew compensation circuit 64 compensates for the skew of the second field image signal formed by interpolation in the interlace circuit 62. The skew compensation circuit 64 is 0
．． It consists of a delay circuit 64A equivalent to 5H, and a switch 64B that selects a signal delayed by the delay circuit 64A or a signal bypassed by the delay circuit 64A. Switch 64B is SSG
When the reproduction field signal from the magnetic disk 10 is to be output as is under the switching control signal from the magnetic disk 76,
When outputting the signal of the pseudo field formed by the interlace circuit 62, it is connected to the a contact during the equalization pulse period, and is connected to the b contact at other times.

FIG. 3 shows a timing diagram of the luminance signal processing described above. For ease of understanding, they are shown as analog signals. FIG. 3(1) shows a PG pulse (or its waveform-shaped pulse) input from the PG input terminal 38. (2) is a field discrimination signal formed by a PG pulse, and is used to switch the head during frame playback and the interlacing switch 6 during field playback.
2C and skew compensation switch 64B are controlled. (3) is a composite synchronization signal separated by the synchronization separation circuit 74. (4) is a switching control signal for the skew compensation switch 64B, and (5) is a switching control signal for the interlacing switch 62C.

The output of the skew compensation circuit 64 is phase-adjusted by a delay circuit 66 consisting of a FIFO memory, and then
A converter 42 is supplied with the signal.

Next, a color difference signal processing system will be explained. Although the details will be described later, the offset removal circuit 68 removes the offset between the color difference component RY and the color difference component B-Y of the line sequential color difference signal. The offset removal circuit 68 also determines whether the line is a horizontal line of the color difference component R-Y or a horizontal line of the color difference component B-Y based on the difference in the pedestal levels, and outputs a color discrimination signal indicating the determination result to the SSG 76.

The line-sequential color difference signal from which the offset has been removed by the offset removal circuit 68 is supplied to a color difference skew compensation circuit 70 . The color difference skew compensation circuit 70 is
Similarly to the skew compensation circuit 64 for luminance signals, 0.5H
, and a switch 70B for selecting a signal delayed by the delay circuit 70A or a signal bypassing the delay circuit 70A. Switch 70B is switch 64B
Switching is controlled by the same switching control signal as . As a result, a signal delayed by 0.5H at the pseudo field timing during field reproduction is output.

The output of the color difference skew compensation circuit 70 is supplied to a line synchronization circuit 72 where it is line synchronized. The line synchronization circuit 72 includes a delay circuit 72A equivalent to 1H, a delay circuit 72
A first switch 72B that selects the R-Y component from the input or output of A, and a first switch 72B that selects the R-Y component from the input or output of delay circuit 72A;
-A second switch 72C that selects the Y component. When the input of the delay circuit 72A has a RY component, its output has a BY component, and when the input has a BY component, its output has a RY component. Therefore, in the SSG 76, the switch 72B always selects the R-Y component according to the color discrimination signal from the offset removal circuit 68, and the switch 72B always selects the R-Y component.
switch 72B so that C always selects the BY component;
Controls 72C. This synchronizes the line sequential signals. The output of switch 72B is supplied to D/A converter 44, and the output of switch 72C is supplied to D/A converter 46.

An example of the internal circuit configuration of the offset removal circuit 68 is shown in FIG. 80 is a gate circuit that is opened and closed by a gate control signal from the SSG 80, and the A/D converter 32
Pass the output of the pedestal. Gate circuit 80
The outputs of are cumulatively added by an accumulator consisting of an adder 82 and a register 84. That is, the output of the adder 82 is applied to the register 84, and the output of the register 84 is fed back to the adder 82. To the load control terminal of the register 84, a large number (for example, n clocks) of the color difference signal processing rate are applied from the SSG 76 within the pedestal period of each horizontal line. Thereby, the register 84 holds the level cumulative sum of n sample points of the pedestal level of each horizontal line.

The value held in register 84 is stored in registers 86 and 8.
8. Register 86 is load controlled by the line switch signal from SSG 76 and register 88
is load-controlled by a signal obtained by inverting the line switch signal by an inverter 90. The line switch signal is a signal that is inverted for each horizontal line. As a result, the register 86 is loaded with the n-time addition value of one of the pedestal levels of the even-numbered and odd-numbered horizontal lines, and the register 88 is loaded with the other n-time addition value. According to the rules, the pedestal level of the B-Y component is to be higher than the R-Y component, so by comparing the values held in registers 86 and 88,
It is possible to know whether the horizontal line of interest is the RY component or the BY component. Comparison circuit 92 compares the values held in registers 86 and 88, and sends the comparison result to SSG as a color discrimination signal.
76.

The color discrimination signal is a line switch signal.
During the “H” period, if the horizontal line of interest is the R-Y component, it is “H”, and if the horizontal line of interest is the B-Y component, it is “H”.
During the period when the line switch signal is “L”,
If the horizontal line of interest is the RY component, the signal is "L", and if the horizontal line of interest is the BY component, the signal is "H". Within a single field, this color discrimination signal does not change, but
It may change between fields of frame playback.

The divider 94 divides the value held in the register 84 by 1/
Do n. This provides an average value of the pedestal level that is less affected by noise. The subtracter 96 is the divider 9
Subtract the fixed value from the output of 4. This fixed value is a value near the median of the dynamic range of the color difference signal processing system. For example, in the case of 8 bits, set it to 128. The output of the subtracter 96 is, so to speak, a value that eliminates the offset of the offset line sequential color difference signal.
The offset can be removed by subtracting the output of the subtracter 96 from the output of the converter 32, that is, the line-sequential color difference signal with an offset. The output of the subtracter 98 is applied to the color difference skew compensation circuit 70.

FIG. 5 shows an operation timing diagram within the offset removal circuit 68 for the line sequential color difference signal with offset of the color bar. Figure 5 (1) shows the line sequential color difference signal with color bar offset, and Figure 5 (2) shows the gate circuit 8.
Gate control signal for 0, same (3) is clamp circuit 3
The clamp pulse for 0 (4) is the output of the subtracter 98 (line sequential color difference signal with offset removed). The clamp circuit 30 clamps the RY component near the center of the dynamic range. When clamping near the center of the dynamic range, it is better to clamp the RY component because of the difference in maximum amplitude between the RY component and the BY component. By referring to the output of the comparator circuit 92 to form a clamp pulse for the clamp circuit 30, the RY component can be clamped. Here, the line-sequential color difference signal with offset is simply clamped once every two horizontal lines, but it can also be configured so that it is clamped once every two horizontal lines with a specific color component. In this way, the dynamic range of the signal processing system can be effectively utilized.

In this embodiment, the clamp circuit 30
-The pedestal level of the Y component is clamped to the median value, but the offset removal circuit 68 allows the pedestal level of each horizontal line to be set accurately to the median value.
The clamp circuit 30 may clamp to approximately the median value. Of course, doing so requires some margin in the dynamic range of the A/D converter 32.

FIG. 6 shows a block diagram of a modified embodiment of the color difference signal processing system. 100 is an offset removal circuit, 1
02 is a line synchronization circuit that performs line synchronization on the line sequential color difference signal whose offset has been removed by the offset removal circuit 100;
Reference numeral 104 denotes a skew compensation circuit that outputs the color difference signal output from the line synchronization circuit 102 either as is or after being delayed by 0.5H.

In the offset removal circuit 100, the gate circuit 106, the adder 108, and the register 110 are respectively replaced by the gate circuit 80, the adder 82, and the register 84 in FIG.
It works the same way. That is, at the end of the pedestal period of each horizontal line, the register 110 holds the cumulative sum of n sample points of the pedestal period. The subtracter 112 subtracts a fixed value n times the median value of the dynamic range (for example, 128×n for 8 bits) from the output of the register 110. Divider 114 is subtracter 1
The output of 12 is made 1/n and applied to the subtracter 116. The output of divider 114 matches the output of subtractor 96 in FIG. A subtracter 116 subtracts the output of the divider 114 from the output of the A/D converter 32 (line sequential color difference signal with offset). Thereby, the pedestal level of each horizontal line can be adjusted to the center value of the dynamic range, and the offset of the line-sequential color difference signal with offset is removed.

Furthermore, the comparison circuit 118 compares the output of the register 110 with a fixed value n times the intermediate value of the two offset pedestal levels, and supplies the comparison result to the SSG 76 as a color discrimination signal. In this color discrimination signal, the line sequential color difference signal with offset is "L" for the horizontal line of the R-Y component, and "H" for the horizontal line of the B-Y component.
becomes.

The line synchronization circuit 102 has the same configuration as the line synchronization circuit 72 in FIG. 1, and has a 1H delay circuit 120.
and switches 122 and 124 for selecting the output of the delay circuit 120 or a signal bypassing the delay circuit 120. Switches 122 and 124 are controlled by the output (color discrimination signal) of comparison circuit 118, and switch 120
, 122 is connected to its a contact when the output of the comparator circuit 118 is "L", and is connected to its b contact when the output of the comparator circuit 118 is "H". As a result, the R-Y signal from the switch 120 and the B-Y signal from the switch 122 are output simultaneously.

The skew compensation circuit 104 includes delay circuits 126 and 1 that delay each of the R-Y signal and the B-Y signal output from the line synchronization circuit 102 by 0.5H.
28 and the outputs of delay circuits 126 and 128 or delay circuit 1
Switch 130 for selecting the signal bypassing 26, 128
, 132. Switches 130 and 132 are shown in FIG.
Switching is performed by a switching control signal having the same timing as shown in (4). Thereby, a pseudo frame signal can be generated from the field reproduction signal.

In the circuit configuration shown in FIG. 4, the noise margin is the offset amount itself of the offset line sequential color difference signal, whereas in the circuit configuration shown in FIG. (difference from the median value of the range), so it is susceptible to noise in the pedestal period of the color difference signal. However, there is an advantage that the internal circuit of the SSG 76 can be simplified.

Within the DSP 28, the delay circuit can be easily realized by a FIFO memory, and the delay circuit in the above embodiment is actually a FIFO memory.

In the above embodiment, the chroma signal is formed from the synchronized color difference signal by analog signal processing.
Needless to say, this can be realized by digital signal processing.

In the embodiments described above, dropout compensation;
Since circuits that use delay lines with a predetermined amount of delay can be configured with digital circuits, such as skew compensation and line synchronization of color difference line sequential signals, adjustment circuits such as compensation for temperature characteristics that are necessary when using analog delay lines can be used. This eliminates the need to provide a circuit, which simplifies the circuit as a whole and reduces adjustment work. It can also be integrated into an IC, making it easier to downsize the device.

[0040]

As can be easily understood from the above description, according to the present invention, offsets in line-sequential color difference signals with offsets can be accurately and completely removed.

[Brief explanation of the drawing]

FIG. 1 Digital processing circuit 2 according to an embodiment of the present invention
FIG. 8 is a detailed circuit configuration block diagram of No. 8.

FIG. 2 is an overall circuit configuration block diagram of an embodiment of the present invention.

FIG. 3 is a timing diagram of luminance signal processing.

FIG. 4 is a detailed circuit configuration block diagram of an offset removal circuit 68.

FIG. 5 is a processing timing diagram of a line-sequential color difference signal with an offset for a color bar.

FIG. 6 is a circuit configuration block diagram of a modified example of a digital processing system for color difference signals.

[Explanation of symbols]

10: Magnetic disk 12: Playback head 14: Playback amplifier 16: High-pass filter 18: Band-pass filter 20, 22: FM demodulation circuit 2
4: Clamp circuit 26: A/D converter 28: Digital signal processing circuit (DSP) 30: Clamp circuit
32: A/D converter 34: Dropout detection circuit 36: Crystal resonator 38: PG signal input terminal
40: Head switching signal output terminals 42, 44, 46:
D/A converter 48: Modulation circuit 50: Mixing circuit
52: Output terminal 60: Dropout compensation circuit
62: Interlace circuit 64: Skew compensation circuit 66: Delay circuit 68: Offset removal circuit
70: Color difference skew compensation circuit 72: Line synchronization circuit 74: Synchronization separation circuit 76: System signal generation circuit 60A: Delay circuit 60B: Switch 6
2A: Adder 62B: Divider 62C: Switch 64A: Delay circuit 64B: Switch 70A
:Delay circuit 70B: Switch 7 72A: Delay circuit 72B, 72C: Switch 80: Gate circuit
82: Adder 84, 86, 88: Register 90
: Inverter 92: Comparison circuit 94: Divider
96, 98: Subtractor 100: Offset removal circuit
102: Line synchronization circuit 104: Skew compensation circuit 106: Gate circuit 108: Adder 110: Register 112: Subtractor 114: Divider 116:
Subtractor 118: Comparison circuit 120: Delay circuit
122, 124: Switch 126, 128: Delay circuit 130, 132: Switch

Claims (2)

[Claims] 1. An analog clamp circuit that clamps an analog offset line-sequential color difference signal at its pedestal level at predetermined intervals, and a first A/D converter that digitizes the output of the analog clamp circuit. and an offset removal circuit that adjusts the pedestal level of each horizontal line to a predetermined value based on the cumulative value of a plurality of sample values of the pedestal level for the predetermined period obtained from the output of the first A/D converter. An image signal processing circuit characterized by: 2. Further, a second A/D converter that digitizes the analog luminance signal with a synchronization signal, a dropout detection circuit that detects a dropout of the analog luminance signal, and a dropout detection circuit that detects a dropout of the analog luminance signal. A dropout compensation circuit that compensates for dropout in the output of the second A/D converter based on the out detection signal, and a synchronization separation that separates the synchronization signal from the digital luminance signal dropout compensated by the dropout compensation circuit. Claim 1 characterized in that it has a circuit.
The image signal processing circuit described in .