JP3231463B2 - Image signal playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for reproducing an image signal in a still video camera or the like.

[0002]

2. Description of the Related Art In a still video device such as a still video camera, an electric signal of a subject image photoelectrically converted by an image pickup device or the like is converted from a luminance signal Y and color difference signals (RY, BY). An image signal is recorded on a magnetic disk and reproduced from the magnetic disk. Here, at the time of recording, a horizontal synchronizing signal and a vertical synchronizing signal are added, and further, an I.D.
The D signal is superimposed and recorded.

On the other hand, during reproduction from a magnetic disk, a signal for each pixel is extracted using a sampling clock generated based on a horizontal synchronization signal and a vertical synchronization signal. Here, in the reproducing apparatus provided with the memory means, the start timing of A / D conversion of the image signal or writing to the memory means is determined by the elapsed time from the horizontal synchronization signal. For example, the sampling start signal is directly counted from the output of the horizontal synchronizing signal, and the storage start timing is set. However, since the cycle of the sampling clock fs is relatively short, the count start timing from the horizontal synchronizing signal may be shifted by about one clock. This shift has resulted in noise or fluctuation of the image, resulting in a deterioration in the quality of the reproduced image.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a recording and reproducing apparatus for an image signal capable of obtaining a high-quality image free from fluctuations and noises. With the goal.

[0005]

SUMMARY OF THE INVENTION The present invention, which achieves the above objects, comprises a reference signal
From the recording medium on which the
And the reference signal is reproduced, and the reproduced reference signal is
Higher sampling clock and write clock
Clock and sample with the sampling clock.
To write to memory means by the above write clock
An apparatus comprising: counting means for counting the output of the reference signal from the time of detecting the predetermined synchronization signal of the image signal reproduced from the recording medium, when the count value of said counting means has reached a predetermined value A memory control means for starting the writing of the image signal into the memory means is provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. FIG. 1 is a block diagram showing a configuration of an embodiment of a still video apparatus to which the present invention is applied. For the sake of simplicity, an embodiment will be described in which the present invention is applied to a still video apparatus for recording and reproducing only a luminance signal (black and white). These circuits are connected to the system controller 24.
Is generally controlled by the Recording and playback operations are
This is performed by the system controller 24 that has received the operation of the operation switch 22.
It is displayed on the display 25.

A digitized luminance signal for each pixel, which is input from an image output device (not shown) such as an image sensor,
The memory controller 31 sequentially stores the recording memory 3
Written in 3. When a luminance signal for one screen is written into the recording memory 33 for recording, the luminance signal is sequentially read from the recording memory 33 by the memory controller 31 and the D / A converter 3
The signal is converted into an analog signal at 5, and the high-frequency component is removed by the low-pass filter 37, and is output as a black and white video signal. Here, the memory controller 31 and the D / A converter 35 perform a write / read process and a D / A conversion process in synchronization with the sampling clock fs' output from the sampling clock generation circuit.

The black-and-white video signal input to the FM modulation circuit 39 is FM-modulated here, and is synthesized by a synthesizing circuit (multiplexing means) 4.
4 is input. In the synthesizing circuit 44, a pilot signal generating circuit (reference signal generating means) 47 is added to the black and white video signal.
Are superimposed on a pilot signal (reference signal) of a predetermined frequency which is output by. Pilot signal generation circuit 47 generates a pilot signal based on sampling clock fs' output from sampling clock generation circuit 41. The pilot signal of this embodiment is fsc × 4/10 ≒ 1.43 MHz.
z (fsc is the frequency of the subcarrier of the image signal,
3.58MHz), but any frequency can be selected.

The multiplexed FM modulated signal on which the pilot signal fp is superimposed by the synthesizing circuit 44 is amplified to a predetermined level by a recording amplifier 46, and the REC of a video changeover switch 48
The signal is output to the recording / reproducing head 50 via the terminal. A signal for one screen (in the case of field recording) is recorded on one predetermined track of the magnetic disk 54 by the recording / reproducing head 50. The magnetic disk 5
4 is rotated at a predetermined rotation speed by a spindle motor 58 during recording and reproduction.

A video switch 48 is a switch for selectively connecting the recording / reproducing head 50 to the recording amplifier 46 during recording and to the reproducing amplifier 56 during reproduction via the REC terminal and the PB terminal. ,
The recording / reproducing head 50 is connected to a reproducing amplifier 56 via a PB terminal.
Connect to The multiplexed FM modulation signal read out from the magnetic disk 54 via the recording / reproducing head 50 during reproduction is amplified by the reproducing amplifier 56 and output to the FM demodulation circuit 84 and the pilot signal reproducing circuit (reference signal reproducing means) 68. .

The signal input to the FM demodulation circuit 84 is demodulated and output to the A / D converter 92 and the synchronization signal separation / pulse generation circuit 103. Of the demodulated signals, the image signals are sequentially converted into digital signals by an A / D converter 92 and stored in a reproduction memory 93. When the memory of the signal for one track is completed, the signal is sequentially read from the reproduction memory 93, and is converted into an analog signal by the D / A converter 88.
The high-frequency component is removed by the low-pass filter 96 and output as a black and white video signal. Further, among the signals demodulated by the FM demodulation circuit 84, the synchronization signal is separated by the synchronization signal separation / pulse generation circuit 103, a corresponding synchronization pulse is generated, and output to the memory write start control circuit 101.

On the other hand, a pilot signal reproducing circuit 68 converts a signal inputted from the reproducing amplifier 56 into a pilot signal f
Only p is extracted and output to the PLL circuit 70 and the memory write start control circuit 101. The PLL circuit 70 outputs a pulse signal of a predetermined frequency synchronized with the phase of the pilot signal fp to the write clock generation circuit 80 based on the input pilot signal fp. The PLL circuit 7
Reference numeral 0 denotes a known circuit including a phase comparator 72, a low-pass filter 74, a voltage controlled oscillator (VCO) 76, and a frequency divider 78.

A write clock generation circuit 80 generates a sampling clock S1 and a write clock fsn based on a pulse signal input from the PLL circuit 70,
It outputs to the D converter 92 and the write address counter 82. That is, the A / D converter 92 operates with a sampling clock, and the write address counter 82 operates with a write clock fsn.

The A / D converter 92 receives a black-and-white video signal demodulated by the FM demodulation circuit 84. The black-and-white video signal is sampled in synchronization with the sampling clock S1 and converted into a digital signal. You. The digitized black and white video signal is sequentially written into the address of the reproduction memory 93 specified by the write address counter 82 in synchronization with the write clock fsn.

The reading from the reproduction memory 93 and the D / A conversion operation of the D / A converter 88 are performed by a reference clock generation circuit 90.
And is executed in synchronization with the read clock S4 generated by the read clock generation circuit 94 based on the clock output from.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG.
FIG. 2 shows, from the top, the reproduced image signal output from the FM demodulation circuit 84, the horizontal synchronization signal Hsync synchronously separated by the synchronization signal separation / pulse generation circuit 103, and the pilot signal fp reproduced by the pilot signal reproduction circuit 68. , And the write clock f output from the write clock generation circuit 80
Indicates sn.

Here, conventionally, in synchronization with the rise of the horizontal synchronization signal Hsync separated by the synchronization signal separation / pulse generation circuit 103, the rise of the write clock fsn reproduced after this rise is counted and a predetermined number is counted. Writing was started at C1 at the later rise.

The horizontal synchronizing signal Hsync output from the synchronizing signal separation / pulse generating circuit 103 may be shifted in time from the horizontal synchronizing signal of the reproduced image signal. Even if this deviation is slight, the frequency of the write clock signal is relatively high (about 14.3 MHz), so that the reference pulse for starting the count of the write clock may be shifted. For example, if the separated horizontal synchronization pulse is shifted to the position indicated by the dashed line, the write clock for starting counting is shifted from a to b, so that C1 also shifts from C1 to C2 at the start of writing. This shift becomes jitter or noise.

In this embodiment, the pilot signal fp, which has a lower frequency than the write clock and is recorded together with the horizontal synchronizing signal Hsync and the image signal and reproduced at the same time as the reproduction of the image signal by the FM demodulation circuit 84, is used. Utilization is used to start writing. That is, the memory write start control circuit 101 outputs the separated horizontal synchronization signal Hsync.
The rising edge of the reproduced pilot signal fp output from the first reproduced pilot signal fp after the detection of the rising edge is counted, and after counting the predetermined number, the write output first output after the predetermined number of rising edges. Writing is started by detecting the rising edge C1 of the clock fsn.

FIG. 3 shows a more specific circuit of the memory write control circuit 101. The memory write control circuit 101 counts the pilot signal fp on condition that the enable signal En is output from the D flip-flop 105 and its output terminal Q. When the count value reaches a predetermined value, the write address counter 82 A reference time counter 107 for outputting an enable signal Wen for permitting the counting operation.

A predetermined voltage Vcc is input to an input terminal D of the D flip-flop 105 from a constant voltage circuit (not shown).
The clock input C has a synchronization signal separation / pulse generation circuit 1
03, a pulse signal corresponding to the horizontal synchronization signal Hsync is input. Further, an enable signal Wen output from the reference time counter 107 is input to the reset terminal R of the D flip-flop 105.

When the horizontal synchronizing signal Hsync is input to the synchronizing signal separation / pulse generating circuit 103, a corresponding pulse signal is output from this circuit 103 to the clear terminal C of the D flip-flop 105. Then, the level of the output terminal Q changes to “H” level, and the reference time counter 107 is enabled to count, and the input pilot signal f
Start counting p.

When the count value of the reference time counter 107 reaches a predetermined value, the enable signal Wen of the reference time counter 107 changes to "H" level, whereby the count operation of the write address counter 82 is permitted and the count operation is started. Be started.

On the other hand, the enable signal Wen is transmitted from the reset terminal R of the D flip-flop 105 to the reference time counter 1.
07 are also input to the reset terminals R, respectively, the enable signal En changes to "L" level, the count value is reset, and the enable signal Wen changes to "L" level. Thereafter, the synchronization signal separation / pulse generation circuit 103
The above operation is repeated each time the .phi. Detects the horizontal synchronization signal Hsync and outputs a corresponding pulse.

Here, the horizontal synchronizing signal Hsy at the time of recording is
The difference between the output timings of nc and pilot signal fp does not change during reproduction. Therefore, counting the pilot signal fp is equivalent to counting the timing of the true horizontal synchronization signal Hsync having no time lag.

The counting operation of the reference time counter 107 is started by a horizontal synchronizing signal Hsync having a time lag outputted from the synchronizing signal separating / pulse generating circuit 103. The frequency of the pilot signal fp is higher than that of the write clock fsn. Since the time difference is low, this time lag is canceled by the counting operation of the pilot signal fp, so that the enable signal Wen output from the reference time counter 107 is output after a predetermined time from the true horizontal synchronization signal Hsync. Become. That is, the count start timing of the write address counter 82 is prevented from shifting.

By detecting and counting the reproduced pilot signal fp in this manner, a high-quality reproduced image signal free from jitter and free from fluctuations of the separated horizontal synchronizing signal Hsync can be obtained.

Although the present invention has been described with reference to the embodiment applied to a monochrome image recording / reproducing apparatus, it goes without saying that the present invention can be applied to a color image recording / reproducing apparatus including color signals.

[0029]

As described above, according to the present invention, a reference signal which is recorded together with an image signal and has no time lag is detected in synchronization with a horizontal synchronizing signal, and the timing of writing to the memory means is determined based on this detection. Therefore, it is possible to reproduce an image signal having no deviation from the horizontal synchronization signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a circuit configuration of an embodiment of a still video device to which the present invention is applied.

FIG. 2 is a reproduction timing chart of the embodiment.

FIG. 3 is a more specific circuit diagram of a memory write start control circuit of the embodiment.

[Explanation of symbols]

31 memory controller 33 recording memory (memory means) 35 D / A converter 41 sampling clock generation circuit (reference signal generation means) 44 synthesis circuit (superimposition means) 45 FM modulation circuit 47 pilot signal fp generation circuit (reference signal generation means) 54) Magnetic disk 68 Pilot signal reproducing circuit (reference signal reproducing means) 92 A / D converter 93 Memory for reproduction (memory means) 101 Memory write start control circuit (counting means, memory control means) 103 Synchronous signal separation / pulse generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 9/79-9/898

Claims (1)

(57) [Claims] 1. A recording system in which a reference signal is multiplex-recorded with an image signal.
The image signal and the reference signal are reproduced from the recording medium, and the reproduced
Sampling clock of higher frequency than the reference signal from the reference signal
Generate lock and write clocks and sample
Sampling with the clock and using the above write clock
A reproducing device for writing to a memory device , wherein the counting device counts an output of the reference signal from a time when a predetermined synchronization signal of an image signal reproduced from the recording medium is detected; An image signal reproducing apparatus comprising a memory control means for starting writing of the image signal into the memory means when the value becomes a value.