JPH0541852A - Time axis fluctuation elimination device and magnetic recording and reproducing device using same - Google Patents

Abstract

PURPOSE:To realize a device eliminating time axis fluctuation generated in a signal read from a magnetic tape due to uneven drive of the magnetic tape or an uneven revolution of a drum or the like in a tape head system with simpler circuit configuration than that of a conventional system at the read of a video signal from the magnetic tape. CONSTITUTION:A time axis fluctuation elimination circuit 150 to eliminate a time axis error included in a signal read from a magnetic tape 23 in a camcorder delays a reproduced chroma signal and a reproduced luminance signal reproduced from a signal read from the magnetic tape 23 in a camcorder by a time in response to a phase difference between a horizontal synchronizing signal included in the reproduced luminance signal and a stable horizontal synchronizing signal generated from a synchronizing signal generator 201 in a video camera section 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis fluctuation eliminating device and a magnetic recording / reproducing apparatus using the same, and more particularly to a time axis fluctuation used in a helical scan type magnetic recording / reproducing apparatus for recording and reproducing a video signal. Regarding the removal device.

[0002]

2. Description of the Related Art A magnetic recording / reproducing apparatus for recording and reproducing a video signal, such as a VTR (video tape recorder) or a camera-integrated VTR, uses mechanical movement of a recording medium for recording and reproducing the signal. Therefore, the reproduced video signal fluctuates with time, that is, the time axis fluctuates.
Such a time-axis fluctuation is caused by a tape head system in an apparatus using a magnetic tape as a recording medium, for example.

That is, in the VTR, since the running speed of the magnetic tape and the rotating speed of the rotary drum to which the head is attached are not strictly maintained constant and slightly change, the waveform of the video signal read by the head from the magnetic tape is changed. , That is, the fluctuation occurs in the time axis direction with respect to the original waveform.

A reproduced image obtained from a video signal containing such a variation (jitter component) in the time axis direction has a horizontal fluctuation called jitter. For this reason,
The video signal including the fluctuation in the time axis provides an unsightly screen.

Therefore, the VTR and the camera-integrated VTR are
A time fluctuation removing device (time base collector) for correcting fluctuations in the time axis direction (hereinafter, also referred to as time axis error) of video signals read from magnetic tape (hereinafter, referred to as reproduction video signals). Have.

FIG. 12 is a schematic block diagram showing the basic structure of a time axis fluctuation eliminating device. Referring to FIG. 12, the time axis fluctuation eliminating device basically writes the reproduced video signal once in the memory at a timing according to a clock signal having the same time axis error as the time axis error included in the reproduced video signal. After that, the time axis error of the reproduced video signal is corrected by reading from the memory at the timing according to the stable clock signal which does not include the time axis error.

The basic configuration of the time axis fluctuation eliminating apparatus will be described below with reference to FIG.

The A / D converter 310 converts the reproduced video signal into
In response to the clock signal generated from the write clock generation circuit 340, sampling is performed and converted into digital data.

The digital data converted by the A / D converter 310 is written in the memory 320 in response to the clock signal output from the write clock generating circuit 340, and then read from the memory 320.
It is read in response to the clock signal output from 50.

The D / A converter 330 converts the digital data read from the memory 320 into an original analog signal in response to the clock signal output from the read clock generation circuit 350, and outputs the analog signal.

The write clock generation circuit 340 separates the synchronizing signal from the reproduced video signal and, based on the separated synchronizing signal, has the same time axis error as the time axis error contained in the reproduced video signal, and thus, the fluctuation of the time axis. Generates a clock signal.

In the A / D converter 310, the reproduced video signal is sampled in response to the rising (or falling) of the clock signal having the time axis fluctuation, and the sampled reproduced video signal voltage is converted into digital data. To be converted. These digital data are stored in the memory 310.
At, the address is written in each address in response to the rising (or falling) of the clock signal having the above-mentioned time axis fluctuation. Therefore, at each address of the memory 320, the video signal voltage obtained from a plurality of pixels located at equal intervals in the horizontal direction on the screen is written.

FIG. 13 is a waveform diagram showing how the reproduced video signal is sampled by the A / D converter 310.
FIG. 14 is a diagram showing a pixel array on the screen. Next, FIG.
3 and FIG. 14, the principle of writing the reproduced video signal voltage of pixels at spatially equidistant positions on the screen in the memory 320 will be briefly described.

As shown in FIG. 13A, the video signal includes the original video signal portion obtained from each horizontal scanning line on the screen 500 and the beginning of the video signal portion of each horizontal scanning line, that is, the horizontal direction. And a color burst signal inserted in the blanking period. The color burst signal is an NTSC (Natio)
nal Television System Com
a color subcarrier having a reference phase necessary for demodulating a color signal from a composite video signal of the
It carries the most accurate time information in the signals included in the TSC video signal.

The screen 500 is composed of pixel rows 600 corresponding to horizontal scanning lines, and each pixel row 600 is considered to be composed of n minute pixels P1 to Pn of the same size.

If there is no time axis error in the video signal of each horizontal scanning line, the luminance information and color information of the n pixels P1 to Pn are the video at the position of x in FIG. 13 in the video signal of the corresponding horizontal scanning line. It is represented by a signal voltage. Therefore, in order to write the video signal of each horizontal scanning line into the memory 320 as the color information and the luminance information of the n pixels P1 to Pn, the video signal of each horizontal scanning line is as shown in FIG. In addition, if the time period corresponding to the width of each pixel is set as one cycle and sampling is performed in synchronization with the rising edge of the clock signal having a phase such that all rising timings coincide with the positions of x in FIG. Good.

However, there is a time axis error in the video signal of each horizontal scanning line, and for example, in the video signal of the horizontal scanning line (FIG. 13 (a)) corresponding to the video signal voltage of the pixels P2 and P3, it is slightly after x. When the video signal of each horizontal scanning line is sampled in response to the clock signal shown in FIG. 13B, the video signal is sampled as the video signal voltage of the pixel P1. The time interval a between the upper position and the position on the video signal sampled as the video signal voltage of the pixel P2, the pixel P
The time interval b between the position on the video signal sampled as the video signal voltage of 2 and the position on the video signal sampled as the video signal voltage of the pixel P3, the pixel P3
The time interval c between the position on the video signal sampled as the video signal voltage of the pixel P4 and the position on the video signal sampled as the video signal voltage of the pixel P4 is the screen 5
00 does not match the spatial distance between two adjacent pixels. Therefore, in the memory 200, the video signal voltage of n pixels which are not spatially equidistant on the screen 500 is 1
It is stored as a video signal of a horizontal scanning line.

Therefore, in this case, the video signal of each horizontal scanning line is the clock signal as shown in FIG. 13 (c), that is, the clock signal shown in FIG. 13 (b) is the pixels P2 and P3. Sampling is performed in response to the rising edge of the signal whose phase is delayed only in the period corresponding to the portion including the position on the video signal sampled as the video signal voltage. The magnitude of this phase delay depends on two positions on the video signal sampled as the video signal voltage of the pixels P2 and P3, and the video signal voltage of the pixels P2 and P3 when the video signal has no time axis error. Is set so as to match the magnitude d of the deviation between the two positions to be sampled. Therefore,
Digital data stored in the memory 320 as a video signal of each horizontal scanning line becomes a video signal voltage of n pixels at spatially equidistant positions on the screen 500.

Referring again to FIG. 12, write clock generating circuit 340 outputs a clock signal having a predetermined reference phase (for example, FIG. 13B) during a period in which the reproduced video signal does not fluctuate on the time axis. During a period in which the reproduced video signal is output and has a time-axis fluctuation, a clock signal (for example, FIG. 13C) having a phase difference according to the magnitude and direction of the time-axis fluctuation with respect to the reference phase is output. Output. As a result, the video signals of a plurality of pixels at spatially equidistant positions on the screen 500 are constantly written in the memory 320.

The read clock generating circuit 350 generates a stable clock signal free from fluctuations in the time axis based on an external synchronizing signal independent of the reproduced video signal and supplies it to the memory 320 and the D / A converter 330. Therefore, memory 3
The video signals of a plurality of pixels at spatially equidistant positions once written in the memory 20 are stored in the memory 320 at regular time intervals.
After being read from, it is converted into a smooth analog signal by the D / A converter 330. As a result, from the D / A converter 330, the video signal voltages of the plurality of pixels are smoothly connected at time intervals corresponding to the spatial positional relationship of these pixels on the screen 500,
That is, the video signal whose time axis is corrected is output.

FIG. 15 is a block diagram showing a concrete structure of a conventional time axis fluctuation eliminating apparatus. Hereinafter, the configuration and operation of the conventional time axis fluctuation removing device will be described with reference to FIG. The reproduced video signal includes both the luminance signal and the chroma signal.

The A / D converter 710 converts the luminance signal (reproduction luminance signal) included in the reproduced video signal into a rising edge (or a falling edge) of the output signal of the write timing generator 810.
In response to, and the sampled voltage is converted into digital data. This digital data is DRA
It is provided to M (random access memory) 730.

Similarly, the A / D converter 720 samples the chroma signal (reproduced chroma signal) included in the reproduced video signal in response to the rising (or falling) of the output signal of the write timing generator 810. , Convert the sampled voltage to digital data. This digital data is given to the DRAM 740.

The DRAM 730 sequentially fetches the output data of the A / D converter 710 in response to the rising (or falling) of the output signal of the write timing generator 810, stores it in each address, and then stores it in the read timing generator 80.
In response to the rising (or falling) of the output signal of 0, the stored data is sequentially read from each address and D /
It is given to the A converter 750.

Similarly, the DRAM 740 transfers the data from the A / D converter 720 to the write timing generator 810.
In response to the rising edge (or falling edge) of the output signal, the data is sequentially captured and stored at each address, and then the stored data is sequentially loaded from each address in response to the rising edge (or falling edge) of the output signal of the read timing generator 800. It is read and given to the D / A converter 760.

The D / A converter 750 converts the data from the DRAM 730 into the original analog voltage in response to the fall (fall) of the output signal of the read timing generator 800, and supplies it to the buffer circuit 770.

Similarly, the D / A converter 760 is
The data from the AM740 is converted into the read timing generator 8
In response to the rise (or fall) of the output signal of 00, it is converted into the original analog voltage and given to the buffer circuit 780.

On the other hand, the sync separation circuit 820 separates the vertical sync signal and the horizontal sync signal contained therein from the reproduced luminance signal. The separated vertical sync signal and horizontal sync signal are input to a monostable multivibrator (MMV) 830.

The monostable multivibrator 830 operates so as to hold its output voltage at a high level for a certain period in synchronization with the rise (or fall) of the applied sync signal. As a result, the MMV 830 removes the phase fluctuation of the sync signal included in the reproduction luminance signal, and outputs a signal having a constant frequency and a stable phase.

The phase comparison circuit 840 compares the phase of the input signal to the MMV830 with the phase of the output signal of the MMV830, and supplies the voltage controlled oscillator 850 with a voltage proportional to the phase difference between these signals. ..

When the reproduced video signal includes a time base error, the intervals between the vertical synchronizing signals and the intervals between the horizontal synchronizing signals in the reproduced luminance signal are different from the original lengths. Therefore, the phase of the horizontal synchronization signal in the reproduction luminance signal changes according to the time axis error included in the reproduction video signal.

Therefore, the output voltage of the phase comparison circuit 840 changes following the phase change of the horizontal synchronizing signal included in the reproduction luminance signal. The voltage control oscillator 850 gives the write timing generator 810 a signal having a frequency proportional to the magnitude of the output voltage of the phase comparison circuit 840. Therefore, the write timing generator 810 causes the voltage controlled oscillator 8 to
The frequency of the signal received from 50 changes following the phase change of the horizontal synchronizing signal included in the reproduction luminance signal.

The write timing generator 810 changes the phase of the clock signal of a constant frequency by following the change of the output frequency of the voltage controlled oscillator 850, and the A / D converters 710 and 720 and the DRAMs 730 and 7 thereof.
Give to 40. Therefore, the sampling point of the reproduced luminance signal in the A / D converter 710 and the sampling point of the reproduced chroma signal in the A / D converter 720 are both images of a plurality of pixels at equal intervals on the screen. A component that represents information appears. Furthermore, D
The data write timing to each address in the RAMs 730 and 740 is synchronized with the sampling timing in the A / D converters 710 and 720, respectively.

Therefore, in the DRAMs 730 and 740, the reproduction luminance signal voltage and the reproduction chroma signal voltage of a plurality of pixels located at equidistant positions on the screen are respectively reproduced by the reproduction luminance signal and the reproduction chroma signal of each horizontal scanning line. Is once stored as.

The read timing generator 800 has the same frequency as the frequency of the output signal of the write timing generator 810 on the basis of a predetermined reference signal given from the outside, and has a stable phase change without time axis fluctuation. Is generated and applied to the DRAMs 730 and 740 and the D / A converters 750 and 760.

Therefore, D / A converters 750 and 76
From 0, each is once stored in the DRAM 730,
The reproduced luminance signal voltages of a plurality of pixels located at regular intervals on the screen are connected to each other and smoothed, and the analog signals once stored in the DRAM 740 and located at equidistant positions on the screen. The reproduced chroma signal voltage is connected and a smoothed analog signal is output.

Buffer circuits 770 and 780 buffer the output signals of D / A converters 750 and 760, respectively, and apply the buffered signals to Y / C mix circuit 790.

The Y / C mix circuit 790 synthesizes the analog signals supplied from the buffer circuits 770 and 780 and outputs it as a time-axis corrected reproduced video signal.

[0039]

As described above, the conventional time axis fluctuation eliminating apparatus determines the video signal voltages of a plurality of pixels arranged at equal intervals in the horizontal direction on the screen from the reproduced video signal. Since it is necessary to extract the reproduced video signal of the horizontal scanning line, an A / D converter for converting the reproduced video signal into a digital signal, a memory for temporarily storing the video signal converted into the digital signal, a memory A control circuit for changing the data writing timing and the data reading timing according to the time base error contained in the reproduced video signal, a D / A converter for reconverting the digital signal read from the memory into an analog signal, etc. However, it requires a circuit with a complicated configuration that is expensive in price and requires a large amount of power consumption.

Therefore, an object of the present invention is to solve the above problems and to reduce the time base error included in the reproduced video signal easily at a relatively low cost, by removing the time base fluctuation eliminating device. Is to provide.

[0041]

In order to achieve the above-mentioned object, a time axis fluctuation eliminating apparatus according to the present invention comprises a delay time variable delay means for delaying a reproduced video signal including a synchronization signal, and a delay means. Means for extracting a sync signal from the reproduced video signal delayed by the means, displacement means for varying the displacement amount for receiving a predetermined reference sync signal and displacing the phase of the reference sync signal, and synchronization extracted by the extracting means The change in the phase difference between the signal and the reference synchronization signal whose phase is displaced by the displacement means is detected, the delay time in the delay means is changed according to the detected change in the phase difference, and the displacement amount of the displacement means And means for adjusting so that the phase difference after change is maintained.

According to another aspect, the time axis fluctuation removing apparatus according to the present invention has a rotary drum having a magnetic head for reading a video signal from a magnetic tape on which a video signal including a sync signal is recorded, and a predetermined reference synchronization. Synchronization signal generating means for generating a signal, means for detecting the rotation phase of the rotating drum, and means for controlling the rotation phase of the rotating drum based on the detection output of the detecting means and the reference synchronization signal generated by the generating means. It is applied to a magnetic recording / reproducing apparatus having and. In this magnetic recording / reproducing apparatus, the time axis fluctuation removing apparatus displaces the phase of the reference synchronization signal generated by the synchronization signal generating means in order to remove the time axis error included in the video signal read by the magnetic head. A displacement amount variable displacement means, a delay time variable delay means for delaying the read video signal, an extraction means for extracting a synchronization signal included in the video signal delayed by the delay means, and a phase shifter for changing the phase. A change in the phase difference between the displaced reference synchronization signal and the synchronization signal extracted by the extraction means is detected, and the change amount of the displacement means is changed in accordance with the change in the detected phase difference. Means for adjusting so that the subsequent phase difference is maintained.

According to another aspect, the time axis fluctuation eliminating device according to the present invention is applied to a magnetic recording / reproducing device having an imaging function. This magnetic recording / reproducing apparatus reads a video signal from a magnetic tape on which a video signal including a sync signal is recorded at the time of reproduction, and records a video signal including the sync signal on a magnetic tape at the time of recording, and a magnetic head. A rotary drum to which a magnetic head is attached, a reference sync signal generating means for generating a predetermined reference sync signal, a means for detecting the rotational phase of the rotary drum, a means for imaging a subject during recording, and an imaging output of the imaging means. A video signal creating means for creating a video signal based on the reference sync signal generated by the sync signal generating means and a control means for controlling the rotation phase of the rotary drum are provided. The control means controls the rotational phase of the rotary drum based on the reference sync signal generated by the sync signal generation means and the detection output of the detection means during reproduction, and is created by the video signal creation means during recording. The rotation phase of the rotary drum is controlled based on the synchronization signal included in the video signal and the detection output of the detection means. The video signal creating means includes a delay means with a variable delay time, which delays the image pickup output of the image pickup means. In such a magnetic recording / reproducing apparatus, the time axis fluctuation eliminating apparatus according to the present invention comprises means for supplying the read video signal to the delay means during reproduction,
Displacement means for displacing the phase of the reference synchronization signal generated by the synchronization signal generation means, variable displacement amount means, means for extracting the synchronization signal from the delayed output of the delay means at the time of reproduction, and extraction means at the time of reproduction The change in the phase difference between the sync signal and the reference sync signal whose phase is displaced by the displacement means, and the delay time in the delay means is changed according to the detected change in the phase difference, and the displacement And a means for adjusting the displacement amount in the means so that the phase difference after the change is maintained.

[0044]

Since the time axis fluctuation eliminating apparatus according to the present invention is configured as described above, the reproduced video signal always has a deviation of the phase of the sync signal contained in the reproduced video signal from the phase of the reference sync signal. It is delayed for a length of time accordingly. The phase of the synchronization signal included in the reproduced video signal changes according to the time base fluctuation generated in the reproduced video signal. Therefore, in the reproduced video signal output from the delay means, the position where the component representing the video information of each pixel on the screen appears changes according to the time axis error contained in the reproduced video signal before being delayed.

[0045]

FIG. 1 is a camera-integrated VT according to an embodiment of the present invention.
It is a schematic block diagram which shows the partial structure of R. In Figure 1,
The portion related to the time axis correction of the reproduced video signal is mainly shown. In this camera-integrated VTR, the time base correction of the reproduced video signal is performed in the VTR unit 100.

FIG. 11 is a waveform diagram for explaining the relationship between the time variation generated in the reproduced video signal and the phase of the horizontal synchronizing signal included in the reproduced video signal. Below, FIG.
The principle of removing the time base fluctuation of the time fluctuation removing device according to the present invention will be described with reference to FIG.

At the time of reproducing a video signal from the magnetic tape, unevenness that cannot be completely controlled by the drum servo 1 and the tape running system 29, such as the running speed of the magnetic tape and the rotating speed / rotating phase of the drum on which the magnetic head is mounted. Yes, in the reproduced video signal (FIG. 11B), a video signal of one horizontal scanning line appears in a period longer than the original one horizontal scanning period, and the video of the kth and subsequent pixels forming this horizontal scanning line. It is assumed that the component Pk representing information appears at a time later than the original time.

In such a case, the phase of the horizontal synchronizing signal (Fig. 11 (d)) in the reproduced video signal is the horizontal synchronizing signal (Fig. 11 (a)) in the original reproduced video signal (Fig. 11 (a)) without fluctuation in the time axis. 11 (c)) is delayed from the phase in FIG. 11 (c) by T, which corresponds to the magnitude of the difference between the position where the video signal voltage of the kth pixel and the subsequent pixels should originally appear and the position where it actually appears.

Therefore, the phase of the horizontal synchronizing signal in the reproduced video signal is constantly compared with the phase of the accurate horizontal synchronizing signal which can be regarded as the horizontal synchronizing signal appearing in the reproduced video signal having no time axis fluctuation, and between these signals. If the reproduced video signal is delayed as shown in FIG. 11 (e) so that the phase difference becomes 0, the video signal components of the kth and subsequent pixels in the delayed reproduced video signal are the original reproduced video signals. It appears almost where it appears in the signal. On the other hand, during the period in which the phase difference between the horizontal sync signal in the actual reproduced video signal and the horizontal sync signal in the original reproduced video signal is 0, if the actual reproduced video signal is not delayed, The video signal voltage of the still pixel appears at the original time. Thus, if the delay time for the actual reproduced video signal is changed according to the phase difference between the actual reproduced video signal, the horizontal synchronization signal, and the horizontal synchronization signal in the original reproduced video signal, In the video signal of the horizontal scanning line, the actual reproduced video signal can be corrected so that the video signal component of each pixel forming the horizontal scanning line appears at the time when it should originally appear.

Hereinafter, the operation of the camera-integrated VTR at the time of reproducing the video signal from the magnetic tape will be described with reference to FIG.

The motor 25 rotates the drum 24 around which the magnetic tape 23 is wound. On the periphery of the drum 24, from the magnetic tape 23 to RF (Radio Flex)
magnetic head for reading signals (not shown)
Is installed. The magnetic tape 23 is run in a predetermined direction at a constant speed. The traveling speed and the traveling direction of the magnetic tape are controlled by the tape traveling system 29.

FIG. 3 is a diagram showing a general waveform of the composite video signal. FIG. 4 is a diagram showing a recording track pattern on a magnetic tape in a helical scan VTR.

With reference to FIG. 3A, the composite video signal is
The video signal component of each field and the period from the end position of the video signal of each field to the start position of the video signal of the next field, that is, the vertical synchronization signal component and the horizontal synchronization signal component that are inserted in the vertical blanking period. including. (A color burst signal is not shown in FIG. 3A.) FIG. 5 is a diagram showing a signal waveform in the vertical blanking period. Referring to FIG. 5, the horizontal synchronizing signal is a pulse (horizontal synchronizing pulse) generated every 1H (H is one horizontal scanning period).
Is. On the other hand, each vertical synchronization signal is generated in a so-called vertical synchronization pulse, which is a pulse having a narrow width that is generated in twice the horizontal synchronization cycle, and in a cycle that is twice the horizontal synchronization pulse cycle.
It includes a so-called equivalent pulse whose width is one half of the horizontal period pulse. The equivalent pulse is inserted in the 3H time period B before and after the 3H time period A in which the vertical synchronizing pulse appears.

Referring to FIG. 4, the magnetic tape 23 is formed with a plurality of tracks 230 which are parallel to each other at a constant angle with respect to the running direction. On each track 230, a video signal component for one field and a horizontal sync signal component and a vertical sync signal component inserted in the vertical blanking period immediately before the start position of this video signal component are recorded. Therefore, the vertical synchronization signal is recorded at the same position on each of these tracks 230.

As the drum 24 of FIG. 1 rotates, the magnetic head 2 mounted on the peripheral edge of the drum 24.
8 sequentially traces these tracks 230 one by one in the direction of the arrow in FIG.

Therefore, in order to reproduce the original composite video signal from the magnetic tape 23, the magnetic head 28 traces the recording position of the vertical synchronizing signal on the track 230 every vertical scanning period. The rotation speed and rotation phase of the drum 24 must be controlled.

Therefore, referring again to FIG. 1, for this control, FG (Flequency Generato) is used.
r) and PG (Pulse Generator)
And a drum servo 1 are provided.

The FG 27 is attached to the motor 25 in order to detect the rotation speed of the drum 24, and outputs a signal having a frequency proportional to the rotation speed of the motor 25. PG26
Is a motor 2 for detecting the rotation phase of the drum 24.
It is attached to the motor 5 and outputs a signal having a phase according to the rotation phase of the motor 25.

Where the magnetic head 28 traces the recording track 230 in FIG. 4 can be known from the rotation phase of the drum 24 in FIG.

In the PG 26, the magnetic head 28 tracks the track 2.
A pulse signal is output when a predetermined position on 30 is reached. Usually, this predetermined position is set at a position separated from the recording position of the vertical synchronizing signal by a distance corresponding to 6.5H. Therefore, the magnetic head 28 tracks the track 2 at a timing synchronized with an accurate vertical synchronization signal generated separately.
If the recording position of the vertical synchronizing signal on 30 is traced, as shown in FIG. 3B, from the PG 26, the magnetic head 28 is moved from the recording track 230 to the original video signal (FIG. 3A). The pulse signal is output at the time point when the signal 6.5H before the vertical synchronizing signal of () is read. However, if the magnetic head 28 traces the recording position of the vertical synchronizing signal on the track 230 at a timing different from the timing synchronized with the accurate vertical synchronizing signal, P
The output pulse of G26 appears at a position different from the position separated by 6.5H from the vertical synchronizing signal of the reproduced video signal.

That is, if the rotational phase of the track 24 is such that each track 230 is traced by the magnetic head 28 at proper timing and speed, then P
A certain relationship is established between the timing at which the pulse is output from G26 and the timing at which the accurate vertical synchronizing signal is generated. However, the rotation phase of the drum 24 is
As long as each track 230 is not traced to the magnetic head 28 at the proper timing and speed, the magnetic head 28 is traced between the timing at which a pulse is output from the PG 26 and the timing at which the accurate vertical synchronization signal is generated. A certain relationship is no longer established. Therefore, PG2
Based on the output signal of No. 6 and the accurate vertical synchronizing signal, how much the timing at which the magnetic head 28 starts tracing each track 230 deviates from the proper timing,
That is, it is possible to determine how much the rotational phase of the drum 24 deviates from the proper phase.

Therefore, the drum servo 1 compares the phase of the output signal of the PG 26 with the phase of the accurate vertical synchronization signal separately generated by the SSG (synchronization signal generator) 201, and detects the phase difference between these signals. The driver 2 is controlled accordingly. That is, the driver 2 controls the rotational phase of the drum 24 to the proper phase as described above while being controlled by the drum servo 1 to slightly increase or decrease the rotational speed of the motor 25.

The rotation speed of the drum 24 is equal to that of each track 23.
When the magnetic head 28 is in a proper speed range capable of tracing 0 at a proper speed, the rotation phase of the drum 24 is adjusted to a proper phase by the operation of the drum servo 1. However, when the rotation speed of the drum 24 deviates greatly from such an appropriate speed range,
Such operation of the drum servo 1 makes it impossible to force the rotation phase of the drum 24 to a proper phase.

Therefore, in such a case, the drum servo 1 detects the speed of the drum 24 based on the output frequency of the FG 27, and controls the driver 2 according to the detected speed. That is, the driver 2 is controlled by the drum servo 1 to change the speed of the motor 25 to some extent, and the rotational speed of the drum 24 can be adjusted by the phase control based on the output signal of the PG 26 in the drum servo 1. Force to a certain range.

Thus, the phase comparison for the phase control in the drum servo 1 requires the reference signal having the stable frequency and phase. As described above, the reference signal is generally an output signal of a crystal oscillator (not shown) provided in the drum servo 1 or a reference oscillator (not shown) provided in a video circuit for creating a chroma signal. ) such as dividing the signal a signal 3.58MH _Z output from is used. However, in this embodiment, the output signal of the SSG 201 is used as described above.

The switching circuit 22 outputs the output signal of the SSG 201 in the video camera section 200 and a sync signal (vertical sync signal and horizontal sync signal) extracted from the video signal to be recorded when the video signal is recorded on the magnetic tape 23. Signal) and either one of the signals) is selectively applied to the drum servo 1.
At the time of reproducing the video signal, the switching circuit 22 gives the output signal of the SSG 201 to the drum servo 1.

The output signal of the SSG 201 is also input to the time axis fluctuation removing circuit 150. Time fluctuation removal circuit 150
Operates based on the output signal of the SSG 201 so as to remove the time base fluctuation of the reproduced video signal.

The output signal of the magnetic head 28 tracing the magnetic tape 23 is amplified by the head amplifier 3.
A composite video signal is stored in each track 230 of the magnetic tape 23 in a form in which a low-frequency converted chroma signal is superimposed on an FM-modulated luminance signal. Therefore, an FM-modulated luminance signal (hereinafter referred to as FM luminance signal) and a low-frequency converted chroma signal (hereinafter referred to as low-frequency conversion) are provided on the high-frequency side and the low-frequency side of the output signal of the magnetic head 28, respectively. (Called a chroma signal).

Therefore, the high-pass filter 4 extracts only the FM luminance signal from the output of the head amplifier 3 by passing only the high frequency component of the output signal of the head amplifier 3. On the other hand, the low-pass filter 5 extracts only the low frequency conversion chroma signal from the output signal of the head amplifier 3 by passing only the low frequency component of the output of the head amplifier 3.

The limiter 9 removes the level fluctuation of the FM luminance signal and supplies it to the demodulation circuit 10. The demodulation circuit 10 demodulates the FM luminance signal from the limiter 9 to obtain the original luminance signal before FM modulation. The demodulated luminance signal (hereinafter, referred to as a reproduction luminance signal) is processed by the time variation removing circuit 150.
After the time axis error is removed, it is given to the noise canceller 12.

The noise canceller 12 removes the noise of the input luminance signal and gives it to the Y / C mix circuit 13 in order to improve the quality of the reproduced image.

On the other hand, the low-pass conversion chroma signal extracted by the low-pass filter 5 (hereinafter, referred to as a reproduction chroma signal) is supplied to the conversion circuit 7 after its time axis error is corrected by the time fluctuation removing circuit 150. ..

The conversion circuit 7 restores the input low-frequency converted chroma signal to a chroma signal having the original carrier frequency before low-frequency conversion and applies it to the band-pass filter 8.

The bandpass filter 8 extracts only the components necessary for obtaining the original composite video signal before being recorded on the magnetic tape 23 from the chroma signal from the conversion circuit 7 and Y
/ C to the mix circuit 13.

The Y / C mix circuit 13 synthesizes the luminance signal supplied from the noise canceller 12 and the chroma signal supplied from the bandpass filter 8 to reproduce the original composite video signal.

Next, the structure and operation of the time axis fluctuation eliminating circuit 150 will be specifically described.

In the time axis fluctuation eliminating circuit 150, SS
The output signal of G201 is applied to the horizontal sync extraction circuit 17. The horizontal sync extraction circuit 17 extracts only the horizontal sync signal component from the output signal of the SSG 201 to extract the phase shift circuit 1
Give to eight.

The phase shift circuit 18 delays the phase of the horizontal sync signal component from the horizontal sync extraction circuit 17 by an amount corresponding to the output signal of the buffer filter 21, and the phase comparator 1
Give to 6.

The phase comparator 16 compares the phase of the output signal of the phase shift circuit 18 with the phase of the output signal of the horizontal sync extraction circuit 15, and outputs a signal having a voltage level corresponding to the phase difference between these signals. Apply to buffer filters 19 and 21.

The buffer filter 19 is the phase comparison circuit 1
Only the predetermined frequency component is extracted from the output signals of 6 and given to the phase shift circuit 18.

A CCD (Charge Coupled device) delay element 6 delays the reproduced chroma signal output from the low-pass filter 5 by a time period having a length corresponding to the output frequency of the voltage controlled oscillator 20 and applies it to the conversion circuit 7.

The CCD delay element 11 delays the reproduced luminance signal output from the demodulation circuit 10 by a time period having a length corresponding to the output frequency of the voltage controlled oscillator 20, and supplies it to the noise canceller 12 and the sync separation circuit 14.

The sync separation circuit 14 separates and extracts sync signal (vertical sync signal and horizontal sync signal) components from the reproduction luminance signal delayed by the CCD 11.

The horizontal sync extraction circuit 15 includes the sync separation circuit 1
Only the horizontal synchronizing signal component is extracted from the synchronizing signal components separated by 4, and the extracted horizontal synchronizing signal component is given to the phase comparison circuit 16.

Therefore, in the phase comparison circuit 16,
The phase difference between the accurate horizontal sync signal output by the SSG 201 and the horizontal sync signal included in the reproduced video signal is detected. As a result, both CCD delay elements 6 and 11 delay the input signal by a length of time corresponding to the phase of the horizontal synchronizing signal representing the time information of this signal. As a result, both the reproduction chroma signal and the reproduction luminance signal output from the CCD delay elements 6 and 11 are
The time axis error is corrected.

Hereinafter, the operation of the time fluctuation removing circuit 150 will be described in more detail with reference to FIGS. 6 to 8.

FIG. 6 is a diagram showing output signal waveforms of main circuits in the time fluctuation removing circuit 150. FIG. 7 shows C
It is a graph which shows the general characteristic of a CD delay element. Figure 8
[Fig. 4] is a graph showing general characteristics of a voltage controlled oscillator.

The horizontal sync extraction circuit 17 is, for example, MMV.
Including oscillators. This oscillator synchronizes with the falling edge of the output signal (FIG. 6A) of the SSG 201, and applies a high level potential for a certain period of time longer than the pulse width of the equivalent pulse and shorter than the pulse width of the horizontal synchronizing pulse. Works to output. As a result, from the output signal of the SSG 201, the equivalent pulse and the vertical sync pulse, and the SS
Noise included within the fixed time period from the fall of the output signal of G201 is removed. That is, as shown in FIG. 6B, this oscillator outputs a signal which rises in synchronization with the fall of the horizontal sync signal and which has the same frequency as the horizontal sync signal. Next, the phase shift circuit 18 outputs the output signal of the horizontal synchronization extraction circuit 17 (see FIG. 6).
The length of the period in which (b) is at a high level is changed to a time period t1 having a length corresponding to the output voltage of the buffer filter 21 to obtain a signal as shown in FIG. 6 (c). Next, the phase shift circuit 18 creates a signal as shown in FIG. 6 (d) which rises in synchronization with the fall of this signal (FIG. 6 (c)) and gives it to the phase comparator 16. .. Therefore, the phase comparator 16 receives a signal whose phase is delayed from the horizontal synchronizing signal output by the SSG 201 by a time period t1 having a length corresponding to the output voltage of the buffer filter 21.

The phase comparison circuit 16 includes, for example, a clock pulse generator 160 which outputs a clock pulse at a constant frequency sufficiently higher than the frequency of the output signal of the phase shift circuit 18, a counter 161, and a sample hold circuit 162. including.

The counter 161 synchronizes with the rising edge of the output signal of the phase shift circuit 18 and the clock generation circuit 16.
The number of output pulses of 0 is started to be counted, the counting operation is stopped in synchronization with the fall of the output signal of the phase shift circuit 18, and the count value is reset to 0. The counter 161 outputs a voltage of a level proportional to the count value to the sample hold circuit 162. Therefore, the output voltage of the counter 161 is the output signal of the phase shift circuit 18 as shown in FIG.
It rises in proportion to time from each rising time in (d) to the falling time of the output signal of the phase shift circuit 18.

The sample hold circuit 162 is the counter 1
The output voltage of 61 is sampled in synchronization with the rising edge of the output signal of the horizontal sync extraction circuit 15, and the sampled voltage is continuously output until the next rising time of the output signal of the horizontal sync extraction circuit 15. This sample hold circuit 1
An output voltage of 62 (hereinafter referred to as a phase error voltage) is applied to buffer filters 19 and 21.

Therefore, if the rising timing of the output signal of the horizontal sync extraction circuit 15 matches the rising timing of the output signal of the phase shift circuit 18, the output voltage of the sample hold circuit 162 is 0V. However, if the rising timing of the output signal of the horizontal sync extraction circuit 15 is later than the rising timing of the output signal of the phase shift circuit 18, the sample hold circuit 162 sets this at the time when the output voltage of the counter 161 is rising. Since sampling is performed, the output voltage of the sample hold circuit 162 becomes higher than 0V. As the rising timing of the output signal of the horizontal sync extraction circuit 15 deviates from the rising timing of the output signal of the phase shift circuit 18, the sample hold circuit 162 samples the output voltage of the counter 161 at a higher time. Therefore, the output voltage of the sample hold circuit 162 becomes high. That is, the phase error voltage is the horizontal synchronization extraction circuit 15
2 and the output signal of the phase shift circuit 18 have a magnitude proportional to the phase difference.

Therefore, the level of the output signal of the phase comparison circuit 16 changes according to the change in the difference between the phase of the output signal of the horizontal sync extraction circuit 15 and the phase of the output signal of the phase shift circuit 18. However, the output signal of the phase comparison circuit 16 is
Due to a cause which will be described later, an extra signal component other than the level fluctuation due to the phase difference between the output signal of the horizontal sync extraction circuit 15 and the output signal of the phase shift circuit 18 is included. Therefore, the buffer filters 19 and 21 remove such extra signal components from the output signal of the phase comparison circuit 16. As a result, the voltage controlled oscillator 20 and the phase shift circuit 18
In either of the above, a phase error voltage signal representing only the fluctuation of the phase difference between the output signal of the horizontal sync extraction circuit 15 and the output signal of the phase shift circuit 18 is applied.

Referring to FIG. 8, the output frequency f of the voltage controlled oscillator 20 is the voltage V supplied to this as a control voltage.
Increases in proportion to. Therefore, the higher the phase error voltage is, that is, the more the phase of the output signal of the horizontal sync extraction circuit 15 is delayed from the phase of the output signal of the phase shift circuit 18, the higher the frequency signal is supplied to the CCD delay elements 6 and 11. It

FIG. 9 is a plan view and a sectional view showing the basic structure of the CCD delay element. Referring to FIG. 9, the CCD delay element basically includes a plurality of stages of electrodes 910 formed on a semiconductor substrate 900. These multiple stages of electrodes 91
0 are externally slightly shifted in phase from each other, and voltage signals of the same frequency are supplied as drive voltages, respectively, so that an amount of charge proportional to the input signal voltage is applied to a plurality of stages along the surface of the semiconductor substrate. It is possible to transfer under the electrode 910 along the arrangement direction of these electrodes. Therefore, the delay time τ of the input signal by the CCD delay element
Is represented by f, where f is the frequency of the clock signal applied to each of the plurality of stages of electrodes, and N is the number of stages of the electrode 910.

That is, referring to FIG. 7, the signal delay time τ of the CCD delay element is inversely proportional to the frequency f of the signal driving the CCD delay element. In FIG. 1, the output signal of the voltage controlled oscillator 20 is the CCD delay elements 6 and 11
Is a signal for driving. Therefore, the longer the phase delay of the output signal of the horizontal sync extraction circuit 15 with respect to the output signal of the phase shift circuit 18 and the higher the phase error voltage, the longer the time the reproduction luminance signal is delayed by the CCD delay element 11 and the reproduction chroma signal. The time delayed by the CCD delay element 6 becomes shorter.

Now, when the phase error voltage is 0V, the output frequency of the voltage controlled oscillator 20 becomes the minimum, so that the delay times in the CCD delay elements 6 and 11 become the maximum at this time. On the other hand, the phase shift circuit 18 advances the phase of the output signal of the horizontal synchronization extraction circuit 17 by an amount proportional to the output voltage of the buffer filter 21. Specifically, when the phase error voltage is 0 V, the phase shift circuit 18 changes the phase of the output signal of the horizontal synchronization extraction circuit 17 to the voltage controlled oscillator 2
Advance by an amount corresponding to the signal delay time (hereinafter referred to as the basic delay time) in each of the CCD delay elements 6 and 11 when the output frequency of 0 is the maximum. Therefore, the phase error voltage becomes 0 V only when the phase of the sync signal in the reproduction luminance signal before being delayed by the CCD delay element 11 and the phase of the sync signal output by the SSG 201 match.

For example, since the phase delay of the synchronizing signal in the reproduction luminance signal delayed by the CCD delay element 11 with respect to the synchronizing signal output by the SSG 201 corresponds to the basic delay time in the CCD delay element 11, Assume that the delay time is larger than the equivalent.

In such a case, the sync signal in the reproduction luminance signal delayed by the CCD delay element 11, that is, the output signal of the sync separation circuit 14 is the sync signal output from the SSG 201 as shown in FIG. 6 (g). Signal (Fig. 6 (a))
Than the basic delay time t1 in the CCD delay element 11
The phase has a phase greatly delayed as described above. But,
At this time, the phase error voltage has the same magnitude as before, that is, 0V. Therefore, the phase of the output signal of the phase shift circuit 18 (FIG. 6 (d)) is a phase advanced from the phase of the horizontal synchronizing signal output by the SSG 201 by the basic delay time t1 in the CCD delay element 11.

On the other hand, the horizontal sync extraction circuit 15 operates similarly to the horizontal sync extraction circuit 17, removes the vertical sync pulse, the equivalent pulse and noise from the output signal of the sync separation circuit 14 and outputs only the horizontal sync pulse. Extract. As a result, as shown in FIG. 6H, the horizontal sync extraction circuit 15 becomes a signal which rises in synchronization with the fall of the horizontal sync signal output from the CCD delay element 11.

Therefore, the rising timing of the output of the horizontal sync extraction circuit 15 is delayed by the time t2 from the rising timing of the output signal of the phase shift circuit 18. This is because the sampling timing in the sample-hold circuit 162 is the rising timing of the output signal (FIG. 6D) of the phase shift circuit 18, that is, the counter 161 causes the clock generator 1 to operate as shown in FIG.
This means that the time t2 is delayed from the timing at which the counting of 60 output pulses is started. Therefore, as shown in FIG. 6 (f), the phase error voltage is 16 V at the time when the time t 2 has elapsed from the time when the counter 161 started the counting, from the magnitude of 0 V until then.
The voltage rises to the voltage v corresponding to the count value of 1.

As a result, the output frequency of the voltage-controlled oscillator 20 becomes higher than before, so that the delay time τ in the CCD delay elements 6 and 11 becomes equal to the output signal of the horizontal sync extraction circuit 15 and the output signal of the phase shift circuit 18. It is shortened by the time t2 corresponding to the phase difference between As a result, the phase of the sync signal output from the CCD delay element 11 leads the phase of the sync signal.

Therefore, the phase of the horizontal synchronizing signal included in the reproduction luminance signal output from the CCD delay element 11 changes in the direction in which it coincides with the phase of the output signal of the phase shift circuit 18 until then. As a result, the reproduction luminance signal output from the demodulation circuit 10 has a phase of the synchronization signal included therein which is S
It is delayed by the CCD delay element 11 so as to match the phase of the sync signal output from the SG 201.

On the other hand, when the output voltage of the buffer filter 21 rises to v, the phase shift circuit 18 operates so as to advance the phase of the output signal of the horizontal sync extraction circuit 17 more than before. As a result, the phase of the output signal of the phase shift circuit 18 is obtained by delaying the phase of the horizontal synchronizing signal output by the SSG 201 by an amount corresponding to the length of the delay time after the change of the CCD delay element 11. Therefore, even after that, in the phase comparison circuit 16, CC
The reproduction luminance signal whose phase is delayed by the amount corresponding to the delay time in the D delay element 11, and the SSG whose phase is delayed by the amount corresponding to the delay time in the CCD delay element 11.
The output horizontal synchronizing signal of 201 is compared in phase. If they match, the phase error voltage becomes 0V, so the CCD
The signal delay time in the delay elements 6 and 11 returns to the basic delay time. If they do not match, as described above, the phase error voltage is increased by the amount corresponding to the phase difference between them, and the signal delay time in the CCD delay element 11 is the reproduction luminance signal output from the demodulation circuit 10. The phase of the synchronizing signal therein is shorter than that so that it matches the phase of the synchronizing signal output from the SSG 201.

In this way, in the phase comparison circuit 16, the horizontal synchronizing signal included in the reproduced video signal and the accurate horizontal synchronizing signal generated by the SSG 201 are phase-compared, and according to the phase difference between these signals. The reproduced chroma signal and reproduced luminance signal output from the low-pass filter 5 and the demodulation circuit 10 are delayed. That is, it is detected how much the phase of the sync signal in the reproduction luminance signal output from the demodulation circuit 10 lags behind the phase of the sync signal output from the SSG 201, and the reproduction luminance signal output from the demodulation circuit 10 is detected. The larger the phase delay of the synchronizing signal is, the reproduction luminance signal output from the demodulation circuit 10 and the reproduction chroma signal output from the low-pass filter 5 are not delayed much in the CCD delay elements 6 and 11, respectively, and are not delayed. And to the noise canceller 12.

The short delay time in the CCD delay elements 6 and 11 means that the reproduction chroma signal output from the low-pass filter 5 and the reproduction luminance signal output from the demodulation circuit 10 are in phase with the conversion circuit 7 and the noise canceller 12, respectively. It means that it is given without much delay. Therefore, when the phase of the sync signal in the reproduced video signal deviates from the phase of the reference sync signal due to the time base error included in the reproduced video signal, the direction opposite to this deviation is produced in proportion to the magnitude of this deviation. , The phase of the reproduced video signal is displaced. That is, the time base error included in the reproduced video signal is corrected. As a result, the reproduced composite video signal output from the Y / C mix circuit 13 has reduced time axis error components mixed in the reproduced video signal in the tape head system.

Now, the phase error voltage has a magnitude corresponding to the time base error included in the reproduced video signal at a position between the output signal of the horizontal sync extraction circuit 17 and the output signal of the horizontal sync extraction circuit 15. This is the case where the phase difference matches the time base error included in the reproduced video signal. Therefore, the phase comparison circuit 16 can output an appropriate phase error voltage for controlling the delay time in the CCD delay elements 6 and 11 to a value capable of removing the time base error included in the reproduced video signal. Only when the time axis error included in is within a certain small range. Such a range is called an operating range of the phase comparison circuit 16.

Even when the traveling speed of the magnetic tape 23 fluctuates due to the disturbance of the tape traveling system 29, the magnetic tape 2
8 does not trace each recording track 230 at the proper timing as described above, the phase difference between the vertical synchronizing signal generated by SSG 201 and the output signal of PG 26 fluctuates. If the fluctuation of the phase difference is large, the time base error generated in the reproduced video signal due to the fluctuation deviates from the operation range of the phase comparison circuit 16. However, PG26
The phase fluctuation (that is, the time axis error) that occurs in the reproduced video signal due to such a very large phase fluctuation that occurs in the output signal of the It is a variable component. The time axis fluctuation component of the reproduced video signal is the phase comparison circuit 16
Is propagated to the output signal of. Therefore, when a large phase variation occurs in the output signal of the PG 26, the phase error voltage signal includes a signal component having a frequency considerably lower than the jitter component normally included in the reproduced video signal. Therefore, buffer filters 19 and 21 are provided in order to remove such low frequency components other than the normal jitter component.

It should be noted that changing the phase of the reproduced video signal so that the phase of the output signal of the horizontal sync extraction circuit 15 matches the phase of the output signal of the phase shift circuit 18 is generated by the SSG 201 in the reproduced video signal. It means that a low frequency component of the same level as that of the horizontal synchronizing signal is mixed. However, since such a low frequency component can be removed by a television receiver (not shown) that receives the reproduced composite video signal, it is possible that such a low frequency component is mixed in the reproduced composite video signal in the reproduced image. Has no adverse effect.

Next, the operation of this camera-integrated VTR at the time of recording when a video signal is recorded on the magnetic tape 23 will be described with reference to FIGS. 1 and 2. Figure 2
It is a schematic block diagram showing a configuration of a video camera unit 200 of this camera-integrated VTR.

Referring to FIG. 2, lens system 101 takes in reflected light from a subject (not shown) and irradiates it on the light receiving surface of CCD image pickup device 102. As a result, an optical image of the subject is formed on the light receiving surface of the image sensor 102.

The image pickup device 102 converts the optical image formed on the light receiving surface thereof into an electric signal in accordance with a predetermined timing pulse output from the SSG 201 and converts the optical signal.
Give to 03.

The signal processing circuit 103 converts the electric signal from the image pickup device 102 into a luminance signal Y representing the luminance of the subject.
Two color difference signals R-Y and B-Y representing the color of the object
And create.

The low-pass filter 105 extracts only a predetermined low frequency component from the luminance signal Y created by the signal processing circuit 103 and supplies it to the vertical contour compensation circuit 106.

The vertical contour compensating circuit 106 emphasizes the component of the output signal of the low-pass filter 105, which corresponds to the luminance change portion in the vertical direction of the image, and gives it to the adder 113.

The horizontal contour compensating circuit 111 uses the signal generated intermediately in the removal of the signal processing in the vertical contour correcting circuit 106 to correspond to the luminance change portion in the horizontal direction of the image in the output signal of the low pass filter 105. The component to be applied is emphasized and given to the amplifier 112.

The amplifier 112 is a horizontal contour compensation circuit 111.
The output signal of 1 is amplified and given to the adder circuit 113.

The vertical contour compensation circuit 106 includes two CCDs.
Includes delay elements 108 and 109, adder 125, and enhancement circuit 110.

The CCD delay element 108 delays the luminance signal output from the low-pass filter 105 by one horizontal scanning period under the control of a predetermined clock signal. CCD
The delay element 109 delays the luminance signal delayed by the CCD delay element 108 by one horizontal scanning period under the control of the clock signal.

The adder 125 outputs the output signal of the CCD delay element 109, that is, the luminance signal delayed by two horizontal scanning periods, and the output signal of the CCD delay element 108, that is,
By synthesizing the luminance signal delayed by one horizontal scanning period, a component corresponding to a luminance change portion in the vertical direction of the screen is extracted and given to the emphasis circuit 110.

The enhancement circuit 110 superimposes the component extracted by the adder 125 on the luminance signal before being delayed. The signal obtained by this is given to the adder 113 as a luminance signal which has been subjected to the processing for vertical contour compensation.

The luminance signal delayed by one horizontal scanning period by the CCD delay element 108 is applied to the horizontal contour compensation circuit 111.

On the other hand, the color difference signals RY and BY are input to the synchronizing circuit 107. Generally, the color difference signals R-Y and B-Y of each horizontal scanning line are obtained alternately every horizontal scanning period. Therefore, the color difference signal R-Y and the color difference signal B-Y are temporally displaced by one horizontal scanning period. Therefore,
The synchronization circuit 107 outputs the color difference signals R-Y and B.
It operates so as to eliminate the time shift between Y and Y.

In the synchronizing circuit 107, the switching circuit 11
5 is color difference signals R-Y and B- for each horizontal scanning period.
Output Y alternately. The output of switching circuit 115 is applied to CCD delay element 116 and switching circuits 117 and 118. CCD delay element 116 delays the output signal of switching circuit 115 by one horizontal scanning period and supplies it to switching circuits 117 and 118.

The switching circuit 117 includes the CCD delay element 116.
And the output signal of the switching circuit 115 are alternately applied to the low-pass filter 119 every horizontal scanning period. Similarly, the switching circuit 118 alternately supplies the output signal of the CCD delay element 116 and the output signal of the switching circuit 115 to the low-pass filter 120 for each horizontal scanning period. The switching circuit 118 supplies the output signal of the switching circuit 115 to the low-pass filter 120 while the switching circuit 117 supplies the output signal of the CCD delay element 116 to the low-pass filter 119.

Therefore, the color difference signals RY and BY of the same scanning line are simultaneously input to the low pass filters 119 and 120, respectively. Low-pass filter 11
9 and 120 are the input color difference signals R-Y, respectively.
And a predetermined low frequency component of BY is extracted.

The modulator 121 has a low-pass filter 119.
Color difference signal R-Y component extracted by 3.58 MH
_ZBand conversion to low frequency signals. Similarly, modulator 122
Is the color difference signal extracted by the low-pass filter 120.
No. B-Y component is 3.58 MH _ZBand conversion to low frequency signals
To do.

The adder 123 includes modulators 121 and 12
The signals respectively converted by 2 are added and given to the bandpass filter 124.

The bandpass filter 124 includes the adder 12
Only the predetermined band component of the output signal of No. 3 is extracted.
The component extracted by the bandpass filter 124 is given to the adder 113 as a final chroma signal.

The adder 113 has a bandpass filter 12
The chroma signal from No. 4, the luminance signal processed for vertical contour compensation, and the luminance signal processed for horizontal contour compensation are combined and given to the adder 114.

The adder 114 further superimposes the sync signal output from the SSG 201 on the output signal of the adder 113. The signal thus obtained is the final composite video signal (hereinafter referred to as the recording video signal) to be given to the VTR unit 100.

The recording video signal created in the video camera section 200 as described above is given to the amplifier 3 and the vertical synchronization extraction circuit 30 via the recording signal processing circuit 31 of FIG.

The vertical sync extraction circuit 30 extracts the vertical sync signal contained in the recording video signal and supplies it to the switching circuit 22 as a video sync signal. The head amplifier 3 supplies the recording video signal processed by the recording signal processing circuit 31 to the magnetic head 28 attached to the drum 24.

The switching circuit 22 gives the vertical sync signal from the vertical sync extraction circuit 30 to the drum servo 1 contrary to the reproduction.

The drum servo 1 uses the vertical synchronizing signal extracted from the recording video signal, that is, a so-called video synchronizing signal, similarly to the vertical synchronizing signal from the SSG 201 at the time of reproduction, and based on the outputs of PG 26 and FG 27. The magnetic head 28 operates to control the rotation phase and rotation speed of the drum 24 so that the recording track 230 as shown in FIG. 4 is formed on the magnetic tape 23.

That is, the drum servo 1 is 6.5H from the time when each vertical synchronizing signal is supplied to the magnetic head 28.
Just before, so that the pulse can be obtained from PG 26 at the time,
The rotation phase of the motor 25 is controlled via the driver 2 in accordance with the phases of the output signal of the PG 26 and the video synchronization signal, and the output frequency of the FG 27 is maintained within a predetermined frequency range via the driver 2. The rotation speed of the motor 25 is controlled.

The tape running system 29 runs the magnetic tape 23 at a constant speed. Therefore, the recording video signal is recorded on the magnetic tape 23 for each field so that the vertical synchronizing signal is recorded at the same position on each recording track 230.

In the above embodiment, the elements 6 and 11 for delaying the reproduction chroma signal and the reproduction luminance signal are provided in the VTR section 100 in order to remove the time base error contained in the reproduction video signal. However, an element in the video camera unit 200 may be used as an element for such a delay.

FIG. 10 is a schematic block diagram showing the overall construction of a camera-integrated VTR in such a case, and shows another embodiment of the present invention. In FIG. 10, the VTR unit 100
The configuration of is mainly shown in the part related to the correction of the time base fluctuation of the reproduced video signal.

Referring to FIG. 10, VTR section 100 differs from that shown in FIG. 1 in that a CCD delay element for delaying a reproduction chroma signal output from low-pass filter 5 and a reproduction luminance output from demodulation circuit 10. It does not include a CCD delay element that delays the signal. VTR unit 10 of this embodiment
The configuration of the other parts of 0 is the same as that shown in FIG. However, in the figure, the configuration other than the part related to the correction of the time base fluctuation of the reproduced video signal is omitted for simplicity.

On the other hand, the video camera unit 200 has five switching circuits 130 to 130 in addition to the functional blocks shown in FIG.
Including 135.

The switching circuit 135 outputs the above-mentioned clock signal to the CCD delay elements 108 and 109 for controlling the CCD delay elements 108 and 109 to delay the input signal by one horizontal scanning period at the time of recording, At the time of reproduction, the output signal of the voltage controlled oscillator 20 in the VTR section 100 is operated to be applied to the CCD delay elements 108 and 109.

The switching circuit 131 supplies the luminance signal output from the low-pass filter 105 to the CCD delay element 108 during recording, and the reproduction chroma signal output from the low-pass filter 105 in the VTR unit 100 during reproduction.
It operates to feed the CD delay element 108.

The switching circuit 132 gives the output signal of the CCD delay element 108 to the switching circuit 133 at the time of recording, and outputs the output signal of the CCD delay element 108 at the time of reproduction to the VTR section 1.
It operates so as to give to the conversion circuit 7 in 00.

The switching circuit 133 gives the output signal of the switching circuit 132 to the CCD delay element 109 at the time of recording, and gives the reproduction luminance signal outputted from the demodulation circuit 10 in the VTR section 100 to the CCD delay element 109 at the time of reproduction. ..

The switching circuit 134 gives the output signal of the CCD delay element 109 to the adder 125 during recording, and outputs the output signal of the CCD delay element 109 during reproduction.
It is given to the noise canceller 12 in 0.

Therefore, at the time of recording, the low-pass filter 105 is used in the video camera section 200 as usual.
The luminance signal output from C is the C signal for vertical contour compensation.
Addition circuit 125 is delayed by one horizontal scanning period and two horizontal scanning periods by CD delay elements 108 and 109.
The signal delayed by one horizontal scanning period by the CCD delay element 108 is applied to the horizontal contour compensation circuit 111. As a result, the horizontal contour compensation circuit 10
6 and the horizontal contour compensation circuit 111 can respectively output a luminance signal processed for vertical contour compensation and a luminance signal processed for horizontal contour compensation.

On the other hand, during reproduction, the reproduction chroma signal and the reproduction luminance signal generated in the VTR section 100 pass through the CCD delay elements 108 and 109, respectively,
The delay time in the CCD delay elements 108 and 109 is supplied to the conversion circuit 7 and the noise canceller 12, and is controlled by the output frequency of the voltage controlled oscillator 20 in the VTR unit 100. That is, in order to correct the time base error included in the reproduced video signal, two luminance elements that delay the reproduced chroma signal and the reproduced luminance signal, respectively, are used for the luminance signal captured by the video camera unit 200. CCD delay elements 108 and 109 are used to perform contour compensation.

As described above, a part of the circuit in the video camera section 200 is used both for the signal processing in the video camera section 200 and for removing the time base fluctuation of the reproduced video signal in the VTR section 100. And a camera integrated V
It is possible to remove the time axis error included in the reproduced video signal without increasing the scale of the internal circuit of the TR. As a result, the product cost of the camera-integrated VTR can be reduced and the internal circuit configuration can be rationalized.

In the above embodiment, the circuit for vertical contour compensation in the video camera unit 200 is configured to include the two CCD delay elements 108 and 109. However, the processing for vertical contour compensation is performed by a single CCD. It is also possible to use a delay element. So in such a case,
CCD delay element in the horizontal contour compensation circuit and synchronization circuit 1
The CCD delay element (CCD delay element 116 in FIG. 10) in 07 is the CCD delay elements 6 and 1 in FIG.
It may be used as 1.

The switching circuits 131 to 135 in the video camera section 200 and the switching circuit 22 in the VTR section 100.
Is for recording video signals on the magnetic tape 23 attached to the outside of this camera-integrated VTR and for recording the magnetic tape 23.
The output signal is switched in conjunction with the operation switch 202 for the user to select one of the reproductions of the video signal from the. On the other hand, a clock signal for controlling the CCD delay elements 108 and 109 in the vertical contour compensation circuit 106 and the switching circuits 115, 117, 1 in the synchronization circuit 107.
Signals for controlling 18 are generated from SSG 201.

In any of the above embodiments, not only the reproduced luminance signal but also the reproduced chroma signal is delayed to remove the time axis error. Therefore, when there is a time lag between the reproduction chroma signal and the reproduction luminance signal, this deviation is generated between the reproduction chroma signal input to the conversion circuit 7 and the reproduction luminance signal input to the noise canceller 12. No longer exists. Therefore, the time-variation removing circuit 150 of each of the above-described embodiments also has an effect of removing the time difference between the reproduction chroma signal and the reproduction luminance signal.

Further, by delaying the reproduced chroma signal and the reproduced luminance signal to remove the fluctuations in the time axis, the time axis errors of the different kinds of signal components contained in the reproduced video signal are eliminated. Means to correct. Therefore, the time variation removing circuit 15 of each of the above embodiments
According to 0, the time axis error included in the reproduced video signal is more effectively removed, so that the jitter appearing in the reproduced image is more effectively reduced.

As described above, according to the embodiment, since the time base fluctuation correction for the reproduced video signal can be performed without converting the reproduced video signal into a digital signal, the conventional time fluctuation removing circuit is required. The complicated circuit (memory, A / D converter, D / A converter, circuit for controlling data write timing and data read timing in the memory, etc.) is unnecessary. Furthermore, since the time axis correction is performed by changing the phase of the playback video signal in response to the change in the time axis error included in the playback video signal in real time, the time included in the playback video signal is different from the conventional case. Axis error can be detected and removed in real time.

[0155]

As described above, according to the present invention, the time axis error contained in the reproduced video signal read from the recording medium can be effectively used in real time by using a circuit having a simpler structure than the conventional one. Can be removed. Further, if the present invention is applied to a video device such as a VTR with a built-in camera, which has a delay element whose delay time is variable and is not used at the time of reproduction, a new reproduction video signal is delayed in order to remove a time base error of the reproduction video signal. Since it is not necessary to provide such a delay element, it is possible to remove the time base error of the reproduced video signal with a circuit of a smaller scale. Therefore, it is possible to relatively inexpensively provide the video equipment capable of effectively eliminating the lateral vibration that occurs in the reproduced image.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of a VTR unit in a camera-integrated VTR according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a configuration of a video camera unit in the camera-integrated VTR shown in FIG.

FIG. 3 is a waveform diagram for explaining a timing at which a pulse is output from a PG in a VTR section.

FIG. 4 is a diagram showing a formation pattern of recording tracks on a magnetic tape.

FIG. 5 is a diagram showing a waveform of a composite synchronization signal.

FIG. 6 is a waveform diagram for explaining the operation of the time variation removal circuit 150 in FIG.

FIG. 7 is a graph showing characteristics of a CCD delay element.

FIG. 8 is a graph showing characteristics of the voltage controlled oscillator.

9A and 9B are a plan view and a sectional view showing the basic configuration of a CCD delay element.

FIG. 10 is a schematic block diagram showing an overall configuration of a camera-integrated VTR according to another embodiment of the present invention.

FIG. 11 is a waveform diagram for explaining the principle of time-axis fluctuation elimination of the time-axis fluctuation elimination device according to the present invention.

FIG. 12 is a block diagram showing the basic principle of a conventional time axis fluctuation removing device.

FIG. 13 is a waveform diagram for explaining the principle of time fluctuation elimination in the conventional time axis fluctuation elimination device.

FIG. 14 is a schematic view of a screen in which each horizontal scanning line is composed of a plurality of pixels.

FIG. 15 is a schematic block diagram showing a general configuration of a conventional time variation removing circuit.

[Explanation of symbols]

 150 time fluctuation removal circuit 6, 11, 108, 109, 116 CCD delay element 14 sync separation circuit 15, 17 horizontal sync extraction circuit 16 phase comparison circuit 18 phase shift circuit 19, 21 buffer filter 20 voltage controlled oscillator 201 sync signal generator In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A delay means having a variable delay time for delaying a reproduced video signal including a synchronizing signal, a means for extracting the synchronizing signal from the reproduced video signal delayed by the delay means, and a predetermined reference synchronizing signal. A displacement means that receives and displaces the phase of the reference synchronization signal, a displacement amount variable displacement means, a phase difference between the reference synchronization signal whose phase is displaced by the displacement means, and the synchronization signal extracted by the extraction means. Is detected, and the delay time of the delay means is changed in accordance with the detected change in the phase difference, and the displacement amount in the displacement means is adjusted so that the phase difference after the change is maintained. And a time axis fluctuation removing device. 2. A rotary drum having a magnetic head for reading the video signal from a magnetic tape on which a video signal including the sync signal is recorded, and means for generating a predetermined reference sync signal in addition to the sync signal. A unit for detecting a rotation phase of the rotating drum; a unit for controlling a rotation phase of the rotating drum based on a detection output of the detecting unit and a reference synchronization signal generated by the generating unit; And a means for removing a time axis error included in the video signal, wherein the removal means delays the read video signal by a delay time variable delay means, and the video signal delayed by the delay means. Means for extracting the synchronization signal; displacement means for displacing the phase of the synchronization signal generated by the generation means; variable displacement amount; phase displacement by the displacement means Reference synchronization signal,
A change in the phase difference between the synchronizing signal extracted by the extracting means is detected, the delay time in the delay means is changed according to the detected change in the phase difference, and the displacement amount of the displacing means is changed. A magnetic recording / reproducing apparatus, comprising means for adjusting the phase difference after the change. 3. A video signal including a sync signal is recorded during reproduction.
Reading the video signal from the recorded magnetic tape, and
When recording, record video signal including sync signal on magnetic tape
A rotating drum having a magnetic head, a unit for generating a predetermined reference synchronizing signal, a unit for detecting the phase of the rotating drum, a detection output of the detecting unit during the reproduction,
Based on the reference synchronization signal generated by the stage,
It controls the rotation phase of the rolling drum,
The detection output of the detection means and the recording on the magnetic tape
Based on the synchronization signal included in the video signal
A means for controlling the rotation phase of the rolling drum, and removing a time axis error included in the read video signal.
Means for capturing an image of a subject at the time of recording, an image output of the image capturing means at the time of recording,
Based on the reference synchronization signal generated by the stage,
And means for creating a video signal to be recorded on the tape.
The video signal creating means delays the imaging output of the imaging means.
Delaying means for extending the delay time, the time axis error removing means for displacing the phase of the generated reference synchronization signal,
A variable amount displacement means, and the read means for delaying the read video signal during the reproduction.
And means for supplying the synchronization from the delay output of the delay means during the reproduction.
Means for extracting a signal, and the synchronizing signal extracted by the extracting means during the reproduction
And the reference synchronization signal displaced by the displacement means
The change in the phase difference of the
On the other hand, when the delay time in the delay means is changed,
In addition, the amount of displacement of the displacement means is maintained by the phase difference after the change.
And a magnetic recording / reproducing device including a means for adjusting so as to drip.
Place