JP3109874B2 - Still video equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still video apparatus for recording an image signal on a recording medium such as a magnetic disk.

[0002]

2. Description of the Related Art Conventionally, a still video apparatus is configured to FM-modulate and record an input image signal.
The band of the signal recorded on the track of the magnetic disk is determined. Further, the width of this band is limited by the structural reason of the disk device and cannot be increased without limit.

For this reason, in a conventional still video device, even if a high quality image signal, that is, a wideband image signal is input to the still video device, the resolution of the image is limited. In particular, when this image is printed out, the image quality is limited. The decline is significant. Therefore, the present applicant has filed a patent application filed on July 16, 1991 with a configuration in which a wideband image signal is recorded by a narrowband still video device using means such as subsampling (decimation) or time axis conversion. Proposed. In this still video apparatus, an input image signal is added with a synchronization signal generated by a synchronization signal generation circuit in order to synchronize between horizontal scanning lines.

[0004]

However, at the time of reproduction, sampling of an image signal must be performed with high precision timing. On the other hand, when a synchronization signal used in a conventional still video apparatus is used as a reference, If jitter or a rounded waveform of the synchronization signal occurs, the image signal cannot be sampled accurately, and there is a risk that the reproduced image is degraded due to a shift in pixels. An object of the present invention is to provide a still video device that can always accurately sample an image signal at the time of reproduction and can obtain a high-quality image.

[0005]

According to a first aspect of the present invention, there is provided a still video apparatus which stores an input signal including a first synchronization signal and an image signal in a memory based on the first synchronization signal.
Signal storage means and a second synchronization signal for generating a second synchronization signal.
Input from a memory using a signal generation means and a second synchronization signal
Means for reading out a signal;
Means for pre- adding, the input signal and the second synchronization signal
Means for recording on a recording medium . Further, the still video device according to the second aspect of the present invention provides an image signal, a first synchronization signal, and a second synchronization signal from a recording medium in which an input signal including the first synchronization signal and the image signal is stored together with the second synchronization signal. Means for reproducing, and a second means for separating a second synchronizing signal from a signal reproduced by the reproducing means.
Signal separation means, based on the separated second synchronization signal.
Means for separating the first synchronization signal Te, and means for storing the image signals in the memory based on the first synchronization signal, first
A reproduction processing means of the synchronizing signal subjected to predetermined reproduction process to the image signal as a reference, a third for generating a third synchronizing signal
Synchronization signal generating means, and a memory based on a third synchronization signal
And means for reading out an image signal from the device .

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block diagram of a recording system of a still video apparatus to which one embodiment of the present invention is applied.

[0007] The system control circuit 10 is a microcomputer, and controls the whole still video apparatus. The disk device has a magnetic head 11 and a spindle motor 12 for rotating and driving the magnetic disk D. The tracking of the magnetic head 11 is controlled by the system control circuit 10, and the magnetic head 11 is displaced along the radial direction of the magnetic disk D. The drive of the spindle motor 12 is controlled by the system control circuit 10, and rotates the magnetic disk D at a rotation speed of, for example, 3600 rpm. While the magnetic disk D is rotating, the magnetic head 1
Numeral 1 is located on a predetermined track of the magnetic disk D, and an image signal and an ID code are recorded on this track. The recording amplifier 13 is controlled by the system control circuit 10 and outputs an image signal and the like to the magnetic head 11. In addition,
The magnetic disk D has 52 tracks, and signals such as image signals are recorded on 50 tracks counted from the outermost track to the inner circumference.

[0008] An operation unit 14 connected to the system control circuit 10 is provided for operating the present still video device. Note that an ID code relating to an image recorded on the magnetic disk D, that is, data such as a recording mode and a shooting date is also input via the operation unit 14.

A high-quality image signal obtained by a still video camera (not shown) or an external input terminal (not shown) includes a luminance signal (Y + S) and a color difference signal (R-
Y, BY) are input to the still video device. In this embodiment, the input image signal is an HDTV
(High-definition television), and the luminance signal (Y + S) and the color difference signals (RY, BY) each include a horizontal synchronizing signal. In the drawing, the symbol (H) attached to the luminance signal and the color difference signal means high image quality. Horizontal synchronization signal S included in luminance signal (Y + S)
Is a luminance signal (Y + S) by the synchronization signal separation circuit 21.
And sent to the memory control circuit 22 and the system control circuit 10. Based on the horizontal synchronization signal S, the memory control circuit 22 converts the AD converters 23, 24, 25, the Y memory 26, the RY memory 27
And the BY memory 28. In addition, the memory control circuit 22 outputs the DA converters 31, 32, 33, based on a synchronization signal from a synchronization signal generation circuit 34 described later.
Y memory 26, RY memory 27, and BY memory 2
8 is controlled.

The luminance signal (Y + S) is AD-converted by an AD converter 23, stored in a delay memory 71 under the control of a memory control circuit 22, and then delayed by a predetermined time and stored in a Y memory 26. This delay processing will be described later in detail. Similarly, the color difference signal (R-
Y) is AD-converted by the AD converter 24 and stored in the delay memory 72, delayed by a predetermined time and stored in the RY memory 27. The color difference signal (BY) is AD-converted by the AD converter 25, stored in the delay memory 73, delayed by a predetermined time, and stored in the BY memory 28. Note that a luminance signal (Y + S), a color difference signal (RY,
BY) are the Y memory 26, the RY memory 27, and the B
When each is stored in the -Y memory 28, it is halved by the memory control circuit 22 as described later.

Y memory 26, RY memory 27 and B memory
The luminance signal (Y + S) and the color difference signals (RY, BY) stored in the Y memory 28 are based on a synchronization signal (reference clock signal) output from the synchronization signal generation circuit 34.
D / A conversion is performed by the D / A converters 31, 32, and 33, respectively. At this time, the reference clock signal is stored in the memories 26, 2
7 and 28 have, for example, half the frequency as compared with a reference clock signal used for recording an image signal. Therefore, the image signal is stored in each of the memories 26, 27 and 28.
Are read out at a relatively slow speed, thereby extending the time axis. The DA-converted luminance signal (Y + S) is input to the Y recording processing circuit 35 and subjected to processing such as FM modulation. Similarly, the two D / A-converted color difference signals (RY, BY) are input to the C recording processing circuit 36 and subjected to processing such as FM modulation.

The ID code input via the operation unit 14 and the system control circuit 10 is subjected to processing such as DPSK modulation in an ID recording processing circuit 37.

The DPSK-modulated ID code, the FM-modulated luminance signal and the chrominance signal are superposed by an adder 38, amplified by a recording amplifier 13, and sent to a magnetic head 11. Then, the ID code, the luminance signal and the color difference signal are recorded on predetermined tracks of the magnetic disk D by the magnetic head 11. As described above, the signal recorded on the magnetic disk D is expanded in time as compared with the signal input to the present still video device. In order to record an image signal on the magnetic disk D by extending the time axis in this manner, the input image is divided and stored in the memories 26, 27, and 28, as described later.

FIG. 2 shows an input image signal and memories 26 and 2.
7 shows a relationship between image signals recorded on the magnetic disks 7 and 28 and image signals recorded on the magnetic disk D. In addition,
In this embodiment, the input image signal is recorded by the frame recording mode, also the number and line frequency scan lines of the input image, you that determined in accordance with HDTV (high definition television) and the like.

In FIG. 2, an input image signal K corresponds to one horizontal scanning line. Band of the input image signal K is f _H
However, the image signals stored in the memories 26, 27, and 28 are sub-sampled (thinned out), whereby the band of the image signal becomes _fH / 2. The image signals of the first field and the second field are divided into first to fourth areas of the memories 26, 27, and stored. That is, the image signal corresponding to the upper half screen of the first field is stored in the first area of the memory, and the image signal corresponding to the lower half screen of the first field is stored in the third area of the memory. The image signal corresponding to the upper half screen of the second field is stored in the second area of the memory, and the image signal corresponding to the lower half screen of the second field is stored in the fourth area of the memory. The image signals stored in the first to fourth areas are recorded on the first to fourth tracks of the magnetic disk D, respectively.

A luminance signal (Y + S) and color difference signals (RY, BY), which are input image signals, are stored in memories 26, 27, and 28, respectively, after being delayed by a predetermined time. The included horizontal synchronizing signal S is also stored in the memories 26, 27, and 28 together with the image signal.

The image signals stored in the memories 26, 27, and 28 are expanded on the time axis by a factor of two at the time of recording on the magnetic disk D, whereby the band of the image signal becomes _fH / 4.
Therefore, even if the input image signal conforms to the HDTV system, it is written on the magnetic disk D by the still video device while maintaining high image quality. When writing to the magnetic disk D, the additional synchronization signal X generated by the synchronization signal generation circuit 34 is recorded immediately before the horizontal synchronization signal S for the luminance signal (Y + S).

FIG. 3 shows a configuration of the memory 2 by delaying an input signal.
It is a figure which shows the effect | action stored in 6,27,28. The input signal includes an image signal K and a synchronization signal S provided in front of the image signal K. Also, behind the image signal K,
A succeeding synchronization signal S 'is formed, and the next image signal K' is formed further behind the synchronization signal S '. That is, the input signal is composed of a synchronous signal and an image signal that are repeatedly formed.

This input signal is supplied to delay memories 71, 72, 7
3 and is output after being delayed by a time τ _{1 under} the control of the memory control circuit 22. The signals output from the delay memories 71, 72, and 73, that is, the delay signals are converted into the Y memory 26, the RY memory 27, and the B
-Input to the Y memory 28. The address switching signal is output from the memory control circuit 22 and is a pulse signal having a time width τ _2. Delayed signals are input to the memories 26, 27 and 28 in synchronization with the fall of the address switching signal. The address switching signal is output before and after the image signal K. The address switching signal output before the image signal K falls before the preceding synchronization signal S by a predetermined time, and the address switching signal output after the image signal K is lower than the rear end of the image signal K. Fall after a predetermined time. Therefore, the memories 26, 27, 2
8 stores a synchronization signal S and an image signal K in pairs.

The memory 2 for the synchronizing signal S and the image signal K
6, 27, and 28, the memory control circuit 22 stores the data in the memory 2 every time the address switching signal falls.
While resetting the column addresses of 6, 27 and 28,
Count up the row address. Therefore, the synchronization signal S and each pixel signal of the image signal K are continuously stored in a predetermined row of the memory from the first address of the row to the predetermined address. Then, when the synchronization signal S and the image signal K are stored in a predetermined row, the next synchronization signal S ′
And the image signal K ′ are stored in the next row. That is, in each row of the memories 26, 27, and 28, a synchronization signal and an image signal corresponding to one horizontal scanning line H are stored.

As described above, in the present embodiment, the horizontal synchronizing signal S included in the input signal is stored as it is and stored in the memory 2.
6, 27, and 28. This horizontal synchronization signal S
Is provided before the image signal with a predetermined accuracy, and the positional relationship between the horizontal synchronizing signal S and the image signal is read from the memories 26, 27, 28, and
It does not change due to processing such as conversion and FM modulation. Therefore, the horizontal synchronizing signal S and the image signal are recorded on the magnetic disk D while maintaining a predetermined positional relationship. Therefore, when an image signal is reproduced from the magnetic disk D, the image signal is reproduced with high accuracy, and there is no possibility that the image will be distorted even if jitter or the like occurs. Further, the sub- sampling is controlled with high precision because the sub- sampling is controlled based on the time from the horizontal synchronization signal S of each pixel signal.

FIGS. 4 and 5 show the operation of subsampling. FIG. 4 is a diagram showing the relationship between subsampling and interpolation. Band of the input image signal in this figure is f _H, the image signal is half of the image by subsampling
The elements are thinned out and stored in the memories 26, 27 and 28.
Hand, upon reproduction of the image signal, the image signal is interpolated by a known method, thereby, decimated image signal is substantially reproduced, the image of the input image equivalent to the image quality can be obtained.

In FIG. 4, for the pixels in the first field, the leftmost pixel on the screen is sampled, the next pixel is thinned out, and so on. . On the other hand, as for the pixels in the second field, the pixels at the leftmost end of the screen are thinned out, the next pixel is sampled, and so on. In this way, the pixels of the input image signal are thinned out uniformly on the screen.

Next, the operation of reading an image signal recorded on a magnetic disk by subsampling from the magnetic disk will be described with reference to FIG. As mentioned above,
When reading from the magnetic disk, the image signal is interpolated. The pixels obtained by this interpolation correspond to the pixels thinned out at the time of sampling (the pixels of the symbol A surrounded by the broken line in the image signal indicated by the symbol L). Accordingly, pixels (reference numeral 33,
The value of this pixel (A) is obtained by averaging the values of the pixels (35, 24, 44). Now, the pixels (33, 35) located on the left and right of the pixel (A) are pixels on the same horizontal scanning line, but the pixels (24, 44) located above and below the pixel (A) are horizontal pixels located above and below, respectively. This is a pixel on the scanning line. That is, the pixels (24, 4
4) is included in a field different from the pixel (33, 35). As described above, since the thinned-out pixels are restored by interpolation, when the image signal recorded on the magnetic disk is reproduced, an image is obtained with substantially the same resolution as the input image signal.

FIG. 6 is a block diagram of a reproduction system of the still video device. The system control circuit 10, the magnetic head 11, the spindle motor 12, and the operation unit 14 are shown in FIG.
Are included in the recording system shown in FIG. 1, that is, they are both a recording system and a reproducing system.

The magnetic head 11 is located on a predetermined track of the magnetic disk D, and reproduces an ID code and an image signal recorded on this track. The reproduction amplifier 41 reads out the image signal and the ID code recorded on the magnetic disk D, and performs a Y reproduction processing circuit 42, a C reproduction processing circuit 43,
Output to the D reproduction processing circuit 44. The Y reproduction processing circuit 42 FM-demodulates the additional synchronization signal X and the luminance signal (Y + S) and outputs them. The C reproduction processing circuit 43 outputs the color difference signals (RY, B
-Y) is FM-demodulated and output. ID reproduction processing circuit 44
Outputs the ID code by DPSK demodulation.

The synchronization signal separation circuit 45 separates the additional synchronization signal X from the signal output from the Y reproduction processing circuit 42. The original synchronization signal separation circuit 74 separates the horizontal synchronization signal S from the luminance signal (Y + S) output from the Y reproduction processing circuit 42. The original synchronization signal separation circuit 75 separates the horizontal synchronization signal S from the color difference signals (RY, BY) output from the C reproduction processing circuit 42. These horizontal synchronization signals S
Is sent to the memory control circuit 46 and the system control circuit 10. Memory control circuit 4
6 controls the A / D converter 47 and the Y memory 51 based on the horizontal synchronization signal S separated from the luminance signal (Y + S), and controls the horizontal synchronization signal S separated from the color difference signals (RY, BY). Converter 44 and C memory 52 based on
Control. In addition, the memory control circuit 46, based on a synchronization signal from a synchronization signal generation circuit 53 described later,
The DA converters 54, 55, 56, the Y memory 51, and the C memory 52 are controlled.

Luminance signal (Y + S) including horizontal synchronizing signal
The luminance signal Y recorded between the two horizontal synchronizing signals is stored in the Y memory 51 under the control of the memory control circuit 46.
The luminance signal Y stored in the Y memory 51 is a synchronization signal (reference clock signal) output from the synchronization signal generation circuit 53.
Is DA-converted by the DA converter 54 based on
Similarly, the color difference signals (RY, BY) are converted by the AD converter 48.
And is stored in the C memory 52. The color difference signals (RY, BY) are alternately output from the C memory 52 based on the reference clock signal, but the color difference signals (RY, BY) of the same horizontal scanning line are output from the memory control. Due to the operation of the circuit 46, the signals are simultaneously output from the synchronizing circuit 57 and input to the D / A converters 55 and 56, respectively.
A conversion is performed.

The reference clock signal has, for example, twice the frequency of the reference clock signal used to record the image signals in the memories 51 and 52. Therefore, the image signal is read out from each of the memories 51 and 52 at a relatively high speed, whereby the time axis is compressed.

Blanking sync mix circuits 61 and 6
Reference numerals 2 and 63 are provided to set a predetermined portion in front of each luminance signal (Y + S) and two color difference signals (RY, BY) to a signal of 0 level and to superimpose a synchronization signal. The blanking sync mix circuits 61 and 6
According to 2, 63, a clean synchronization signal conforming to each system such as HDTV is added before these signals. The signals (Y + S), (RY), and (BY) from the blanking sync mix circuits 61, 62, and 63 are, for example,
For example, in accordance with the HDTV system (for example, HDTV system)
And is directly input to a display device (not shown).

The interpolation processing circuit 64 is a circuit for performing the interpolation processing described with reference to FIG. That is, the interpolation processing circuit 64 calculates the luminance and color difference of the reproduced pixel by interpolation from the luminance and color difference of the pixels located around the pixel to be reproduced.

On the other hand, I stored in the magnetic disk D
The D code is subjected to processing such as DPSK demodulation in the ID reproduction processing circuit 44 and is decoded by the system control circuit 10.

FIG. 7 shows a luminance signal (Y + S) of the image signal.
FIG. 6 is a diagram showing an operation of reproducing and storing the data in a memory 51. The reproduction signal has an image signal K and a synchronization signal S provided in front of the image signal K, and an additional signal added by a synchronization signal generation circuit 34 (FIG. 1) further in front of the synchronization signal S. A synchronization signal X is included. These additional synchronizing signal X, original synchronizing signal S and image signal K repeatedly appear in the reproduced signal.

In order to separate the original synchronization signal from the reproduction signal,
The separation gate signal is output from the synchronization signal separation circuit 45 to the original synchronization signal separation circuit 74. This separation gate signal G is
A pulse signal output when the falling of the additional synchronization signal X has passed a predetermined time tau _4, having a pulse width of the time tau _5. A reproduction signal is input to the original synchronization signal separating circuit 74, and a separation gate signal G is input corresponding to the original synchronization signal S included in the reproduction signal. Therefore, the original synchronization signal S is separated from the reproduction signal and output from the original synchronization signal separation circuit 74. On the other hand, the address switching signal J by the action of the memory control circuit 46 rises in synchronism with the zero-crossing point of the original synchronization signal S, so that the falls after the elapse of a predetermined time tau _6. A predetermined time τ ₇ from the fall of the address switching signal J
During this time, the memory write enable signal M is output from the memory control circuit 46. The time τ ₇ during which the memory write enable signal M is output corresponds to the length of the image signal K,
The image signal K is written to the memory 51 in synchronization with the memory write enable signal M.

When storing the image signal K in the memory 51, the memory control circuit 46 resets the column address of the memory 51 and counts up the row address each time the address switching signal falls. Therefore, each pixel signal of the image signal K is continuously stored in a predetermined row of the memory from a first address of the row to a predetermined address. When this image signal K is stored in a predetermined row, the next image signal K 'is stored in the next row. That is, each row of the memory 51 stores an image signal corresponding to one horizontal scanning line H.

The color difference signals (RY, BY) are stored in the memory 52 in the same manner as the luminance signal (Y + S).

As described above, at the time of reproduction in this embodiment, the horizontal synchronizing signal S included in the input signal is used as a synchronizing signal for storing the image signal in the memories 51 and 52. As described above, the horizontal synchronization signal S is provided before the image signal with a predetermined accuracy in advance, and the positional relationship between the horizontal synchronization signal S and the image signal is determined in the processing up to the reproduction. It does not change. Therefore, the image signal is reproduced with the same precision as that at the time of input, and a high-precision screen is obtained.

Although the image signal is in the frame recording mode in the above embodiment, it goes without saying that the present invention can be applied to the field recording mode. In the above embodiment, the input signal is delayed, and the horizontal synchronization signal S located in front of the image signal K is stored in the memories 26, 27, and 28 together with the image signal K. , The horizontal synchronization signal S ′ behind the image signal K may be stored in the memories 26, 27, and 28 together with the image signal K.

[0039]

As described above, according to the present invention, it is possible to obtain an effect that an image signal can always be sampled accurately during reproduction and a high-quality image can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a recording system of a still video device to which an embodiment of the present invention has been applied.

FIG. 2 is a diagram showing a relationship between an input image signal, an image signal recorded on a memory, and an image signal recorded on a magnetic disk.

FIG. 3 is a diagram illustrating an operation of storing an input image signal in a memory after delaying the input image signal.

FIG. 4 is a diagram illustrating a relationship between sub-sampling of image signals and interpolation.

FIG. 5 is a diagram illustrating an operation of sub-sampling an input image signal and recording the sub-sampled image signal on a magnetic disk, and generating a thinned pixel by interpolation.

FIG. 6 is a block diagram of a reproduction system of a still video device to which an embodiment of the present invention has been applied.

FIG. 7 is a diagram illustrating an operation of storing an image signal included in a reproduction signal in a memory.

[Explanation of symbols]

 71, 72, 73 Delay memory 74, 75 Original synchronization signal separation circuit D Magnetic disk (recording medium) K Image signal S Horizontal synchronization signal (first synchronization signal) X Additional synchronization signal (second synchronization signal)

Claims (2)

(57) [Claims] An input for storing an input signal including a first synchronization signal and an image signal in a memory based on the first synchronization signal.
Force signal storage means and a second synchronizing signal generating means for generating a second synchronizing signal.
Using the synchronization signal generating means and the second synchronization signal.
Means for reading an input signal from the memory;
Means for adding a signal immediately before an input signal;
And a unit for recording the second synchronization signal on a recording medium . 2. A recording medium in which an input signal including a first synchronization signal and an image signal is stored together with a second synchronization signal,
The image signal, means for reproducing the first and second synchronization signals, from said signal reproduced by the reproducing means first
Second synchronization signal separating means for separating the second synchronization signal;
Means for separating the first synchronization signal based on the obtained second synchronization signal, and means for separating the first synchronization signal based on the first synchronization signal.
Means for storing the image signal in a memory;
A reproduction processing means for performing predetermined reproduction processing on the image signal as a reference signal, a third synchronization signal for generating a third synchronizing signal
Signal generating means and the memo based on the third synchronization signal.
And a means for reading the image signal from the memory .