JPH0357384A - Picture signal reproducing device - Google Patents

Abstract

PURPOSE:To accurately reproduce a picture signal by controlling the storage of a picture signal based on a clock signal phase-locked to a reproduced pilot signal and a phase reference signal detected from the reproduced picture signal. CONSTITUTION:A BPF 16 extracts a reproduced pilot signal from a reproduction signal and a PLL circuit 18 forms a clock signal phase-locked to the reproduced pilot signal. On the other hand, a comparator 20 is controlled for 1H period with an LPF 14a and a synchronizing separator circuit 17 or the like, a luminance signal from an A/D converter circuit 15a is compared with a reference level, a phase reference signal is detected from the reproduced picture signal and a clock signal is retarded so as to synchronize with the phase reference signal via a variable delay circuit 19 for the signal period. A write timing of the reproduced picture signal into the picture memory 23 is controlled via A/D converters 15a, 15b and address converters 22a, 22b to read the content of the memory 23 and the result is subject to interpolation processing to accurately decode the picture signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal reproducing device for reproducing image signals recorded on a recording medium.

[Conventional technology]

Conventionally, there is a still video (hereinafter referred to as Sv) system as a recording and reproducing device for still image signals.

This Sv system records the current TV signal on a 2-inch magnetic disk by FM modulating it. The image resolution achieved by this system is only comparable to that of the current TV system. However, in systems that handle still images, such as the Sv system, the final output may be printed out by a printer, and in that case, the problem is that the image quality (especially resolution) is lower than that of silver halide photography. There is.

On the other hand, recently HDTV (High Definition)
New TV systems such as tionTV) are being considered.
Among these, the HDTV system has approximately 1,000 scanning lines, which is approximately twice as many as the current NTSC system, and has a corresponding horizontal signal band. Therefore, even in the Sv system, the IOOO that can be obtained with HDTV etc.
XIOOO pixels (when a square screen is extracted)
It has become essential to develop a still image recording and reproducing system with a certain level of image quality.

In view of this situation, the Sv system has changed the recording format for the recording medium to a high band (wideband).
are doing. However, when viewed as an Sv system, high image quality must be achieved while maintaining compatibility with conventional systems to some extent.

Therefore, as a method for achieving high image quality while maintaining compatibility with conventional systems, the applicant proposed the CHSv system (CHSv system)
Compatible High Definity
on SV).

An outline of the CHSV method will be described below.

First, a method for recording a luminance (Y) signal based on the CHSV method will be described. FIG. 5 shows sample points of the Y signal recorded based on the CHSV method. The sample points of the Y signal are subsampled, for example, at a sampling period Ts so as to be offset as shown in the figure. 650 sample points in one row (1300/2)
, and there are 500 (1000/2) in one line. Then, the sample values included in the line AI+A2+... in the figure are stored in one track on the magnetic disk.
All sample values are recorded using a total of four tracks, such that the sample values included in the lines B2+, . . . are recorded on another track, and so on. Furthermore, recording is performed on each track in accordance with the format of the conventional Sv system.

Next, the reproduction method will be described. FIG. 6 shows a schematic configuration of a playback device based on the CHSV method. A signal reproduced by a magnetic head 1502 from a magnetic disk 1501, which is a recording medium, is amplified by a reproduction amplifier 1503 and then input to an SV reproduction process circuit 1504. Here, separation of luminance signal Y and color difference line sequential signal C, FM demodulation,
De-emphasis and the like are performed, and a reproduced Y signal and a reproduced C signal are output. Then, those two signals are γ-inverse transformed in a γ-inverter l506 or 1507, and the LPF
After being band-limited at 1508 or 1509, the signal is input to the image memory via an analog-to-digital (A/D) converter 1513 or 15l4, respectively. This A/
The sampling clocks in the D converters 1513 and 1514 are obtained by extracting a pilot signal that has been frequency multiplexed in advance from the signal reproduced from the magnetic disk 1501 using a band pass filter (BPF) 1505 during recording, and extracting the pilot signal from the signal reproduced from the magnetic disk 1501 using a band pass filter (BPF) 1505. The sampling clock generation circuit 1511. 1512.

The above process is performed on the four tracks on the magnetic disk 1501, and the A/D converters 1513 and 1514
The sample data output from the address generator 151
7. Image memory l515 specified by 1518
It will be stored at the above address. And image memory 15l
The image processing circuit 1 uses the sample data stored in 5.
After performing interpolation processing etc. using 516, the high components of the Y signal (
Y}I), low frequency component of Y signal (YL), color difference signal (CR
ICB), YCR and C8 are supplied to the matrix circuit 1519 as shown in the figure, and after being converted into three primary color signals (RLI GLI BL), the Takagi component (YH) of the Y signal is added to the adder. 1520, 1521.
1522 and digital/analog (D/
A) It is converted into an analog signal by converters 1523, 1524, and 1525, and output as an RGB signal.

The reproduction process has been described above. Next, analog transmission of sample values performed in the CHSV method will be described.

FIG. 7 shows a conceptual diagram of a CHSV transmission system.

As shown in the figure, the input analog signal is sampled at a period T. Then, the sample value is band-limited, FM modulated, and recorded on a magnetic disk.

Then, the signal reproduced from the magnetic disk is FM demodulated, band-limited, resampled, and a sample value signal as shown in FIG. 7 is output.

In this analog transmission of sample values, it is a very important factor that the time axis of the sampling pulse is transmitted without fluctuation. FIG. 8 shows an explanatory diagram illustrating the importance of the time axis of the sampling pulse. Consider a case where a sample value sequence obtained by sampling with a period T is recorded and reproduced, as shown in FIG. 2(a). The transmission line consisting of the FM modulation/demodulation and electromagnetic conversion system exhibits LPF characteristics, and the transmission line output signal is as shown in FIG. 2(b). The period of this signal is T, which is the same as the sampling pulse at the time of input as shown in the same figure (C),
In addition, if the sample is regenerated using a sampling pulse with the correct phase, as shown in (d) in the same figure, if the phase is shifted like the original input sample, a sequence of sample values as shown in (f) in the same figure will be output, and the sequence will be correct. No playback occurs and ringing occurs. Furthermore, it goes without saying that even if the sampling period is different, the data will not be played back correctly.

Therefore, during reproduction, a resampling pulse with the correct frequency (period) and correct phase is required. There is also one more condition for completely transmitting sample values. This means that the transmission path characteristics are linear phase (flat group delay), and the amplitude characteristics are symmetrical roll-off characteristics centered on the frequency f s (= 1/2T). The characteristics shown in the figure are required.

[Problem to be solved by the invention] In the case of the CHSV method using sample value analog transmission as described above, in order to generate a correct reproduced sampling clock, a sampling clock that is phase-synchronized with the pilot signal reproduced from the magnetic disk is required. The TBC circuit is designed to absorb jitter that occurs during playback by sampling the FM-modulated image signal reproduced using the FM-modulated image signal and demodulating the sampled FM-modulated image signal and storing it in the memory according to the sampling clock. A sampling clock is formed in the Time Base Corrector, and by using this sampling clock, jitter that occurs during playback is absorbed, and when the sampled FM modulated image signal is demodulated and stored in memory. It is configured to reset the horizontal address of the image signal storage memory in synchronization with the horizontal synchronization signal and vertical synchronization signal added to the demodulated image signal.

By the way, when configured in this way, for example, Fig. 10 (
As shown in a), if waveform distortion occurs in the synchronization signal part of the image signal after demodulation, or if the SN is poor, even if the waveform of this part is shaped, the waveform will not be as shown in Figure 10 (b). The time axis of the edge part of is disturbed, and if the horizontal address of the image signal storage memory is reset at the timing of the edge part of the synchronization signal, the image signal will be stored at a different address than when the memory is normal. Even if the image signal stored in the memory is read in this way using an accurate readout clock signal, the address at the time of writing is shifted, so the restored image will also be shifted, and the original image cannot be accurately reproduced. It will not be possible to restore it.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal reproducing device that can solve the above-mentioned problems and accurately restore an original image signal from a signal recorded on a recording medium.

[Means to solve the problem]

The image signal reproducing device of the present invention is a device for reproducing an image signal from a recording medium in which a pilot signal is frequency-multiplexed and recorded on an image signal to which a phase reference signal serving as a phase reference is added, and the image signal is reproduced from the recording medium. storage means for storing the reproduced image signal reproduced from the recording medium; clock signal generating means for forming a clock signal phase-synchronized with the reproduced pilot signal reproduced from the recording medium; A phase reference signal detecting means for detecting and outputting a signal, a clock signal formed in the clock signal generating means, and a phase reference signal detected in the phase reference signal detection, controlling a storage operation in the storage means. The invention also includes a control means for controlling.

[For production]

With the above configuration, it becomes possible to accurately restore the original image signal from the signal recorded on the recording medium.

〔Example〕

Hereinafter, the present invention will be explained using one embodiment of the present invention.

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention in which the present invention is applied to a recording and reproducing apparatus for an electronic still video system based on the CHSV system.

In FIG. 1, an image signal input from an image signal input terminal l is converted into a luminance (Y) signal and a color difference line sequential (C) signal in a recording signal processing circuit 2. And this Y signal,
A phase reference signal as shown in FIG. 2 is added to the two C signals by phase reference signal adding circuits 3a and 3b. This phase reference signal is added to the beginning of the video signal immediately after the back-up of the synchronization signal section, and the center point of the phase reference signal, that is, point a in FIG. , the position to be added is determined to be a point at which a predetermined sampling interval has elapsed. Furthermore, in the case of a C signal without a synchronization signal section, it is added at the same timing as the Y signal. After the Y and C signals to which the phase reference signal has been added in this way are FM modulated by FM modulators 4a and 4b,
Frequency multiplexing is performed by an adder 5, continuous pilot signals are added by a pilot signal adding circuit 6, and are recorded by a magnetic head 8 onto a magnetic disk 9 which is being rotated by a motor 10 at a predetermined number of rotations. At this time, the recording/playback selector switch 7 is set on the recording side (
(a side) in the figure.

At the time of reproduction, the recording/reproduction selector switch 7 is connected to the reproduction side (side b in the figure) according to instructions from a system controller (not shown), and the signal reproduced from the magnetic disk 7 by the magnetic head 8 is amplified by the reproduction amplifier 11. Thereafter, it is input to the SV reproduction process circuit 12. Here, the luminance signal Y
Separation of the signal from the color difference line sequential signal C, FM demodulation, de-emphasis, etc. are performed, and a reproduced Y signal and a reproduced C signal are output. And those two are γ inverse transformers 13a or 13
After being subjected to γ inverse conversion in b and band-limited by LPF 14a or 14b, analog and digital (A
/D) Digitized by converter 15a or 15b and supplied to image memory 23. The clock signals in the A/D converters 15a and 15b are generated by extracting a frequency-multiplexed pilot signal from the reproduced signal reproduced from the magnetic disk 9 using a bandpass filter (BPF) 16 during recording, and synchronizing it with the pilot signal. This is a clock signal formed using the synchronization signal separated in synchronization by the separation circuit 17.

The operation of forming clock signals of the A/D converters 15a and 15b will be described below. The BPF 16 is supplied with the reproduction signal amplified by the reproduction amplifier 11, and the BPF 16 separates the pilot signal that was frequency multiplexed during recording from the supplied reproduction signal.
se Locked Loop) circuit 18.

The PLL circuit 18 generates a clock signal phase-synchronized with the supplied pilot signal, and supplies it to the variable delay circuit 9.

By the way, in this embodiment, the phase reference signal added during recording and the clock signal output from the PLL circuit 18 are used so that the sampling position performed during recording and the resampling position performed during playback accurately match. It is configured to match the phase with the variable delay circuit 19.

The phase control operation of the clock signal output by the PLL circuit 18 will be described below with reference to FIG.

First, the variable delay circuit 19 receives the clock signal from the A/D converter 15a without delaying the clock signal supplied from the PLL circuit 18.
, 15b, and the A/D:I inverter 15a digitizes the Y signal supplied from the LPF 14a based on the supplied clock signal and supplies it to the comparator 20.

Further, the comparator 20 is provided with an L signal by the synchronizing signal separation circuit 17.
A horizontal synchronizing signal H separated from the Y signal output from the PF 14a is supplied, and the comparator 20 performs a signal (not shown) during a predetermined period defined by the supplied horizontal synchronizing signal, that is, a period including the phase reference signal. The reference level signal supplied from the reference level signal generator and the digitalized Y signal are compared in level, and if a digital Y signal indicating a level higher than the reference level indicated by the reference level signal is detected, a detection pulse is generated. Output.

As shown in FIG. 3, among the sample points (A-C in the figure) of the digital Y signal output from the A/D converter 15a, the sample points ( The comparator 20 outputs a detection pulse as shown in the figure in synchronization with the timing at which the digital Y signal A) in the figure is output from the A/D converter 15a.

On the other hand, the digital Y signal output from the A/D converter 15a is also supplied to a phase control signal generation circuit 21, and the phase control signal generation circuit 21 outputs a signal in synchronization with the supply of the detection pulse from the comparator 20. Digital Y signals corresponding to sampling points A, B, and C shown in Figure 3 are detected, and (A-B) - (A-C) (A, B, and C indicate the level of each sampling point in Figure 3). ) is performed, and a control signal corresponding to the result of the calculation is supplied to the variable delay circuit 19.

The variable delay circuit 19 controls the amount of delay of the clock signal according to the control signal supplied from the phase control signal generation circuit 21, so that the center point of the phase reference signal, that is, the level peak point, and the sample point by the clock signal are As shown in Figure 4
Control so that they match.

As described above, the clock signal whose phase is matched with the phase reference signal added at the time of recording is transferred to the A/D converter 15a.
, 15b, write address generators 22a, 22b
is supplied to

The A/D converters 15a and 15b output the L signal based on the clock signal whose phase has been corrected in the variable delay circuit 19.
Reproduction Y signal and reproduction C supplied from PF14a and 14b
The signal is digitized and supplied to image memory 23.

In addition, the write address generators 22a and 22b send the digital Y signal and digital C signal output from the A/D converters 15a and 15b to the image memory 23 in synchronization with the clock signal whose phase has been corrected in the variable delay circuit l9. The write address for writing is specified to the image memory 23. The write address generator 22a outputs the write address data of the digital Y signal, and the write address generator 22b outputs the write address data of the digital C signal.
Outputs signal write address data.

Note that the write address generators 22a and 22b are supplied with the detection pulses generated by the comparator 20, and the synchronization signal separation circuit 17 is supplied with the vertical synchronization signal V separated from the reproduced Y signal output from the LPF 14a. As described above, the write address generators 22a and 22b have a horizontal address counter and a vertical address counter that are counted up in synchronization with the clock signal, and the comparator 2
The horizontal address counter is reset by the detection pulse supplied from 0, and the vertical address counter is reset by the vertical synchronization signal supplied from the synchronization signal separation circuit 17.

In addition, the memory controller 2 controls the start and end of data writing or reading operations in the image memory 23.
4. By the way, while the delay amount of the variable delay circuit 19 is controlled by the control signal generated by the phase control signal generation circuit 2l and the phase of the clock signal is being corrected, the phase control signal generation circuit 2l
outputs a write prohibition instruction signal to the memory controller 24, and the memory controller 24 prohibits the data write operation of the image memory 23 while the write prohibition instruction signal is output from the phase control signal generation circuit 21. When the write inhibit instruction signal is no longer output from the phase control signal generation circuit 21, that is, when the phase correction of the clock signal is completed, the memory controller 24 puts the image memory 23 into the data writing state, and the A/D converter 15a , 15b are written to addresses on the image memory 23 designated by write address generators 22a, 22b.

When the above-described playback operation of the magnetic disk 9 and writing operation to the image memory 23 are completed for the four tracks on the magnetic disk 9, the interpolation circuit 25 reads the magnetic disk 9 stored in the image memory 23. Using the image data corresponding to the recorded image signal, interpolated image data corresponding to the image signal not recorded on the magnetic disk 9 is formed, and the formed interpolated image data is stored in the image memory 23.

When storage of the image data and interpolated image data in the image memory 23 is completed as described above, the memory controller 2
4 sets the image memory 23 in a read state, and based on the accurate clock signal with no time axis fluctuation outputted from the clock signal generator 26, the read address generator 27a,
27b specifies the read address on the image memory 23, and reads the image data stored in the image memory 23 by Y.
Takagi component of the signal (YH), low frequency component of the Y signal (YL),
The two types of color difference signals (CR.Ca) are read out in a state where they are separated, and YL+CR+ca is supplied to the matrix circuit 28, where the signal is
After being converted into three primary color signals (RL, Gt...BL), YH read out from the image memory 23 is added to the RL+GL+BL in adders 29a, 29b, and 29c, and the signal is converted into digital/analog (D/A). :I inverter 30a
, 30b, 30c, the analog three primary color signals (
R, G, B) and further LPF31a, 3lb
, 31c, and then output from output terminals 32a, 32b, and 32c.

As explained above, in this embodiment, the image signal reproduced from the magnetic disk is temporarily stored in the memory in synchronization with a clock signal that includes time axis fluctuations that occur during reproduction, and then stored on the magnetic disk. An image signal for one screen that is divided and recorded into four tracks is reconstructed on the memory, and the image signal is stored in the memory in synchronization with an accurate clock signal with no time axis fluctuation. By reading the , the pilot signal recorded on the magnetic disk along with the image signal is separated from the reproduced signal, and phase synchronization is performed with the separated pilot signal when removing time axis fluctuations occurring in the reproduced image signal during reproduction. The clock signal is then phase-corrected using a phase reference signal that is also added to the image signal during recording, and the write address setting for the memory is performed using a horizontal synchronization signal separated from the reproduced image signal. Instead, it is performed in synchronization with the reproduction timing of the phase reference signal recorded on the magnetic disk that is added to the image signal during recording, and the reproduced image signal is stored in the memory in synchronization with the phase-corrected clock signal. Therefore, it becomes possible to accurately restore the image signal recorded on the magnetic disk as an image signal without time axis fluctuation.

In this embodiment, a modified signal as shown in FIG. 2 was used as the phase reference signal, but similar effects can be obtained by using waveform signals of other shapes.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an image signal reproducing device that can accurately restore the original image signal from the signal recorded on the recording medium. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention in which the present invention is applied to a recording and reproducing apparatus for an electronic still video system based on the CHSV system. FIG. 2 is a diagram showing the waveform of an image signal to which a phase reference signal is added. FIG. 3 is a diagram showing a state in which the phases of the phase reference signal and the sampling points based on the clock signal are shifted. FIG. 4 is a diagram showing a state in which the phases of the phase reference signal and the sampling point based on the clock signal match. FIG. 5 is a diagram showing the sample point arrangement of a luminance signal in the CHSV method. FIG. 6 is a diagram showing a schematic configuration of a playback device for an electronic still video system based on the CHSV method. FIG. 7 is a diagram showing a system for analog transmission of sample values. FIG. 8 is a diagram showing the relationship between the sampling clock and the output signal. FIG. 9 is a diagram showing low-pass filter characteristics exhibited by a transmission line for analog transmission of sample values. FIG. 10 is a diagram for explaining the waveform deterioration of the horizontal synchronizing signal that occurs during reproduction. 3a, 3b... Phase reference signal addition circuit, 6... Pilot signal addition circuit, 9... Magnetic disk, 15a
, 15b...A/D converter, 18...PL
L circuit, 19... variable delay circuit, 20... comparator,
2l... Phase control signal generation circuit, 22a, 22b...
・Write address generator, 23...image memory, 2
4...Memory controller, 26...Clock signal generator, 27a, 27b...Read address generator. Figure 70 of δ area (α) <b)

Claims (1)

[Scope of Claims] An apparatus for reproducing an image signal from a recording medium in which a pilot signal is frequency-multiplexed and recorded on an image signal loaded with a phase reference signal serving as a phase reference, the reproduction being reproduced from the recording medium. storage means for storing an image signal; clock signal generation means for forming a clock signal phase-synchronized with a reproduced pilot signal reproduced from the recording medium; and detecting a phase reference signal from the reproduced image signal reproduced from the recording medium. and outputting a phase reference signal detection means; control for controlling storage operation in the storage means according to the clock signal formed by the clock signal generation means and the phase reference signal detected by the phase reference signal detection means; An image signal reproducing device comprising: means.