JPH02177793A - Image signal recorder - Google Patents

Abstract

PURPOSE:To perform phase adjustment with high definition by using an attached phase reference signal on a luminance signal and a chrominance signal, respectively, at the time of performing reproduction by attaching the optimum phase reference signal on each of the luminance signal and the chrominance signal. CONSTITUTION:The re-sampling phase reference point Rc of a C signal is attached on a position earlier in point of time by the integer times of (1/fN1) the re-sampling phase reference point of a Y signal. Also, relation between the length LY and Lc of phase reference signals is set as LY<=Lc. The inclination of the oblique part of the phase reference signal to be attached on the Y signal can be increased without decreasing the variable range of allowable time added further on the prescribed time difference between a reproducing Y signal and a reproducing C signal by setting the length of a re-sampling phase reference signal for C signal longer than that of the re-sampling phase reference signal for Y signal. Also, the length of the phase reference signal can be reduced, and the required recording band area of the luminance signal can be lowered, and also, a phase error detecting gain for a phase control signal at the time of performing the reproduction can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image signal recording device that records an image signal composed of a luminance signal and a color signal on a recording medium.

[Prior Art] Conventionally, there is a still video (hereinafter referred to as Sv) system as a recording and reproducing device for still image signals. This Sv system converts current TV signals into FM 2-inch magnetic disks.
It modulates and records. The image resolution achieved by this system is only comparable to that of current TV systems. However, in systems that handle still images, such as the Sv system, the final output may be printed out by a printer. In this case, the problem is that the image quality (especially resolution) is lower than that of silver halide photography.

On the other hand, recently HD TV (High Definition)
New TV systems are being considered, such as HDTV, which has about 1,000 scanning lines, which is about twice the number of the current NTSC system, and a corresponding horizontal signal band. is appeased. Therefore, S
Even in the v system, the 10
It has become essential to develop a still image recording and reproducing system with an image quality of about 00x 1000 pixels (when a square screen is taken out).

In view of this situation, the SV system has adopted a high-band recording format for the recording medium (broadband). However, when viewed as an SV system, while maintaining compatibility with conventional systems to a certain extent, We must aim for higher image quality.

Therefore, the applicant proposed the CH5V system (C
Compatible High Definition
SV) can be considered.

An outline of the CHSV method will be described below.

The CHSV method uses a technique called analog transmission of sample values.

The system for analog transmission of sample values is shown in Figure 2 (a).
It is characterized by transmission path characteristics (LPF characteristics) and resampling as shown in FIG. That is, after the input sample value passes through the FM modulation system, electromagnetic conversion system, and FM demodulation system,
This is a system that is restored by being resampled.

The principle of analog transmission of sample values will be discussed a little more with reference to FIG. 3. Here, we will consider the case where a sample value sequence with a period T as shown in FIG. 3(a) is recorded and reproduced. The transmission path consisting of the FM modulation/demodulation and electromagnetic conversion system has low-pass characteristics, that is, low-pass filter (LPF) characteristics. FIG. 3(b) shows the output of this transmission line. Therefore, this transmission line output has a period T as shown in Fig. 3(C).
When resampling is performed with a resampling pulse having the correct phase, the result shown in FIG. 3(d) is obtained. That is, the input sample value sequence is correctly reproduced (transmitted), but as shown in FIG.
If the resampling phase is shifted as shown in e), the sample value sequence will not be reproduced (transmitted) correctly, and ringing will occur as shown in Figure 3 (f). Therefore, in analog transmission of sample values, when reproducing On the (receiving side), ■ Generate a resampling pulse with the correct frequency (period) that follows the reproduced (received) sample value signal ■ Generate a resampled pulse with the correct phase that follows the reproduced (received) sample value signal This is necessary.

There is also one more condition for completely transmitting the sample value signal. this is.

(2) The transmission line consisting of the FM modulation/demodulation and electromagnetic conversion system has a linear phase, and the frequency characteristic is a symmetric roll-off characteristic centered around the sampling frequency r (, 18?).

That is, it is necessary for the transmission line to have LPF characteristics as shown in FIG. The analog transmission of sample values has been briefly explained above.

Next, a method for recording a luminance (Y) signal based on the CHSV method will be described.

FIG. 5 is a diagram showing sample points of a Y signal recorded on a magnetic disk in the CHSV method. As shown in FIG. 5, the sample points of the Y signal are offset and transmitted by subsampling. Furthermore, there are 650 sample points (-1300/2) in one column and 500 sample points (-1000/2) in one row. Then, the sample values included in A , , A , , , , , are stored in one track on the magnetic disk as B, , B , , .
The sample values included in , , , , , etc. are recorded on another track, and so on, all sample points are recorded using a total of four tracks.

All sample points on each track are recorded using S■
It is formed according to the format.

Figure 8 shows the frequency allocation of the recording signal in the Sv format.As shown in Figure 8, the baseband bands of the Y signal and C signal recorded in the Sv format are 7 MH and below, and IMH and below, respectively. Become.

Further, in FIG. 5, the number of Y signal sample points included in each row is 650, and these are recorded in the horizontal effective screen period (53 μsec or less) of the NTSC-TV signal. Therefore, the sampling frequency f (see Fig. 4) at this time is set to 0 or more, which is less than 6.1M islands, and the fourth
A Y signal having a band as shown in the figure is recorded.

Further, FIG. 6 shows two types of recording patterns on a magnetic disk recorded based on the CHSV method. Figure 6 (a
) is the recording pattern when a 2-channel (ah) head is used, and FIG. 6(b) is the recording pattern when a 4-channel head is used (However, if a 4-channel head is used, the recording pattern shown in FIG. 6(a) is (b) is also possible).

In the case of FIG. 6(a), first, for the first and second tracks,
Sample values of the signal are recorded simultaneously on 2 channels using a 2 channel head, and then the 2 channels are recorded at 1 m3. '1 rack (however, it is not necessary to move if a 4ch head is used), and record the sample values of the Y signal of the D1 row + Ci row on 2ch simultaneously. At this time, as shown in the figure, the Di line is inserted to maintain compatibility with the conventional sv format.

C! The track on which the sample value of the Y signal of the row is recorded is reversed.

In addition, when recording on 2 channels at the same time, there is a problem of crosstalk between recording signals within the heads that occurs when recording on a boat, but by using the recording method described above, it is possible to record signals on two channels simultaneously. Since the well-known H arrangement is performed between the two, this problem is solved.

In addition, when a 4ch head is used, recording as shown in FIG. Record at the same time and then 2.4) for the rack,
The sample values of the Y signals in the c1 row and the D1 row are recorded simultaneously for 2 channels.

By recording as described above, in the case of FIG. 6(a), frame playback based on the conventional Sv format becomes possible using the second and third tracks, and in the case of FIG. 6(b)
In this case, it is possible to reproduce frames based on the conventional sv format using the 1.2 tracks or the 3.4 tracks.

The method for recording the Y signal in the CHSV method has been described above.

Next(, mCHSVCHSV method color difference 1a, Jlj[Next(
C) Describe signal recording.

FIG. 7 shows the Y signal, C, t (=RY) signal, and C, (
=B-Y) shows the recording sample pattern relationship of the signal. In the conventional SV format, the recording band of the color difference signal is approximately one-sixth of the Y signal.

Further, the color difference signals are line-sequentially recorded.

Therefore, the color difference signal CR recorded in the CHSV method
The sample patterns of C1 and C1 are shown in Fig. 7(b) and (C).
It becomes as shown in . Also, on the right side of FIG. 7(b) and (C), Y recorded on the same track on the magnetic disk is shown.
The signal line is A.

There are places where the corresponding Y signal lines and C signal lines, indicated by symbols Bi, Cl, and D+, are not the same line, but this is also a result of consideration of compatibility with Sv.

FIG. 10 shows the recording positional relationship of the Y signal and C signal in a table. Here, 1st 5step means “2nd step to be performed for the first time”.
Similarly, 2nd 5tep refers to "the second 2ch simultaneous recording".As mentioned above, in 2st 5tep, track 1.
Track 3.4 is recorded at 2nd 5tep.
For example, in Figure 1O, track 1 is recorded for 1 s.
At t 5tep, Y(A+) (A shown in Figure 7)
Y signal consisting of a sequence of Y sample values on Muramono) and Cl
1l(AI)/C! I(B i) (A shown in Figure 7)
, a CII signal consisting of a CR sample value sequence on the B+ line, and a C8 signal consisting of a C sample value on the B+ line, and a color difference line sequential signal starting from the C8 signal is recorded. Moreover, in FIG. 1O, the imaging unit outputs (y r , y t , R.

B) is a signal simultaneously output from an imaging unit in a CHSV camera to be described later.

Next, the configuration of a CHSV camera (a device composed of an imaging section and a recording section) will be described.

FIG. 9 is a diagram showing a schematic configuration of the CHS V camera.

In the CH5V camera shown in FIG. 9, as mentioned above, the 2c
h The 1st 5step shown in Fig. 10 records the image recording signal for one screen by performing simultaneous recording twice in a row.
In the Sv recording process circuit 826,827,
After subjecting the input Y signal and C signal to predetermined emphasis, FM modulation, etc., they are output as frequency-multiplexed signals. In adders 828 and 829,
The TBC (Time Ba5e Correc
The clock signal generated by the clock generator 813 is passed through a band pass filter (BPF) as a reference signal for
) 825 (frequency 2.5 MH, around 2.5 MH
H2 is the gap between FM-Y and FM-C)) is added. Then, the signals output from the adders 828 and 829 are amplified by the recording amplifiers 830 and 831, and the 2ch
Two channels are simultaneously recorded onto predetermined tracks of a magnetic disk 834 by heads 832 and 833. And 2n
In d5tep, after the 2ch heads 832 and 833 are moved, the recording operation is performed in the same manner as in the above-mentioned 1st 5step.

Next, the imaging unit 801 in FIG. 9 will be explained.

FIG. 12 is a diagram showing a row of color filters used in a solid-state image sensor when the image sensor 801 is configured with one solid-state image sensor. As shown in FIG. 12, the color filter is composed of a Y (luminance) filter arranged in a checkerboard pattern, and an R filter and a B filter whose remaining filters are arranged line-sequentially.

Further, FIG. 13 is a diagram showing an example of the configuration of an imaging section 801 including a solid-state image sensor having a color filter configured as shown in FIG. 12.

In FIG. 13, 1301 is a solid-state image sensor having the color filter shown in FIG. 12, and 1302 to 1305 are sample and hold circuits, respectively. Solid-state image sensor 13
01 is an image sensor having a pixel count of approximately 1300 (pixels) x 1000 (pixels) and configured to be able to read out signals for two vertically adjacent lines simultaneously and every two lines.

In Fig. 13, the signal line (0-1) contains the Y signal (y+) of the upper line of the two lines of signals read out simultaneously.
is output. Also, the lower line Y@ (Y2) is on the signal line (〇-3), the R@ is on the signal line (0-2), and the B signal is on the signal line (0-4). Output.

And in sample hold circuits 1302 to 1305,
These signals are sampled and held at predetermined timing and output.

Figure 14 shows the signals for two adjacent lines simultaneously as described above.
FIG. 7 is a diagram showing a specific example of a case where the solid-state image sensor capable of reading data every two lines is configured with a MOS solid-state image sensor.

The MOS type solid-state image sensor shown in FIG. 14 is TSL: Tran
This is a generally well-known method.

The MOS type solid-state image sensor as shown in Fig. 14 has a CH5V
In this method as well, since the signals are read out in horizontal order, there is an effect of suppressing smear and the like.

Further, since the signal readout of the MOS type solid-state image pickup device uses the X-Y address method, simultaneous readout of two lines as described above is possible. Further, a detailed explanation of this read operation will be omitted.

Next, in FIG. 9, Y
Y2. R and B signals are Sv recording process circuit 826.82
The signal processing up to input to 7 will be described separately for the Y signal and the C signal.

First, regarding the Y signal, the Yl, Y, and signals output from the imaging unit 801 (as described above for y+ and Y2, see FIG. 1O) are connected to the respective adders 814,
The 0 phase reference signal to which the phase reference signal output from the phase reference signal generator 818 is added at step 816 serves as a phase reference for the resampling operation during playback, which will be described later.
8 (H is horizontal synchronization period) and 1v (
A case may be considered in which one recess is inserted every (vertical synchronization period). FIG. 11 shows the case where the phase reference signal is inserted one time for each MH. As shown in FIG. 11, the phase reference signal is a ternary signal, and R in the figure is the phase reference point.

The Y r and Y signals to which the phase reference signals have been added in adders 814 and 816 pass through LPFs 802 and 805, each having a pass frequency band of 6 MH, and pass through gamma correction circuits (γy) 821 and 823, and then Sv It is input to recording process circuits 826 and 827.

Note that γ, t 821 and 823 are transmission line γ correction circuits, which are used for the purpose of improving the S/N in dark areas of the luminance signal and maintaining compatibility with the conventional Sv format. It will be done.

Next, regarding the C signal, the R and B signals obtained from the imaging unit 801 (R and H are as described above.
(see Figure 0) pass through LPFs 804 and 807, each having a pass frequency band of IMH2, and then switch circuits s,
, S2. The switch circuits S, , S2 operate to switch for each MH, and obtain color line sequential signals R/B (output of S) and B/R (output of S2).

The subtracters 809 and 810 extract the LP having a pass frequency band of I MHz from the output signals from these S, , S.
Yl signal output from F803.

lM)1. The Y2 signal output from the LPF 806 having a pass frequency band of is subtracted, and the color difference line sequential signals C, /
C, is the color difference line sequential signal Ca/CM from the subtracter 809.
is output from subtractor 810.

Next, sample and hold circuits 811 and 812 sample the CR and Ca sample patterns shown in FIG. 7, and supply them to adders 815 and 817. This sampling clock is generated by the clock generator 8
Supplied from 13.

Then, in adders 815 and 817, a phase reference signal is added in the same way as the Y signal (however, the phase reference point of the C signal does not have to be at the same position as the phase reference point of the Y signal).

The signals output from the adders 815 and 817 are sent to the LPF 81.
9,820 and gamma correction circuit (γC) 822.824
The signal is then input to the SV recording process circuit 826 and 827.

Next, the configuration of the CHSV reproducing device will be described.

FIG. 15 is a diagram showing the configuration of the CHSV playback device.

A signal reproduced from the magnetic disk 1501 by the magnetic head 1502 is input to both the S■ reproduction process circuit 1504 and the B P F 1505 via the preamplifier 1503 .

The Sv reproduction process circuit 1504 separates the frequencies of FM-Y and FM-C (see FIG. 8) from the input reproduction signal, and performs FM demodulation, de-emphasis, etc. on each of them, thereby reproducing Y and C. Output a signal.

Next-stage inverse gamma correction circuit (γ,!-') 1506. (γ
c-1) 1507 indicates the transmission path γ7. γ
This is a circuit for returning the C-corrected signal to the original signal. And the γ, 1506. The Y signal corrected by γc1507 and passed through LPF 1508.1509 is sent to the A/D converter 1513, and the C signal is sent to the variable delay circuit 15.
28.

Next, a method of generating a resampling clock during playback will be described.

The reproduction TBC reference signal separated from the reproduction signal by BPF 1505 is PLL (Phase
LockedLoop) circuit 1526.

In the PLL circuit 1526, a clock f is synchronized in phase with the signal f and has a frequency equal to the Y signal resampling clock.

is generated and output.

Y signal resampling clock phase control circuit 1511
Then, the resampling clock f, obtained in this way. , and outputs a Y signal resampling clock f□ whose phase is in a constant relationship with the phase reference point of the aforementioned Y signal sampling phase reference signal added to the reproduced Y signal.

On the other hand, for the C@ number, the fl11 is divided into 18 by 1
The clock whose frequency is divided by 18 by 527 ((f, I/6) is used as the resampling clock (however, the frequency divider 2 is
213 is reset at the falling edge of the synchronization signal), and the delay is controlled by a variable delay circuit 1528 controlled by a C signal delay control signal generation circuit 1529, which is the C signal output from the LPF 1509. Sampling clock for C signal (f□/6)
After the phase relationship between the C signal and the resampling phase reference point added to the C signal is made constant, the C signal is supplied to the A/D converter 1514.

The configurations of the PLL circuit 1526, Y signal sampling clock phase control circuit 1511, and C signal delay control signal generation circuit 1529 described above will be described in detail below.

FIG. 16 is a diagram showing the configuration of the PLL circuit 1526.

The input reproduction TBC reference signal is input to the phase comparator 1.
At 601, the phase is compared with a signal obtained by frequency-dividing the clock output of a VCO (voltage controlled oscillator) 1604 to '' by an 18 frequency divider 1603. The BPF 1608 is a filter for extracting the fundamental wave (sine wave) component of the output clock of the 1/4 frequency divider 1603. Also, vC01504
The output clock is l/, and the frequency divider 1605 divides it into "lha".
The frequency is divided and output as a clock f1°.

Here, between the sampling clock f,1 of the Y signal during reproduction and the TBC reference signal f, , there is a difference between f, , =(
1″8) It is assumed that there is a frequency relationship of f, 1.

FIG. 17 shows the configuration of the Y signal resampling clock phase control circuit 1511.

Here, the clock obtained by the PLL circuit 1526 is passed through the variable delay circuit 1705, and the phase of the output, the resampling clock L for the Y signal, is that of the resampling phase reference signal added to the reproduced Y signal. so that it has a constant phase relationship with the phase reference point.

Controls the variable delay circuit 1705.

At this time, a control signal to the variable delay circuit 1705 is obtained by a Y signal resampling clock phase control signal generation circuit 1706 surrounded by a broken line.

In FIG. 17, 1707 is a counter circuit, which operates using the sampling clock f,1 as a clock.

The counter circuit 1707 uses the synchronization signal (5YNC) as a reset signal, and uses the falling edge of the horizontal synchronization signal as a reference point and counts the clock f□ as shown in FIG. The timing is pulse G
Outputs l and G2. 170:l, 1704 is a sample hold circuit, which converts the Y signal into pulses Gl and G2.
Sample and hold at the timing.

A differential amplifier 1702 obtains the output difference between these two sample and hold circuits 1703 and 1704. Then, a signal obtained by multiplying this difference signal by an LPF 1701 (which serves as a loop filter) is output as a phase control signal to control the delay time of the variable delay circuit 1705.

When the phase is correctly controlled by the variable delay circuit 1705, the output sampling clock is the 18th clock.
The timing is shown in Fig. f1□'.

The above-mentioned variable delay circuit 1705 may be constructed by connecting several stages of CMOS buffers as shown in FIG. 19 and changing the delay time by controlling the power supply voltage VI)I. Available for use.

FIG. 20 shows the configuration of the C signal delay control signal generation circuit 1529 shown in FIG. 15.

In FIG. 20, 20 ports 5 are a counter circuit, and the first
The clock (f
□/6) is used as the clock. Counter circuit 20
05 uses the synchronization signal (SYNC) as a reset signal, and as shown in Fig. 21, the clocks (f, □/6) are counted using the falling edge of the horizontal synchronization signal as the reference point. Pulse Gl at the timing shown.
and output G2.

2003 and 2004 are sample and hold circuits, and C
The signals are sampled and held at the timing of pulses G1 and G2, respectively.

The differential amplifier 2002 outputs a difference signal between these two sample and hold outputs. Then, LP is applied to this difference signal.
The signal after applying F2001 (which becomes a loop filter) is C
Output as a signal delay control signal.

Incidentally, FIG. 21 C1 shows the C signal whose delay has been correctly controlled.

Note that a CCD delay circuit or the like can be used as the C signal variable delay circuit 1528 in FIG. 15.

The method for generating the sampling clock during playback has been described above.

A/D converters 1513 and 1514 in FIG. 15 perform A/D conversion of the Y signal and C signal using such a sampling clock as a clock. Then, each converted digital signal is written into the image memory 1515. At this time, the write address for the image memory 1515 is obtained from the address generator 1517.

Furthermore, in the CH3V playback device shown in FIG.
4) and all sample values recorded on the four tracks on the magnetic disk 1501.
It is stored in the image memory 1515 in FIG.

Thereafter, the image processing circuit 1516 causes the image memory 15 to
Using sample value data in 15, interpolation processing and rearrangement of C signal data are performed. Furthermore, at this time, the Y signal is subjected to LPF processing to extract low frequency components of two-dimensional spatial frequencies using a two-dimensional digital filter to obtain YL.

Then, the calculation (Y-YL) is performed to obtain the high-frequency component Y□ of the sample value data of the Y signal. Therefore, in the end, Y,
, Y, C, , C, are stored in the image memory 1515.
It will exist within.

After the above processing is completed, each data in the image memory 1515 is read out at a predetermined clock rate in a predetermined order according to the read address specified by the address generator 1517.

In this way, Y is read out from the image memory 1515.
)l, Yt, , CR, YL in CC signal,
The CR1CB signal is RL in the matrix circuit 1519.
,GL,B,, is converted into a signal. and adder 152
Y is added to 0 to 1522, and the adder 15
From 20,1521.1522, (RL+y□), (G
L+Y H) and (B LAY□) signals are output.

The signals output from adders 1520, 1521, and 1522 are converted into analog signals by D/A converters 1523 to 1525, and output as R, G, and B signals, respectively.

[Problems to be Solved by the Invention] The above-mentioned phase reference signal is added immediately before the Y signal portion, as shown in FIG. This place is originally Y
This is the signal section.

Therefore, it is better to keep the period during which the phase reference signal is added as short as possible for the following reasons (22nd
(see figure).

A-■: It is desired to reduce the required recording band by lengthening the period of the Y signal portion to minimize the number of recorded samples, or by lengthening the recording sampling period.

8-■: It is desired to increase the slope of the slope of the added phase reference signal to increase the phase error detection gain (or S/N) for the phase control signal during reproduction.

However, the above matters are advantages for the Y signal, and the following disadvantages arise for the C signal (second
(See Figure 2).

B-■: Even if the slope of the added phase reference signal becomes larger, the recording band of the C signal is approximately 176 times larger than that of the Y signal, so the phase error detection gain does not increase as expected. It cannot be anticipated.

B-■: In addition, as shown in Figure 22. As a result, the permissible time difference change range (±L, /2) in addition to the predetermined time difference between the reproduced Y signal and the reproduced C signal becomes small.

This allows the addition of circuits to the Y and C signal recording/reproducing system.
deletion, and stricter compatibility between each model.

B-■: In order to solve the above B-■, if a long period phase control signal is added only to the C signal, the period of the Y signal part cannot be passed, and the advantage of the above A-■ disappears. It ends up.

The present invention was made to solve this problem, and provides an image signal recording device that can record a luminance signal and a color signal on a recording medium in a form that allows highly accurate phase control during reproduction. The purpose is to

[Means for Solving the Problems] In order to achieve the above object, an image signal recording device of the present invention is a device that records an image signal composed of a luminance signal and a color signal on a recording medium, and includes: a first phase reference signal adding means that inputs a luminance signal, adds and outputs a first phase reference signal having a first phase reference position to the input luminance signal, and inputs a color signal and outputs the first phase reference signal having a first phase reference position; a second phase reference signal adding means for adding and outputting a second phase reference signal having a second phase reference position different from the first phase reference position to the color signal; and the first phase reference signal adding means. A luminance signal to which the first phase reference signal output from the second phase reference signal addition means is added, and a color signal to which the second phase reference signal output from the second phase reference signal addition means is added are both recorded on a recording medium. It is equipped with a recording means.

[Function] With the above configuration, it is possible to add an optimal phase reference signal to each of the luminance signal and 1 color signal, and use the added phase reference signal to each of the luminance signal and 2 color signals during reproduction. This makes it possible to perform highly accurate phase control.

[Embodiment] FIG. 1 is a diagram showing the relationship between resampling phase reference signals for Y and C signals in an embodiment of the present invention.

In the present invention, the resampling phase reference point Rc of the C signal is (1/f□) lower than the resampling phase reference point of the Y signal.
(f5. is the resampling clock frequency of the Y signal) at an earlier position in terms of time.

Moreover, the length LY, Lc of each phase reference signal is L7≦Lc
The relationship is In addition, the timing chart corresponding to FIG. 21 when this phase reference signal is added is shown in the second figure.
Shown in Figure 3.

Incidentally, each of the above phase reference signals can be easily realized by changing the phase reference signal generator 818 shown in FIG. 9 to a required one.

In this embodiment, by making the length of the resampling phase reference signal for the C signal longer than the length of the resampling phase reference signal for the Y signal, the predetermined time difference between the reproduced Y signal and the reproduced C signal is Furthermore, without reducing the allowable time difference change range, the slope of the phase reference signal added to the Y signal can be increased, and the length of the phase reference signal can be shortened. It becomes possible to lower the required recording band and to increase the phase error detection gain for the phase control signal during reproduction.

[Effects of the Invention] As described above, according to the present invention, it is possible to record a luminance signal and a color signal on a recording medium in a form that allows highly accurate phase control during reproduction.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the relationship between phase reference signals for Y signal and C signal, which is an embodiment of the present invention, Fig. 2 is a diagram for explaining an analog transmission system for sample values, and Fig. 3 is a diagram for explaining the sample value analog transmission system. Diagram 4 for explaining the principle of analog transmission of values
Figure 5 shows the transmission path characteristics in analog transmission of sample values, Figure 5 shows the sample points of the Y signal recorded on the recording medium, Figure 6 shows the recording track pattern on the recording medium, and Figure 7 shows the recording track pattern on the recording medium. The figure shows the sample points of the Y signal and C signal recorded on the recording medium, Figure 8 shows the frequency allocation of the recording signal in the Sv format, and Figure 9 shows the main configuration of the recording system of the CHSV camera. Block diagram, Fig. 10 shows the recording track positional relationship on the recording medium of the Y signal and C signal, Fig. 11 shows the waveform of the luminance signal after adding the phase reference signal, and Fig. 12 shows one FIG. 13 is a diagram showing an example of the configuration of a color filter when the imaging section is formed of a solid-state image sensor; FIG. 13 is a diagram showing the configuration of an imaging section having a color filter having the configuration shown in FIG.
The figure shows the configuration of a MOS type solid-state image sensor that can read out signals for two adjacent lines simultaneously in two-line increments, Figure 15 shows the configuration of a CHSV playback device, and Figure 16 shows the configuration of a PLL circuit. 17 is a diagram showing the configuration of the resampling clock phase control circuit for the Y signal.
8 is an operation timing chart of the resampling clock phase control signal generation circuit for the Y signal, FIG. 19 is a diagram showing the configuration of the variable delay circuit, FIG. 20 is a diagram showing the configuration of the C signal delay control signal generation circuit, FIG. 21 is a timing chart of each signal in the configuration shown in FIG. 20, FIG. 22 is a diagram showing the relationship between the phase reference signals for the conventional Y signal and C signal, and FIG. 23 is the Y signal in this embodiment. FIG. 4 is a diagram showing the relationship between the C signal and the resampling phase reference signal. In the figure. 801: Imaging unit 818: Phase reference signal generator 834.1501: Magnetic disk 832.833.1502 To magnetic disk 826.82
7: SV recording process circuit 1511: Sampling clock position for Y signal Y signal, SL machining phase control circuit 1526: PLL circuit

Claims (3)

[Claims] (1) A device for recording an image signal composed of a luminance signal and a color signal on a recording medium, which inputs the luminance signal and has a first phase reference position with respect to the input luminance signal. a first phase reference signal adding means for adding and outputting a first phase reference signal; and a second phase reference position for inputting a color signal and having a second phase reference position different from the first phase reference position for the input color signal. The second phase reference signal is added and outputted.
a phase reference signal adding means, a luminance signal to which the first phase reference signal is added outputted from the first phase reference signal adding means, and a second phase reference outputted from the second phase reference signal adding means. 1. An image signal recording device comprising: recording means for recording a color signal to which the signal is added together on a recording medium. (2) a first phase reference position of the first phase reference signal;
The image according to claim 1, wherein the second phase reference position of the second phase reference signal is temporally separated by an integral multiple of 1/f_s_1 (f_s_1 is a sampling frequency of the luminance signal). Signal recording device. (3) The image signal recording device according to claim 2, wherein the second phase reference signal has a longer length than the first phase reference signal.