JPH03256493A - Picture signal recording and reproducing system - Google Patents

Abstract

PURPOSE:To simplify configuration by forming interpolating picture signals by sampling and holding stored sampling picture signals. CONSTITUTION:Sample and hold (S/H) circuits 219 and 220 execute sample and hold each time the effective sample value data of CR and CB signals to be supplied from a picture memory 215 are inputted. Then, the sampled and held data are supplied to D/A converters 222 and 223. Thus, since the interpolating picture signals are formed by sampling and holding the stored sampling picture signals, the configuration can be simplified and further, the picture signals can stably be recorded and reproduced without being degraded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal recording and reproducing system that records an image signal on a recording medium and reproduces the image signal recorded on the recording medium.

[Prior Art] Conventionally, there is a still video (hereinafter abbreviated as SV) system as a device for recording and reproducing still image signals. This SV system records a current TV signal, such as an NTSC television (TV) signal, on a magnetic disk by subjecting it to FM modulation. Therefore, the resolution of image signals recorded and reproduced by this Sv system was at a level that complied with the current TV system. However, in systems that handle still image signals such as the Sv system, the reproduced image may be printed out using a printer, and in this case,
It was pointed out that the image quality (especially resolution) was lower than that of silver halide photography. In addition, recently HDTV (High D
New TV formats such as HDTV are being considered, and the HDTV format is the same as the current NTSC.
It has approximately 1,000 scanning lines, which is twice as many as the conventional method, and has a corresponding horizontal signal band. Therefore, it is essential to develop the Sv system into a still image recording and reproducing system having a resolution of about 1000 x 1000 pixels (when a square screen is extracted) such as that obtained from HDTV. In such a development, the problem is the recording format of the recording medium. However, when selecting a recording format, a problem arises in that compatibility with the conventional Sv system must be maintained.

As a way to solve such compatibility problems, CHSV
Compatible High Defini
The present applicant is considering a method called tion SV).

An outline of the CHSV method will be described below.

The CH3V method uses a technique called analog transmission of sample values.

The analog transmission system for sampled values is characterized by transmission path characteristics (LPF characteristics) and resampling, as shown in FIG. That is, the input sample value or
This is a system in which the signal is restored by being resampled after passing through an FM modulation system, an electromagnetic conversion system, and an FM demodulation system.

The principle of analog transmission of sample values will be discussed a little more with reference to FIG. 4. Here, we will consider the case where a sample value sequence with a period T as shown in FIG. 4(a) is recorded and reproduced. The transmission path consisting of the FM modulation and electromagnetic conversion system has low-pass characteristics, that is, low-pass filter (LPF) characteristics. FIG. 4(b) shows the output of this transmission line. Therefore, when this transmission line output is resampled with a resampling pulse having a period T and a correct phase as shown in FIG. 4(c), the result shown in FIG. 4(d) is obtained. That is, the input sample value sequence is correctly reproduced (transmitted). However, Fig. 4 (e
) If the resampler phase shifts, the sample value sequence will not be reproduced (transmitted) correctly, resulting in ringing as shown in FIG. 4(f). Therefore, in analog transmission of sample values, at the time of reproduction (receiving side), it is necessary to: ■ generate a sampling pulse with the correct frequency (period) that follows the reproduced (received) sample value signal; It is necessary to generate a resampling pulse that follows the correct phase.

There is also one more condition for completely transmitting the sample value signal. This is: ■The transmission line consisting of FM modulation/demodulation and electromagnetic conversion system is linear phase, and the frequency characteristic is sampling frequency f, /2 (=
It has a point-symmetric characteristic centered on the frequency l/2a).

That is, the transmission line must have LPF characteristics as shown in FIG. The analog transmission of sample values has been briefly explained above.

Next, a method for recording a luminance (Y) signal based on the CHSV method will be described.

FIG. 6 is a diagram showing sample points of a Y signal recorded on a magnetic disk in the CH3V system. As shown in FIG. 6, eight sample points of the Y signal are arranged in an offset manner and are transmitted by subsampling. Furthermore, there are 650 sample points (=1300/2) in one row and 500 sample points (-1000/2) in one column. Then, the sample values included in A r , A 2 . . . are stored in one track on the magnetic disk as B, , B 2 .
Sample values contained in or to another track...
In this way, all sample points are recorded using a total of four tracks.

Note that all sample points recorded in each track are Sv
It will be held in accordance with the format.

FIG. 7 shows frequency allocation of recording signals in the Sv format. As shown in FIG. 7, the baseband bands of the Y signal and C signal recorded in the Sv format are approximately 6.5 MH2 or less and approximately I MH2 or less, respectively.

In FIG. 6, each row includes 650 Y signal sample points, which are recorded during the horizontal effective screen period (53g5ec or less) of the NTSC-TV signal. Therefore, the sampling frequency fs (see FIG. 5) at this time is approximately 13 MH or less.

As described above, Y having a band as shown in FIG.
The signal is recorded.

In addition, FIG. 8 shows two types of recording patterns on a magnetic disk recorded based on the CHSV method.
) is the recording pattern when a 2-channel (ch) head is used, and FIG. 8(b) is the recording pattern when a 4-channel head is used (However, if a 4-channel head is used, the recording pattern shown in FIG. 8(a) is (b) is also possible.

In the case of FIG. 8(a), first, for the first and second tracks, rows AH (i is a positive integer) and Y of row 80 in FIG.
Record sample values of the signal on two channels simultaneously using a two-channel head, then move the two-channel head to the third and fourth tracks (however, it is not necessary to move when using a four-channel head); D.

Sample values of row, C, and row Y signals are recorded simultaneously for 2 channels. At this time, as shown in the figure, in order to maintain compatibility with the conventional SV format, the tracks on which the sample values of the Y signal in row 8 and row C8 are recorded are reversed.

In addition, when recording on 2 channels at the same time, there is a problem of crosstalk between the recording signals within the head, which generally occurs during recording, or by using the recording method described above, there is no problem between the two heads during simultaneous recording. Since only the well-known H sorting is performed, this problem is solved.

Furthermore, when a 4ch head is used, recording as shown in FIG. 8(b) may be performed. That is, first, for the first and third tracks, the sample values of the A and Y signals of the 88th row are
ch simultaneously, then record C for the 2nd and 4th tracks.
The sample values of the Y signal in row 0 and row D0 are recorded simultaneously for 2 channels.

By performing recording as described above, in the case of Fig. 8(a), frame playback based on the conventional SV format is possible using track 2.3, and in the case of Fig. 8(b).
In this case, frames can be played back based on the conventional S format using the first and second tracks or the third and fourth tracks.

Furthermore, field playback is possible on any track.

The method for recording the Y signal in the CHSV method has been described above.

Next, recording of color difference line sequential (C) signals in the CH3V system will be described.

FIG. 9 shows the Y signal, CM (=RY) signal, and CB (=
B-Y) shows the recording sample pattern relationship of the signal. In the conventional Sv format, the recording band of color difference signals is Y
This is approximately one-sixth of the signal.

Further, the color difference signals are line-sequentially recorded.

Therefore, the color difference signal CR recorded in the CHSV method
The sample patterns of CB and CB are shown in Fig. 9(b) and (c).
It becomes as shown in . Also, on the right side of FIG. 9(b) and (C), Y recorded on the same track on the magnetic disk is shown.
A signal line.

It is indicated by the symbols B, , C, and Di. Whether there are locations where the corresponding Y signal line and C signal line are not the same line is also a result of consideration of compatibility with Sv.

FIG. 10 shows the recording positional relationship of the Y signal and the C signal. Here, 1st 5step means "2 steps to be performed on the first step"
Similarly, 2nd 5tep refers to "the second 2ch simultaneous recording". As mentioned above, in the 1st 5step, track 1.
Track 3.4 is recorded at 2nd 5tep.
record. For example, in Figure 10, track l has 1s.
At t 5tep, Y(At) (A shown in Figure 9)
, Y signal consisting of a sequence of Y sample values on the line) and CR
(At)/c, (B,) (A shown in Figure 9 consists of a C8 signal consisting of a row of CR sample values on the line, and B, a CBC signal consisting of a CB sample value on the line,
, l signal) are recorded. In addition, in Fig. 1O, the output of the imaging section (Yl
.

Y2. R and B) are signals simultaneously output from the imaging unit in the CH8v camera described later.

Next, the configuration of a CHSV camera (a device composed of an imaging section and a recording section) will be described.

FIG. 11 is a diagram showing a schematic configuration of the CHSV camera.

As mentioned above, the CH3V camera shown in FIG.
By performing channel simultaneous recording twice in succession, image recording signals for one screen are recorded. 1st 5te shown in Figure 1O
At p, the Sv recording process circuits 826 and 827 apply predetermined emphasis, FM modulation, etc. to the input Y signal and C signal, respectively, and output signals obtained by frequency multiplexing each signal. In adders 828 and 829,
The output signals of these SV recording process circuits 826 and 827 are combined with the ID signal output from the ID signal generator 835 and the TBC (Time Ba5e Corrector) during playback.
), the clock signal generated by the clock generator 813 is used as a reference signal for the band pass filter (BPF) 8.
The sine wave pilot signal f obtained by passing through
-Y, FM-C gap) and output. The signals output from the adders 828 and 829 are sent to the recording amplifier 830.
, 831, 2ch head 832, 833
2 channels are simultaneously recorded on a predetermined track of the magnetic disk 834. And 2nd 5tep is 2ch
After the head 832°833 is moved, the above 1s
A recording operation is performed in the same manner as in step 5t.

Next, the imaging unit 801 shown in FIG. 11 will be explained.

FIG. 12 is a diagram showing the configuration of a color filter used in a solid-state image sensor when the imaging unit 801 is configured with a solid-state image sensor. As shown in FIG. 12, the color filter is composed of a Y (luminance) filter arranged in a checkered pattern, and an R filter and a B filter arranged line-sequentially in the remaining parts.

Further, FIG. 13 is a diagram showing an example of the configuration of an imaging section 801 including a solid-state image sensor having a color filter configured as shown in FIG. 12.

In FIG. 13, 1301 is a solid-state image sensor having the color filter shown in FIG. 12, and 1302 to 1305 are sample and hold circuits, respectively. Solid-state image sensor 13
The image sensor has a pixel count of approximately 01 to 1300 (pixels) x 1000 (pixels), and is configured to be able to read out signals for two vertically adjacent lines simultaneously and every two lines.

In FIG. 13, the signal &1 (0-1) includes the Y signal (Yl) of the upper line of the two lines of signals read out simultaneously.
) is output. Also, the Y signal (Y2) of the lower line is output to the signal line (0-3), the R signal is output to the signal line (0-2), and the B signal is output to the signal line (〇-4). Ru.

The sample and hold circuits 1302 to 1305 are
These signals are sampled and held at predetermined timing and output.

FIG. 14 is a diagram showing a specific example of a solid-state image sensor configured as a MOS solid-state image sensor that can read signals for two adjacent lines simultaneously and every two lines as described above.

The MOS type solid-state image sensor shown in FIG.
sversal signal line) system, which is generally well known.

The MOS type solid-state image sensor as shown in Fig. 14 is CHSV.
In this method as well, since the signals are read out in order in the horizontal direction, there is an effect of suppressing smear and the like.

Further, since the signal readout of the MOS type solid-state image pickup device is based on the x-y address method, simultaneous readout of two lines as described above is possible. Further, a detailed explanation of this read operation will be omitted.

Next, in FIG. 11, Y, which is output by driving the imaging unit 801 by the imaging unit drive circuit 808 in synchronization with the synchronization signal output from the clock generation unit 813,
, Y2. R, B signal or SV recording process circuit 826, 8
The processing of the signals input to the 27 will be described separately for the Y signal and the C signal.

First, regarding the Y signal, the Y□ and Y2 signals output from the imaging unit 801 (as described above for Y r and Y2, see FIG. A phase reference signal output from a reference signal generator 818 is added. The phase reference signal serves as the phase reference for the resampling operation during playback, which will be described later, and is inserted once every IH (H is a horizontal synchronization period) and once every IV (V is a vertical synchronization period). There may be cases. FIG. 15 shows the case where the phase reference signal is inserted one recess for each IH. As shown in FIG. 15, the phase reference signal is a three-electric signal, and R in the figure is the phase reference point.

The Y, Y2 signals to which the phase reference signal has been added in adders 814 and 816 pass through LPFs 802 and 805, each having a pass frequency band of 6 MHz, and pass through gamma correction circuits (γY) 821 and 823, and then are recorded in S. It is input to process circuits 826 and 827.

Note that γY821 and 823 are transmission line γ correction circuits, which are used to improve the S/N in dark areas of the luminance signal.
This is done for the purpose of maintaining compatibility with the conventional Sv format.

Next, regarding the C signal, the R and B signals obtained from the imaging unit 801 (R and B are as described above.
(see Figure 0) passes through LPFs 804 and 807, each having a pass frequency band of IMH, and then passes through the switch circuit Sl.
, S2. Switch circuit S r , S 2
operates to switch for each MH, and one color line sequential signal R/B
(output of S) and B/R (output of S2) are obtained.

In the subtracters 809 and 810, these switch circuits S +
, S2, the Y1 signal output from the LPF 803 having a pass frequency band of IMH, and the Y2 signal output from the LPF 806 having a pass frequency band of IMH, are subtracted, and a color difference line sequential signal C is obtained. ,/C
B is output from the subtracter 809, and the color difference line sequential signal CB/CR is output from the subtracter 810.

Next, sample and hold circuits 811 and 812 sample the C and l-9CII sample patterns shown in FIG. 9, and supply them to adders 815 and 817. This sampling clock is supplied from the clock generation section 813.

Then, in the adders 815 and 817, a phase reference signal as shown in FIG. 16 is added in the same way as the Y signal. good).

The signals output from adders 815 and 817 are LPFB1
9,820 and gamma correction circuit (yc) 822.82
4, and is input to S2 recording process circuits 826 and 827.

Thereafter, as described above, the TBC reference signal f1 and the ID signal generated by the ID signal generator 835 are combined with the adder 828.
, 829 and recorded on a recording medium 834 by 2ch heads 832 and 833. Furthermore, the ID signal is 13f.
The carrier signal of , is converted into DPS by digital data.
K (Differential Phase 5hi
ft Keying) modulated signal, which is based on the known Sv format.

Next, the configuration of the CHSV reproducing device will be described.

FIG. 17 is a diagram showing the configuration of the CH3V reproducing device.

The signal reproduced from the magnetic disk 1501 by the magnetic head 1502 is input to both the SV reproduction process circuit 1504 and the LPF 1530 via a preamplifier 503.

The Sv reproduction process circuit 1504 separates the frequencies of FM-Y and FM-C (see FIG. 7) from the input reproduction signal, and performs FM demodulation, de-emphasis, etc. on each of them, thereby producing reproduction Y and reproduction C. Output a signal.

Next-stage inverse gamma correction circuit (γy-') 1506. (γ,
-1) 1507 indicates the transmission path γ7. γ.

This is a circuit for returning the corrected signal to the original signal. And the (γY-')1506. (γC-January 50
The Y signal corrected by LPF, 1508 is sent to an A/D converter 1513 and a synchronous separation circuit 1510.7.
In the Y sampler clock generation circuit 1511,
The C signal passed through P F 1509 is sent to A/D converter 151.
4. It is input to the C sample link clock generation circuit 1512.

Next, a method of generating a resampling clock during playback will be described.

On the other hand, TBC (Time Ba5e Correct
The pilot signals f, , for r) are input to a sampling clock generation circuit 1511 for Y signal and a sampling clock generation circuit 1512 for C signal. The Y signal sampling clock generation circuit 1511 generates P L L (P
has a Locked Loop) circuit, and the P
In the LL circuit, a clock fso(Y) which is phase synchronized with the pilot signal f and has the same frequency as the Y signal resampling clock is formed.

In addition, the Y signal resampling clock generation circuit l51
1 also has a phase control circuit, which controls the phase of the resampling clock flTO(Y) formed as described above, and as shown in FIG. A resampling clock fs+(y) for the Y signal having a fixed phase relationship with the phase reference point of the Y signal sampling phase reference signal is formed and output.

On the other hand, the C signal sampling clock generation circuit 1512
In other words, the Y signal sampling clock generation circuit 15
11, a clock fso is synchronized in phase with the pilot signals f, - in the internal PLL circuit and has a frequency equal to 1/6 of the frequency of the resampling clock for the Y signal.
(C) is formed. The C signal resampling clock generation circuit 1512 also has a phase control circuit, and the resampling clock fs generated as described above.
o(c), and as shown in FIG. 16, the resampling for the C signal is carried out in a fixed phase relationship with the phase reference point of the above-mentioned C signal sampling phase reference signal added to the reproduced C signal. A clock fS, (C) is formed and output.

The A/D converters 1513 and 1514 in FIG. 17 are the resampling clock fs+ generated as described above.
(Y), fs+ (C) as clocks, the Y signal and the C signal are A/D converted and written into the image memory 1515.

At this time, the write address for the image memory 1515 is generated by address generators 1517 and 1818.

Furthermore, the CHSV reproducing apparatus shown in FIG. 17 performs the above-described reproducing operation on the magnetic disk 1501 shown in FIG.
All sample values recorded in the upper 4 tracks are stored in image memory 1515 in FIG.

Thereafter, the image processing circuit 1516 causes the image memory 15 to
Using sample value data in 15, interpolation processing and rearrangement of C signal data are performed. At this time, the Y signal is subjected to LPF processing to extract low frequency components of two-dimensional spatial frequency using a two-dimensional digital filter to obtain YL. Then, the calculation (Y-YL) is performed to obtain the high frequency component Y of the sample value data of the Y signal. Therefore, the final result is Y□.

4 types of data or image memory 1515: yL, c, , c8
It will exist within.

After the above-described processing is completed, each data in the image memory 1515 is read out at a predetermined clock rate in a predetermined order according to the read addresses designated by the address generators 1517, 151.8.

In this way, Y is read out from the image memory 1515.
,, Y t , C* , y,,c in the CB signal
,,c, the signals are RL, in the matrix circuit 1519.
The GL and BL signals are converted. and adder 1520~
At 1522, addition to ¥8 is performed, and the adder 1520
, 1521. ]522, (RL +Yl+), (G
L + Y, 4), (BL + Y□) signal is output.

Then, the signal 1 output from the adders 1520, 1521, and 1522 is converted into an analog signal by D/A converters 1523 to 1525, and output as R, G, and B signals, respectively.

In addition, the ID signal multiplexed on the playback signal is LPF153.
After being separated by 0, it is decoded by ID decoder 1531.

Next, the interpolation process performed by the image processing circuit 1516 of the CHSV playback device shown in FIG. 17 will be explained. In FIG. 17, if the sample value data stored in the image memory 1515 is a Y signal, it is either valid sample value data (marked with a circle in the figure) as shown in FIG. 18, similar to the sample point arrangement at the time of recording. Offsets are arranged every two samples. The image processing circuit 1516 uses this valid sample value data to process invalid sample value data (
mark) is interpolated. That is, as an interpolation method, a digital interpolation filter as shown in FIG. 19 is provided in the image processing circuit 1516, and the image memory 151
Interpolation processing of the Y signal is performed by supplying valid sample value data sequentially read from 5 to the digital interpolation filter.

The digital interpolation filter shown in FIG. 19 includes 1 sample delay lines 1802-1840, 1 horizontal synchronization period (H) delay lines 1841-1844, adders 1845-1861. It is composed of coefficient multipliers 1862 to 1867, a divider 1868, and a switch 1869. During the period when valid sample value data is supplied to the input terminal 1801, the switch 1 is
By connecting 869 to the B side in the figure, output terminal 1
870 outputs valid sample value data as is, and during a period when invalid sample value data is supplied to input terminal 1801, switch 1869 is connected to side A in the figure to output the invalid sample value data on image memory 1515. Interpolation calculation data is formed from 18 valid sample value data around the value data, and is output from the output terminal 1870. In addition, in FIG. 19, coefficient multipliers 1862 to 1867
The coefficients multiplied in (X t~) have a total of “1
28", the multiplier 1868 converts the input data to "1/128".
” is set to the value.

In addition, in the case of the C signal, the band is limited to 1/6 of the Y signal at the time of recording and is further line-sequentially recorded, so that the effective sample value data ( (○ marks in the figure) are arranged offset every 12 samples in the horizontal direction and every 2 lines in the vertical direction. Similarly to the Y signal, the image processing circuit 1516 uses the valid sample value data to generate invalid sample value data (
mark) is interpolated. That is, the interpolation method performed by the image processing circuit 1516 is different from the case of the Y signal described above, and the interpolation process in the vertical direction and the interpolation process in the horizontal direction of the image are performed separately. First, the vertical interpolation process uses the average value of the valid sample value data located every 4 lines, and uses the invalid sample value data (Δ in FIG. 20(b)) at the midpoint of the valid sample value data. ) is interpolated. Then, using the average value of the interpolated sample value data and the valid sample value data, the invalid sample value data between the interpolated sample value data and the valid sample value data (Figure 20 (C)
) is interpolated, and as shown in Figure 20 (C),
Interpolation processing is performed so that the valid sample value data becomes an interval of 6 samples in the horizontal direction. Next, the horizontal interpolation process uses the valid sample value data interpolated by the vertical interpolation process as described above, and uses the 5 points between the valid sample value data.
The invalid subtable value data (marked with ◇ in FIG. 20(d)) is linearly interpolated.

[Problems to be Solved by the Invention] By the way, the digital interpolation filter used for horizontal interpolation processing of the C signal in the conventional CH5V reproducing device as described above has a configuration as shown in FIG. 21, for example. It will come true. The digital interpolation filter shown in FIG.
0 to 20I4, and coefficient multipliers 2015 to 2020, and the coefficients multiplied by the input data in the coefficient multipliers 2015 to 2020 are "2", "3", '4", and "
5", "6"1/6".

The digital interpolation filter shown in FIG. 21 requires a total of six coefficient multipliers as shown, making the configuration complicated.

Furthermore, among these coefficient multipliers, the coefficient multiplied by the input data in the coefficient multiplier 2020 is l/6 (approximately 0.16
7), it becomes difficult to set the coefficient multiplier.

In addition, in an image recording and reproducing system that complies with the CH3V method, during recording, a pilot signal for TBC used during playback is placed in the frequency band (2.5 MHz to 3 MHz) between the Y-FM signal and the C-FM signal. The pilot signal is configured to be multiplexed, and the pilot signal leaks into the image signal.
There is a risk that image quality will deteriorate during interpolation processing performed during playback.

The present invention was made to solve such problems,
It is an object of the present invention to provide an image signal recording and reproducing system that can simplify the configuration and stably record and reproduce image signals without deteriorating them.

[Means for Solving the Problems] In order to achieve the above object, the image signal recording and reproducing system of the present invention is formed by sampling image signals each composed of a luminance signal and a color signal. In a system for recording a sampled image signal on a recording medium and restoring the original image signal using the sampled image signal reproduced from the recording medium, a memory means for storing the sampled image signal reproduced from the recording medium; and interpolated image signal forming means for forming an interpolated image signal by sample-holding the sampling image signal stored in the memory means.

[Function] With the above configuration, it is possible to record an image signal on a recording medium with a simple configuration without making the deterioration of one image noticeable, and to stably reproduce the image signal recorded on the recording medium. You will be able to do it.

[Example] Hereinafter, the present invention will be explained using examples of the present invention.

In this embodiment, a CHSV type image signal recording and reproducing system to which the present invention is applied will be explained, and since the luminance signal (Y) is the same as the above-mentioned system, detailed explanation will be omitted and will not be described here. Recording and reproducing of color difference line sequential (C) signals in a CHSV image signal recording and reproducing system will be described.

FIG. 22 shows the relationship between recording sample patterns of C, (=RY) signals and CB (=BY) signals in this embodiment. In this embodiment, the recording band of the color difference signal is approximately one-eighth of the Y signal. Further, the color difference signals are line-sequentially recorded. Therefore, the sample patterns of color difference signals CR and CB recorded in the CHSV method are as shown in FIGS. 22(a) and 22(b). Also, on the right side of FIGS. 22(a) and 22(b), there is a line A□ recorded on the same track on the magnetic disk.

Indicated by symbols B, , C, and D□. The corresponding FIG. 7 (
The Y signal line shown in a) and FIG. 22(a).

Whether there are any locations where the line of the C signal shown in (b) is not the same is also a result of consideration of compatibility with Sv.

Next, the configuration of the CHSV camera (device composed of an imaging section and a recording section) in this embodiment will be described.

FIG. 23 is a diagram showing a schematic configuration of the CH3V camera.

The CHSV camera shown in FIG. 23 records image recording signals for one screen by performing 2ch simultaneous recording twice in succession. In FIG. 23, first, the SV recording process circuits 126 and 127 apply predetermined emphasis, FM modulation, etc. to the input Y signal and C signal, respectively, and then output signals obtained by frequency multiplexing each signal. The adders 128 and 129 are connected to these Sv recording process circuits 12.
The ID signal output from the ID signal generator 135 and the TBC during playback (Time Ba5e
A sine wave pilot signal f (frequency around 2.51H2!, that is, the 24th FM-Y from the figure.

FM-C gap) and output. Adder 128.
The signal output from 129 is sent to recording amplifiers 130 and 131.
The signals are amplified by the 2ch heads 132 and 133 and simultaneously recorded on the predetermined trunks of the magnetic disk 134 for 2ch. Then, after the 2ch heads 132 and 133 are moved, a recording operation is performed in the same manner as described above.

In FIG. 23, an imaging section 101 having the same configuration as the imaging section 801 in FIG. Y2. The signal processing for inputting the R and B signals to the Sv recording process circuits 126 and 127 will be described separately for the Y signal and C signal.

First, regarding the Y signal, the Y, , Y2 signals output from the imaging unit 101 are sent to the respective adders 114 and 1.
At 16, the phase reference signal output from the phase reference signal generator 118 is added. The phase reference signal serves as a phase reference for resampling operation during playback, which will be described later.
(H is the horizontal synchronization period)
It is conceivable that one doujin can be created every (vertical synchronization period).

Y to which the phase reference signal is added in adders 114 and 116 1. The Y2 signal passes through LPFs 102 and 105, each having a pass frequency band of 61H2, and is input to SV recording process circuits 126 and 127 via gamma correction circuits (γy) 121 and 123.

Note that γy 121 and 123 are transmission line γ correction circuits, which are performed for the purpose of improving the S/N in dark areas of the luminance signal and maintaining compatibility with the conventional Sv format. .

Next, regarding the C signal, the R and B signals obtained from the imaging section 101 are input to the switch circuits S, , S, 2 through LPFs 104 and 107, each having a pass frequency band of IMH2. switch circuit S II,
s+2 operates to switch for each MH, and outputs color line sequential signals R/B (output of S11) and B/R (S11 output).
+2 output).

In the subtracters 109 and 110, these switch circuits S,...
, S,2, Y, signal, I output from LPF 103 having a pass frequency band of I MH2.
The Y2 signal output from the LPF 106 having a pass frequency band of MH, is subtracted, and the color difference line sequential signal C, l/C is obtained.
B is output from the subtracter 109, and the color difference line sequential signal CB/CR is output from the subtracter 110.

Next, the sample and hold circuits 111 and 112 sample the CR and Ca sample patterns shown in FIGS. 22(a) and 22(b), and adder 115
, 117. This sampling clock is
It is supplied from the clock generation section 113.

Then, in adders 115 and 117, a phase reference signal is added in the same way as the Y signal (however, the phase reference point of the C signal does not have to be at the same position as the phase reference point of the Y signal).

The signals output from adders 115 and 117 are 0.75
LPF II9.120 with a pass frequency band of MH,
and gamma correction circuit (γc) 122°124, S
v is input to recording process circuits 126 and 127.

Thereafter, as described above, the TBC reference signal f and the ID signal generated by the ID signal generator 135 are combined with the adder 128.
, 129 and recorded on the recording medium 134 by the 2ch heads 132 and 133. Furthermore, the ID signal is 13f.
The carrier signal of , is converted into DPS by digital data.
K (Differential Phase 5hi
ft Keying) modulated signal, which is based on the known Sv format.

Next, the configuration of the CH3V reproducing device will be described.

FIG. 1 is a diagram showing the configuration of a CHSV playback device.

Signals reproduced by the magnetic disks 201 and 202 pass through a preamplifier 203 and are sent to an Sv reproduction process circuit 204.
and LPF 230.

The Sv reproduction process circuit 204 separates FM-Y and FM-C (see FIG. 24) from the input reproduction signal by the same wave number, and performs FM demodulation, de-emphasis, etc. on each of them, thereby producing reproduction Y and reproduction signals. Outputs C signal.

Next-stage reverse gamma correction circuit (γY-'') 206.

(γc-′) 207 is the transmission path γY at the time of recording.

γ. This is a circuit for returning the corrected signal to the original signal. And the (γY-')206. (γ.-1)2
The Y signal corrected by 07 and passed through LPF208 is A
The C signal that has passed through the LPF 209 is input to the A/D converter 214, the synchronous separation circuit 210, the Y sampling clock generation circuit 211, and the C sampler clock generation circuit 212.

Next, a method of generating a resampling clock during playback will be described.

On the other hand, T separated from the reproduced signal by the BPF 205
A B C (Time Ba5e Corrector) pilot signal f is input to a Y signal sampling clock generation circuit 211 and a C signal sampling clock generation circuit 212 . The Y signal sampling link clock generation circuit 211 has a PLL (Phase Loc)
ked Loop) circuit, which is synchronized in phase with the biloft signal f in the PLL circuit and has a clock fs3 (Y
) to form.

In addition, the Y signal resampling clock generation circuit 211
also has a phase control circuit, which controls the phase of the resampling clock fsy(Y) formed as described above, and adjusts the phase of the aforementioned Y signal sampling phase reference signal added to the reproduced Y signal. A resampling clock fs4 (Y) for the Y signal having a constant phase relationship with the reference point is formed and output.

On the other hand, in the C signal sampling clock generation circuit 212, the Y signal sampling clock generation circuit 211
Similarly, in the internal PLL circuit, the pilot signal fr
A clock fs: 5 (C
) to form. The C signal sampling clock generation circuit 212 also has a phase control circuit, and the resampling clock fs3(C) generated as described above is
The C signal resampling clock fS4 has a constant phase relationship with the phase reference point of the above-mentioned C signal sampling phase reference signal added to the reproduced C signal.
(C) is formed and output.

The A/D converters 213 and 214 in FIG. 1 generate resampling clocks fS4(y) and fs as described above.
, (c) as the clock, the Y signal and the C signal are
/D conversion and written to the image memory 215. At this time, the write address for the image memory 215 is generated by address generators 217 and 218.

Furthermore, the CHSV playback device shown in FIG. 1 performs the playback operation as described above on all four tracks (first to fourth) on the magnetic disk 201,
All sample values recorded in the four tracks on the top 1 are stored in the image memory 215 of FIG.

Thereafter, the image processing circuit 216 causes the image memory 215 to
Interpolation processing is performed using the sample value data within.

The interpolation process performed by the image processing circuit 216 of the CH3V playback device shown in FIG. 1 will be described below.

Note that the interpolation process for the Y signal is the same as described above, so a detailed explanation will be omitted, and the interpolation process for the C signal will be described here.

In the case of the C signal, the band is limited to 1/8 of the Y signal at the time of recording, and since it is recorded line sequentially, the second
As shown in FIGS. 2(a) and 2(b), the effective sample value data (marked with ◯ in the figure) is offset every 16 samples in the horizontal direction and every 2 lines in the vertical direction. Then, the image processing circuit 216 interpolates the invalid sample value data (indicated by △ in the figure) using the valid sample value data.

That is, the interpolation process performed by the image processing circuit 216 is only the interpolation process in the vertical direction of the image, and the vertical interpolation process uses the average value of the valid sample value data located at every 4-line interval. Invalid sample value data is interpolated between the value data and valid sample value data, and interpolation processing is performed so that the valid sample value data is at intervals of 8 samples in the horizontal direction.

The Y, C, CB double signal image memory 215 that has been interpolated as described above is read out, and the Y signal is sent to the D/A converter 2.
21, and the C, C, and C signals are respectively supplied to sample and hold (S/H) circuits 219 and 220.

The S/H circuits 219 and 220 perform sample and hold every time the valid sample value data of the C rt and CB signals supplied from the image memory 215 is input, and the sampled and held data is sent to the D/A converters 222 and 223. is supplied to

The D/A converter 221 converts the effective sample value data of the Y signal supplied from the image memory 215 into an analog Y signal, supplies it to the delay line 224 and the LPF 225, and outputs the D/A converter 221.
/A converters 222, 223 and S/H circuits 219, 22
The valid sample value data of the CR9CB signal supplied from 0 is converted to an analog CR+C signal, and the LPF226
, 227.

Incidentally, the LPFs 225, 226, and 227 all have characteristics as shown in FIG. 2, and are one-group delay or flat. In addition, in FIG. 2, ■ represents the sampling interval.

The signals that have passed through the LPFs 225, 226, and 227 are supplied to the matrix circuit 229, which processes the low frequency components (YL), CR, and C of the Y signal.
From the B signal, the R, G, and B signal low frequency components (Rt, , Gt
, , Bt, ), and an adder 230°231.232
supply to.

On the other hand, the output from the D/A converter 221 is output from the LPF 225.
, 226, 227, the Y signal delayed by the delay line 224 having the same amount of delay as the LPF
The low frequency component (yt, ) of the Y signal output from the subtractor 225 is subtracted, and the high frequency component (Y)I of the Y signal is output from the subtracter 228.
) is output, and the adder 230.23! , 232.

The adders 230, 231, and 232 are supplied with R i, , GL, which are supplied from the matrix circuit 229.

The Y□ times signals supplied from the BL times signal subtracter 228 are added, and the R signal (RL◆Y,) and the C signal (G
L”Y!(), output as B signal < B L+Y 14).

In addition, in FIG. 1, the ID signal multiplexed on the reproduction signal reproduced from the magnetic disk 201
After being separated by the ID decoder 231, the ID decoder 231 decodes the data.

As described above, in this embodiment, the frequency band of the C signal is recorded as 1/8 of the frequency band of the Y signal during recording, so that the frequency band between the Y signal and the C signal is The frequency of the TBC pilot signal to be multiplexed can be lowered (that is, placed farther away than the Y signal), the leakage of the pilot signal into the Y signal can be reduced, and deterioration of the reproduced image signal can be suppressed.

Furthermore, even if the C signal is narrow-banded and recorded as described above, the C signal does not require much resolution, and as shown in Figure 1, when restoring the image signal, the C@ signal contains the Y signal. Since the high frequency components are added, the deterioration of the reproduced image due to the narrow band of the C signal is not noticeable.

In addition, in this embodiment, the horizontal interpolation processing of the C signal is performed by susceptibly holding the effective sample value data of the C signal and then passing it through an LPF. Horizontal interpolation processing of the C signal can be performed with a simple configuration without using a digital interpolation filter.

[Effects of the Invention] As explained above, according to the present invention, it is possible to simplify the configuration, and the image signal can be stably recorded and reproduced without deteriorating the upper part of one image. We will be able to provide recording and playback systems.

[Brief explanation of drawings]

FIG. 1 shows a C to which the present invention is applied as an embodiment of the present invention.
A schematic configuration diagram of the H5V reproducing device, Fig. 2 is a characteristic diagram of the LPF in Fig. 1, Fig. 3 is a diagram for explaining the analog transmission system of sample values, and Fig. 4 shows the principle of analog transmission of sample values. Figure 5 is a diagram showing the transmission path characteristics, Figure 6 is a diagram showing sample points of the Y signal recorded on the magnetic disk based on the CHSV method, and Figure 7 is a diagram showing the sample points of the Y signal recorded on the magnetic disk. Figure 8 shows the frequency allocation of image signals recorded on each track of CH5.
A diagram showing a recording pattern when an image signal is recorded on a magnetic disk based on the V method.
A diagram showing the recording sample patterns of the (RY) signal and C, (B-Y) signals, Figure 1O is a diagram showing the recording steps of the CHSV system, and Figure 11 is a diagram showing the conventional recording in the CHSV system. A block diagram of the device, FIG. 12 is a diagram showing an example of the configuration of the color filter used, FIG. 13 is a block diagram of the imaging section, FIG. 14 is a diagram showing the configuration of the MO5 type solid-state image sensor, and FIG. 15 16 is a diagram showing the Y signal waveform after addition of the phase reference signal, FIG. 16 is a diagram showing the relationship between the phase reference signal for the Y signal and C signal, FIG. 17 is a block diagram of a conventional reproducing device in the CHSV system, and FIG. 18 is a diagram showing the data arrangement of the Y signal stored in the image memory, and FIG.
A configuration diagram of a digital interpolation filter used for signal interpolation processing. Fig. 20 is a diagram showing the data arrangement of the C signal stored in the image memory. Fig. 21 is a diagram showing the digital interpolation filter used for horizontal interpolation processing of the C signal. Block diagram of interpolation filter,
FIG. 22 shows C and (RY) signals recorded on a magnetic disk by a CHSV recording device as an embodiment of the present invention. FIG. 23 is a block diagram of a Cl5V recording device as an embodiment of the present invention, and FIG. 24 is a diagram showing recording sample patterns of C, (B-Y) signals. FIG. 3 is a diagram showing frequency allocation of image signals recorded on each track on a disc. In the figure. 215: Image memory 219, 220: S/H circuit 2
21.222.223: D/A converter 224:
Delay line 225, 226, 227: L P F
228: Subtractor 229: Matrix circuit 230
．． 231, 232: Adder lever I

Claims (1)

[Claims] A sampled image signal formed by sampling each image signal composed of a luminance signal and a color signal is recorded on a recording medium, and the original image signal is restored using the sampled image signal reproduced from the recording medium. A system comprising: a memory means for storing a sampled image signal reproduced from the recording medium; and an interpolated image signal forming means for forming an interpolated image signal by sample-holding the sampled image signal stored in the memory means. An image signal recording and reproducing system characterized by comprising: