JP4631257B2 - Frame image buffer device - Google Patents

Description

  The present invention is provided with a memory for storing image data of a frame image input in a raster scanning state, and a memory control circuit for writing and reading image data in the FIFO format with respect to the memory. The present invention relates to a frame image buffer device.

A so-called frame image buffer for buffering a frame image input in a raster scanning state is used for various purposes. For example, in the field of a photographic processor, an image processing circuit, a printer, In addition to buffering the image data between the two, it is also conceivable to buffer the image data between the scanner that reads the frame image of the photographic film and the image processing circuit.
As a configuration of the frame image buffer, it is common to use, for example, a commercially available FIFO memory for images. However, it exceeds the several hundred MB required in the field of photo processors. No one has a large storage capacity.
Further, in the field of a photographic processor, as shown in FIG. 3 schematically showing a frame image to be handled, the frame image 102 of the photographic film 101 is sequentially read through the image reading opening 100 of the film scanner. There are multiple types of image sizes and aspect ratios of real images.
Since the FIFO memory itself does not have a function of transmitting information relating to the image size and aspect ratio in such a frame image, it is necessary to provide a plurality of FIFO memories corresponding to each type.

Under such circumstances, it is considered to operate a memory for a personal computer, which is generally constituted by a DRAM, in a FIFO format under the control of a microprocessor.
Since microprocessors and memories for personal computers are originally designed to randomly access the memory, they are not suitable for use in transferring image data of frame images as time series data at high speed. Due to recent significant performance improvements, frame images transferred at extremely high speeds can be buffered.
JP 2001-298684 A

However, although a large-capacity and high-speed memory has become available at a low cost, a high-speed microprocessor corresponding to such a memory is expensive, resulting in an increase in device cost.
The present invention has been made in view of such circumstances, and an object thereof is to provide a high-speed and large-capacity frame image buffer at a low cost.

A first invention of the present application is a memory for storing image data of a frame image input in a raster scan state, and a memory control circuit for writing and reading image data in a FIFO format with respect to the memory And a frame position signal for specifying a pixel at the leading or trailing edge of the frame image, which is input together with the frame image, and a leading edge of each horizontal scanning line of the frame image. A write data generation circuit that organizes a line position signal for specifying a rear end pixel into data writable in the memory together with the image data is provided, and when the frame position signal is received, The data generated by the write data generation circuit is written to the memory, and the line position signal is input. Then, the configuration data generated by the write data generation circuit correspondingly to write to the memory, the address data of the data for the pixels of the frame image each of the tip or rear end, which is stored in the memory Alternatively, a register for storing address data having a certain relationship with the address data is provided, and the memory control circuit loads the address data stored in the register in accordance with a request from the subsequent circuit, and the address data The data is read out from the front end of the frame image specified by the above and output.

That is, a frame position signal for specifying a pixel at the front end or rear end of the frame image, which is input as information related to the size or aspect ratio of the image from the front side, and the front end of each horizontal scanning line of the frame image or The data is organized so that the write data generation circuit mixes the line position signal for specifying the rear end pixel with the image data of each pixel sequentially input.
As described above, by including information on the image size and aspect ratio in the write data before the data is written in the memory, the memory control circuit for controlling the writing and reading of the memory has the image size and aspect ratio. Without considering any information related to the image, it is possible to transmit information related to the size and aspect ratio of the image to the subsequent stage by simply performing the FIFO operation.
Further, in the circuit existing in the subsequent stage of the frame image buffer device, if the previously output data is lost for some reason, as long as the data remains in the memory, the head of the frame image is once again. Image data can be output to the subsequent stage.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, a synchronous signal reproduction circuit that reproduces the frame position signal and the line position signal based on data read from the memory. Is provided.
That is, the circuit existing in the subsequent stage of the frame image buffer device is configured to perform data processing in consideration of the data generation rule in the write data generation circuit, so that the data read from the memory is directly transferred to the subsequent circuit. Although it is possible to output, by providing the synchronization signal reproduction circuit, the frame image buffer device can perform a buffering operation to reproduce the original input state including not only image data but also a control signal. .

According to a third aspect of the present application, in addition to the configuration of the first or second aspect , the write data generation circuit may be configured to receive the frame position signal and the line position signal based on the input image data. By assigning a data value other than the possible data value, the data value has the same bit length as the image data stored in the memory and is generated as data separate from the image data. .
That is, as a method of embedding data based on the frame position signal and the line position signal in sequentially input image data, for example, when data to be written in the memory is 16 bits, 14 bits are converted into image data. A method of assigning and assigning the remaining 2 bits to data for identifying the frame position signal and the line position signal is also possible, but as described above, the frame position signal and the line position signal are If the data to be written in the memory is 16 bits by generating the data having the same bit length as that of the image data stored in the memory and separate from the image data, Image data can be expressed with all of the 16-bit bit length, and the resolution of image gradation can be increased. Can.

At this time, in order to distinguish the data indicating the frame position signal and the line position signal from the normal image data, the frame position signal and the line position signal include input image data. Data values other than possible data values are assigned.
Various modes are conceivable as data allocation modes indicating the frame position signal and the line position signal. For example, when input image data is distributed discretely, the data values of the gaps are set as the data values. What is necessary is just to allocate as a data which shows a frame position signal and the said line position signal, or the filter processing circuit which prevents the input image data from taking the data value of a specific range is provided in the front | former stage side, and the identification is carried out A data value in the range may be assigned as data indicating the frame position signal and the line position signal.

According to the first aspect of the invention, the memory control circuit does not take into account any information related to the image size and aspect ratio, and simply controls the FIFO operation so that the image size and aspect ratio are transferred to the subsequent stage. Since the information related to the ratio can be transmitted, the memory control circuit can be configured with a simple logic circuit, and a high-speed and large-capacity frame image buffer can be provided at low cost.
In addition, in the circuit existing in the subsequent stage of the frame image buffer device, even if the previously output data is damaged for some reason, the frame image buffer device only has to remain in the memory. This eliminates the need for re-flowing image data from the upstream side.
Moreover, if only the data remaining in the memory is to be read, it is only necessary to read all the stored data from the old memory without providing the register. Efficient data transfer without the need for data transfer.
According to the second aspect of the invention, the frame image buffer device performs a buffering operation so as to reproduce the original input state including not only the image data but also the control signal. It is not necessary to consider internal processing in the image buffer device, and the frame image buffer device can be highly versatile.

Further, according to the third aspect of the invention, the resolution of the image gradation can be increased, so that the image quality of the frame image can be maintained high.

Embodiments of a photographic print system provided with a frame image buffer device of the present invention will be described below with reference to the drawings.
The photo print system DP exemplified in the present embodiment is known as a so-called digital minilab apparatus, as shown in FIG. 6, and has been developed as shown in the block diagram of FIG. An image input device IR for generating image data for exposure by taking in image data for producing a photographic print from a film, memory card, MO or CD-R, and the image data for exposure generated by the image input device IR An exposure / development apparatus EP that exposes the photographic paper 1 is configured.

[Schematic configuration of image input device IR]
As schematically shown in FIG. 5, the image input device IR includes a film scanner 2 as a photographic film reading device FR for reading a frame image of a photographic film, a memory reader, an MO drive, a CD-R drive, and the like. An external input / output device 4 and a main control device 6 that controls the entire photographic print system DP in addition to the control of the film scanner 2 are provided. Further, the main control device 6 includes a simulation that simulates a finished print image. A monitor 6a for displaying and outputting a video image and various types of information and an operation console 6b for manually setting exposure conditions and inputting control information are connected.

[Schematic configuration of film scanner 2]
The film scanner 2 is configured as an imaging device that uses a long photographic film as a subject, and includes an image detection unit 2a including an image detection sensor and an optical system for capturing a frame image of the photographic film, and an image detection And a signal processing unit 2b for amplifying and A / D converting the output signal of the unit 2a.
The image detection sensor of the image detection unit 2a is composed of a line sensor (more specifically, a CCD line sensor), and four line sensors are arranged by arranging about 5000 CCD elements in four rows in the width direction of the photographic film. It has. Red, green and blue color filters and an infrared transmission filter are formed on the light receiving surface of each line sensor, respectively, and detect the frame image of the photographic film by color separation and detect infrared transmission image data of the photographic film. To detect.

In FIG. 3 which shows a state in which the frame image 102 of the photographic film 101 is read by the film scanner 2, the longitudinal direction of the image reading opening 100 corresponds to the arrangement direction of the CCD elements in the line sensor.
FIG. 2 shows a relationship between a general frame image and a synchronization signal for reproducing the frame image. In the film scanner 2 as well, there are various sizes and aspect ratios of the frame image 102. In response to the transmission of the image data of the frame image, the frame position signal for specifying the leading or trailing pixel of the frame image, which corresponds to the synchronization signal, etc. A line position signal for specifying the pixel at the front end or the rear end of the scanning line is output, and a signal indicating whether the image data being sent is valid image data is output.

As described above, the frame position signal and the line position signal may be any signal as long as they can specify either the front end pixel or the rear end pixel. However, for convenience of explanation, both signals are used in the following explanation. Description will be made assuming that the pixel at the tip is specified.
When the frame image output from the film scanner 2 is output as an image of an area including the snook portion around the actual frame image, a signal indicating whether or not the image data being sent is valid image data. Is useful for cutting out the actual frame image, that is, specifying the image size, but is not always necessary when the signal processing unit 2b of the film scanner 2 cuts out the actual frame image and outputs it as a frame image.

[Configuration of main controller 6]
As schematically shown in FIG. 5, the main control device 6 includes a simulation calculation unit 10 that executes calculation processing for predicting a print image when produced based on image data input from the film scanner 2; An image processing apparatus 11 that generates exposure image data for operating the exposure / development apparatus EP based on image data input from the film scanner 2 and a controller 12 that manages these operations are provided. Yes.
The controller 12 is connected to a network together with the film scanner 2 and an exposure control device 21 described later, and exchanges various management information with each other.
In the input stage of the image processing apparatus 11, when the film scanner 2 reads a frame image of a photographic film, a part of the original image that has been photographed is due to scratches or dust on the photographic film. It is provided in the data processing device IP that performs data processing (that is, the scratch removal processing) for correcting the missing portion.

[Configuration of Data Processing Device IP]
As shown in FIG. 4, the data processing device IP temporarily receives the image data received from the film scanner 2 and the input side interface 31 that receives the image data of the frame image of the photographic film as the processing target data from the film scanner 2. A FIFO-format frame image buffer device 32 for holding and outputting, a plurality of processing modules MD comprising an input side DSP circuit 35, a first processing circuit 36, a second processing circuit 37 and an output side DSP circuit 38; An output side interface 33 for passing the completed image data to the subsequent circuit and a data relay board 34 for transferring the image data between the processing modules MD are provided.
Each of these processing modules MD is configured to execute different data processing. The image data sequentially input from the film scanner 2 in the raster scanning state is subjected to the first processing from the input side DSP circuit 35. The data is sequentially transferred to the circuit 36, from the first processing circuit 36 to the second processing circuit 37, and from the second processing circuit 37 to the output side DSP circuit 38 via the data relay board 34. Execute the process.

In the present embodiment, the data processing performed by each processing module MD is performed by the input DSP circuit 35 and the first processing circuit 36 correcting the abnormal image data due to scratches on the base surface side of the photographic film. The second processing circuit 37 analyzes the presence / absence of abnormal image data mainly due to scratches on the emulsion surface side and executes correction processing as appropriate, and the output DSP circuit 38 outputs edge data that is no longer necessary from the image data. Delete processing, data formatting processing for passing image data to the subsequent stage, and the like. In this series of processes, the infrared transmission image data is used to determine whether there is abnormal image data due to the scratch or the like.
Each of the processing modules MD can perform almost real-time processing on image data sequentially input from the film scanner 2 in a raster scanning state by sharing the processing and sequentially transferring data.
However, depending on the state of the photographic film to be processed, it may take time to process, and it may be difficult to flow the data completely in real time. For such a case, the frame image buffer device 32 has a large-capacity memory (several hundred MB to less than 1 GB) that can store image data of frame images of several frames to about one order.

[Configuration of Frame Image Buffer Device 32]
The structure of the frame image buffer device 32 will be described in more detail. The frame image buffer device 32 stores image data of a frame image input in a raster scan state from the film scanner 2 as shown in FIG. A memory 41, a memory control circuit 42 for writing and reading image data to and from the memory 41 in a FIFO format, and the frame position signal and line position signal input together with the frame image together with the image data. A write data generation circuit 43 that organizes the data into writable data, a synchronization signal reproduction circuit 44 that reproduces the frame position signal and the line position signal based on the data read from the memory 41, and a write data generation circuit 43 to adjust the timing of transfer data between the memory 43 and the memory 41 Input-side FIFO memory 45, output-side FIFO memory 46 for adjusting the timing of transfer data between the memory 41 and the synchronization signal reproduction circuit 44, and the leading pixel of each frame image stored in the memory 41 And a register 47 for storing address data of the data. FIG. 1 shows a configuration for one color among four sets of image data of red, green, blue, and infrared, and a similar circuit is provided for the other colors.

Each of these circuits, except for the memory 41, is configured as a logic circuit by CPLD (Complex Programmable Logic Device). The memory 41 is configured using a memory module (DRAM) for a personal computer.
Also, the register 47 stores the address data of the data for the leading pixel of the frame image. In the present embodiment, the frame position signal specifies the leading pixel of the frame image as described above. It is possible to store the address data of the data for the pixel at the rear end of the frame image as long as it can be identified and the position where the target frame image exists in the memory 41 can be specified. However, the address data having a certain relationship with the address data of the data at the leading or trailing pixel may be used.

The memory control circuit 42 is designated with a write address counter 42a for designating a write address of data to the memory 41 and an address for reading data from the memory 41 in order to operate writing and reading of data to and from the memory 41 in a FIFO format. As a basic FIFO operation, the write address counter 42a counts up as data is written from the input side FIFO memory 45 to the memory 41, and the count value of the write address counter 42a is set. While the read address counter 42b counts up until it catches up or reaches the rear end of the frame image, data writing to the memory 41 and data reading from the memory 41 are executed.
During this time, the memory control circuit 42 uses the data bus of the memory 41 for data writing or data reading depending on the data accumulation status in the input-side FIFO memory 45 and the output-side FIFO memory 46. The data output from the input side FIFO memory 45 is monitored, and if there is data indicating the leading pixel of the frame image, the count value of the write address counter 42a at that time is registered in the register 47. Remember me.

In addition to the basic FIFO operation as described above, the memory control circuit 42 is configured to respond to a re-transmission request for a frame image that has already been transmitted from the subsequent circuit.
That is, for example, when the paper of the photographic paper 1 is temporarily generated in the exposure / development apparatus EP, and the image data sent from the subsequent circuit to the exposure / development apparatus EP is lost before printing. If there is a processing error in the latter circuit itself and data is lost, the memory control circuit 42 is designated when the retransmission request is sent from the latter circuit to the memory control circuit 42. The address data of the pixel at the tip of the frame image is read from the register 47 and loaded into the address counter 42b, and the above-described FIFO operation is resumed. As a result, data reading is restarted from the leading end of the lost frame image.
The address data loaded from the register 47 to the read address counter 42b is transmitted to the subsequent circuit via the driver 48 and is used for the subsequent circuit. Further, the count value of the read address counter 42b is also output via the driver 49, and similarly used for the subsequent circuit.

The write data generation circuit 43 inputs the frame position signal and the line position signal for organizing the frame position signal and the line position signal input together with the frame image into data writable in the memory 41 together with the image data. By assigning data values other than the data values that can be taken by the image data, the image data is generated as data having the same bit length as that of the image data stored in the memory and separate from the image data.
In the present embodiment, the case where the bit length of the image data input to the frame image buffer device 32 is 16 bits is exemplified, and the bit length of the data generated by the frame position signal and the line position signal is also shown. 16 bits.
The 16-bit image data input to the frame image buffer device 32 is a circuit located on the upstream side of the frame image buffer device 32, and 12-bit image data is expanded to 16 bits by log conversion processing. Some restrictions are added to the maximum output result of this log conversion process.

That is, in the log conversion process of Dout = ln Din × K (ln: natural logarithm, Din: input image data value, K: constant, Dout: output image data value), the constant “K” is set to ln 4095 × K = By setting the value to satisfy the relationship of 65532, the maximum value of the image data input to the frame image buffer device 32 is limited to 65532.
As a result, two of the three data values “65533”, “65534”, and “65535” are used as information for specifying the pixel at the leading edge of the frame image, and the pixel at the leading edge of the horizontal scanning line. Each can be assigned as information for identification.

  Assuming that the data value “65534” is assigned as information for specifying the leading pixel of the frame image, and the data value “65535” is assigned as information for specifying the leading pixel of the horizontal scanning line. When the frame position signal indicating the leading pixel is received, the data value “65534” is inserted before the image data of the leading pixel, and when the line position signal indicating the leading pixel of the horizontal scanning line is received, A data value “65535” is inserted before the image data of the leading pixel.

On the other hand, the sync signal reproduction circuit 44 detects the data value “65534” in the data input from the output side FIFO memory 46 in accordance with the data generation rule of the write data generation circuit 43 described above, and outputs the frame position signal. The line position signal is reproduced as the data value “65535” is detected.
However, it is not always necessary to reproduce the frame position signal and the line position signal input to the write data generation circuit 43 as they are, but to process and reproduce the signal form suitable for processing in the subsequent circuit. It may be.

[Schematic configuration of exposure / development apparatus EP]
The exposure / development apparatus EP functions as a printing apparatus PE that produces a photographic print based on the image data processed by the data processing apparatus IP. As shown in FIG. An exposure unit 20 that exposes and forms an image of image data for exposure received from the input device IR on the photographic paper 1, an exposure control device 21 that controls the exposure unit 20, and the photographic paper 1 that is exposed by the exposure unit 20. A developing processing device 22 for developing the photographic paper, and a photographic paper transport system PT for transporting the photographic paper 1 drawn out from the photographic paper magazine 23 arranged on the upper surface of the housing to the developing processing device 22 by a number of transport rollers 25 and the like. Is provided. The exposure unit 20 includes an exposure head 20a in which PLZT micro light shutters are arranged in a line, and adopts a PLZT light shutter system.
As shown in FIG. 6, a sorter 26 for classifying the photographic paper 1 developed and dried by the development processing device 22 by order and a discharge port 22a are provided outside the housing of the exposure / development device EP. And a conveyor 27 that conveys the photographic paper 1 discharged from the printer 1 to the sorter 26.
Further, a cutter 28 for cutting the long photographic paper 1 drawn from the photographic paper magazine 23 into a set print size is provided in the middle of the conveyance path of the photographic paper conveyance system PT.

[Photo print production operation]
Next, a photographic print production operation by the photographic print system DP having the above configuration will be schematically described.
When the operator inputs an instruction to make a photographic print for a photographic film frame image, the main controller 6 instructs the film scanner 2 to read the photographic film, and the image data of the photographic film is sent from the film scanner 2. Are sequentially received and subjected to image processing including the above-described processing by the image processing apparatus 11 and recorded in a memory built in the controller 12.
On the other hand, when the operator inputs an instruction to produce a photographic print for image data recorded on a recording medium such as a memory card, MO, or CD-R, the main controller 6 drives the corresponding drive of the external input / output device 4. The image data is instructed to be read, and the image data is sequentially received from the drive and recorded in the memory of the controller 12.

The main control device 6 displays the simulated image obtained by the simulation calculation unit 10 on the monitor 6a based on the input image data.
The operator observes the simulated image on the monitor 6a and appropriately inputs image correction instruction information from the console 6b.
The main control device 6 generates image data for exposure in the image processing device 11 in a state where the input image correction instruction information is reflected, and sends it to the exposure control device 21.
When the exposure control device 21 detects that the front end of the photographic paper 1 has been conveyed to a predetermined exposure start position based on the conveyance information of the photographic paper 1 obtained from the photographic paper conveyance system PT, the exposure unit 20 The image data for exposure is sequentially transmitted to the exposure unit 20 at a speed corresponding to the exposure processing speed.
The exposure unit 20 operates each optical shutter of the exposure head 20a based on the received exposure image data to form a latent image of the print image on the photographic paper 1.
The photographic paper 1 subjected to the exposure processing in the exposure unit 20 is transported to the development processing device 22 by the photographic paper transport system PT, and is developed by sequentially passing through the respective development processing tanks. After being further dried, it is discharged from the discharge port onto the conveyor 27 and collected by the sorter 26 for each order.

[Another embodiment]
Hereinafter, other embodiments of the present invention will be listed.
(1) In the above embodiment, the frame image buffer device 32 of the present invention is arranged between the film scanner 2 and the processing module MD of the image processing device 11 in the photographic print system DP to buffer the frame image. However, the present invention can be applied to various uses in which the size and aspect ratio of an image to be handled are not limited to those related to a photographic processor.
(2) In the above embodiment, the write data generation circuit 43 organizes the frame position signal and line position signal input together with the frame image into data writable in the memory 41 together with the image data. In the example, the signal and the line position signal are generated as data having the same bit length as that of the image data stored in the memory and separate from the image data. When the bit length of data to be read / written to / from 41 is 16 bits, data corresponding to the frame position signal and the line position signal is generated using 2 bits, and the remaining 14 bits are used for image data For example, the frame position signal and the line are included in one data read / written to / from the memory 41. The information and the image data corresponding to the position signal may be configured to mix.
(3) In the above embodiment, a circuit that executes image processing is exemplified as a subsequent circuit of the frame image buffer device 32. However, the synchronization signal as described with reference to FIG. The present invention can also be applied to a case where the circuit to be used is a subsequent circuit.

The block block diagram of the frame image buffer apparatus concerning embodiment of this invention The figure for demonstrating the synchronizing signal of a frame image Diagram for explaining reading of frame image of photographic film Main part block block diagram concerning embodiment of this invention 1 is a block configuration diagram of a photo print system according to an embodiment of the present invention. 1 is an external perspective view of a photographic print system according to an embodiment of the present invention.

Explanation of symbols

41 Memory 42 Memory Control Circuit 43 Write Data Generation Circuit 44 Synchronization Signal Reproduction Circuit 47 Register

Claims (3)

A frame image buffer device provided with a memory for storing image data of a frame image input in a raster scanning state, and a memory control circuit for writing and reading image data to and from the memory in a FIFO format Because
A frame position signal for specifying the leading or trailing edge pixel of the frame image and the line position for specifying the leading or trailing edge pixel of each horizontal scanning line of the frame image, which are input together with the frame image. A write data generation circuit that organizes signals into data that can be written to the memory together with the image data;
When the frame position signal is received, data correspondingly generated by the write data generation circuit is written to the memory, and when the line position signal is received, data correspondingly generated by the write data generation circuit is written. Is configured to write to the memory ;
A register is provided for storing address data of data about the leading or trailing pixel of each frame image stored in the memory or address data having a certain relationship with the address data,
The memory control circuit is configured to load address data stored in the register in accordance with a request from a subsequent circuit, and to read and output data from the front end of the frame image specified by the address data. Frame image buffer device.   2. The frame image buffer device according to claim 1, further comprising a synchronization signal reproduction circuit that reproduces the frame position signal and the line position signal based on data read from the memory. The write data generation circuit assigns the frame position signal and the line position signal to a data value other than a data value that can be taken by the input image data, thereby obtaining a bit length of the image data stored in the memory 3. The frame image buffer device according to claim 1 , wherein the frame image buffer device has the same bit length and is generated as data separate from the image data .

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