JPH11187358A - Time axis correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a time axis correcting device capable of precisely executing time axis correction by a simple circuit. SOLUTION: The time axis error of a input picture signal is detected from a digital signal by a time axis error detecting circuit 3 to execute the clock time axis correction (phase correction) of a clock generation circuit 1 according to this time axis error. This circuit 1 generates a basic clock synchronized with the input picture signal by a period longer than the horizontal line period of the input picture signal. By controlling the respective parts of an A/D converter 2, a memory control circuit 5 and a read clock generation circuit 6 by this basic clock, the write and read clock of a memory 4 is generated for time axis correction of a read signal from the memory 4. As a time axis error detecting circuit 3 consists of a digital circuit and generates this error-corrected basic clock by digital processing, the circuit 3 never receives influence from the variation of a circuit element, temperature variation, etc., unlike an analog circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correcting apparatus, and more particularly to a time axis correcting apparatus for correcting a time axis fluctuation of a reproduced signal in a signal reproducing apparatus such as a video tape recorder (VTR).

[0002]

2. Description of the Related Art In recent years, in a signal reproducing apparatus such as a VTR for broadcasting, a digital time axis correcting apparatus for correcting a time axis fluctuation of a reproduced signal has been widely known. The conventional example will be described below with reference to the drawings.

FIG. 11 is a schematic block diagram of a known time axis correction device. In the figure, the signal including time axis fluctuation is A
/ D converter 111 and write clock generation circuit 114, respectively. In the write clock generation circuit 114,
Generates a clock that follows the time axis fluctuation of the input signal.
The clock is supplied to the / D converter 111 and the memory control circuit 115. The A / D converter 111 samples the analog signal using a write clock that follows the time axis fluctuation, and temporarily stores the obtained digital signal in the memory 112.

On the other hand, a read clock generating circuit 116 generates a fixed clock having no time axis fluctuation, reads a signal stored from a memory 112 in synchronization with the fixed clock, and outputs the signal via a D / A converter 113. Thus, the time axis is corrected.

[0005] In this method, an analog circuit for generating a write clock following the time axis fluctuation of the input signal is necessary. Therefore, the accuracy of the time axis correction is affected by variations in circuit elements of the analog circuit and temperature changes. Is affected.

A write clock generation circuit 114 performs a phase comparison with a synchronization signal or a color subcarrier of an input signal, and applies a comparison error as a control signal to a VCXO (voltage controlled oscillator) PLL (phase locked loop) circuit. However, trying to follow the sudden change in the phase of the horizontal synchronization signal and color subcarrier of the input signal,
If the gain is increased and the time constant of the PLL circuit is reduced, the tracking performance is improved, but there is a disadvantage that the steady jitter increases and the stability of the write clock frequency deteriorates.

As an example of solving such a drawback, a configuration using a method of interpolating time axis correction by digital signal processing has been proposed in Japanese Patent Laid-Open No. 2-10979, and the configuration is shown in FIG. In the figure, a clock generation circuit 125 generates a clock having a fixed cycle and supplies it to each unit. A time axis error detection circuit 124 detects a time axis error, an interpolation circuit 122 interpolates a signal amplitude based on the time axis error to obtain an interpolation signal, and a D / A converter 123 converts the signal into an analog signal and outputs the signal. I do. The A / D converter 12
Numeral 1 digitizes an input signal by a clock.

[0008]

However, FIG.
In the conventional configuration shown in (1), a highly accurate time axis correction can be performed, but a multiplier for multiplying each tap by each coefficient is required for interpolation. It is necessary to increase the number of taps of the interpolation filter to improve the characteristics, and accordingly, the number of multipliers is increased, and a time axis correction circuit capable of performing highly accurate time axis correction with a simple circuit is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a time axis correction device capable of performing highly accurate time axis correction with a simple circuit.

[0010]

According to the present invention, A / D conversion means for converting an input image signal into a digital signal,
Storage means for storing the digital signal; time axis error detection means for detecting a time axis error of the image signal from the digital signal to generate time axis error information; and a time axis correction based on the time axis error information. A read clock generating means for generating a read clock, and a D / A converting means for converting a digital signal read from the memory into an analog signal based on the read clock. Can be

The read clock generating means includes:
A means for generating a basic clock synchronized with the image signal in a cycle longer than the horizontal line cycle of the input image signal; a means for generating phase angle information of the basic clock based on the time axis error information; Means for generating a read clock according to the information.

According to the present invention, a storage means for storing a digital signal of an input image signal, and a time axis error detection for detecting a time axis error of the image signal from the digital signal to generate time axis error information Means, a write clock generating means for generating a write clock whose time axis is corrected based on the time axis error information, and A / D conversion means for converting the input image signal into the digital signal based on the write clock. A time axis correction device characterized by including the above is obtained.

The write clock generating means includes:
Means for generating a basic clock synchronized with the image signal in a cycle longer than the horizontal line cycle of the input image signal;
It is characterized by comprising means for generating phase angle information of the basic clock based on the time axis error information, and means for generating a write clock according to the phase angle information.

Further, according to the present invention, there is provided a time axis correcting apparatus for correcting the time axis of the image signal by sequentially writing a digital image signal to a memory based on a write clock and sequentially reading the digital image signal based on a read clock. A time axis error detecting means for detecting a time axis error from an image signal converted into a digital signal and outputting time axis error information; and detecting a phase angle of an angular velocity of the read clock based on the time axis error information. Clock generation means for obtaining a phase angle obtained by correcting the time axis by correction, and generating a clock from the phase angle, and D / A conversion means for converting a read signal from the memory into an analog signal by a clock generated from the clock generation means. And a time axis correction device characterized by including the following.

Still further, according to the present invention, the digital image signal is sequentially written to the memory based on the write clock while being sequentially read based on the read clock, whereby the time axis of the image signal is corrected. A correction device, a time axis error detecting means for detecting a time axis error from an image signal converted into a digital signal and outputting time axis error information, and an angular velocity of the write clock based on the time axis error information. A clock angle generating means for generating a clock from the phase angle, and an A / A converter for converting the input image signal into a digital signal based on the clock generated from the clock angle generating means. A time axis correction device including D conversion means is obtained.

The operation of the present invention will be described. Time-axis fluctuation information is obtained from an input digital signal obtained by digitally converting an input image signal, a read clock with a corrected time axis is generated, and a digital signal is read from the memory while the memory read time is corrected with time. Therefore, an interpolation circuit by digital processing is not required, and a clock that follows the time axis fluctuation of the input signal is not required. Since the configuration is such that a clock that follows the time axis fluctuation is generated, an analog circuit is also unnecessary.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, an input image signal including a time axis fluctuation input to an input terminal 9 is supplied to a clock generation circuit 1 and an A / D converter 2. Although the input image signal includes time axis fluctuations, it is assumed that the average number of lines and the average frame frequency satisfy NTSC television signal standards.

The clock generation circuit 1 generates a write clock having a constant frequency in synchronization with an input signal. The purpose of synchronizing the write clock with the input signal is not to follow the time axis fluctuation of the input signal, but to simplify the subsequent processing by keeping the number of pixels per line constant. Synchronize with the input signal. Therefore, instead of following the time axis fluctuation of the input signal,
The time constant is made sufficiently large and the gain is made small to constitute a PLL circuit so that a clock having a stable frequency synchronized with the line frequency averaged for a long time is generated.

The frequency fs of the write clock, ie, the sampling clock, is N times the average horizontal frequency fh (fs = N ·
fh). In this embodiment, N = 910, that is, four times the average color subcarrier frequency fsc. The cycle of the sampling clock is T = 1 / fs. The write clock is A / D converter 2, time axis error detection circuit 3, memory control circuit 5, read clock generation circuit 6,
Supplied to

The A / D converter 2 converts an input signal including a time axis fluctuation into a digital signal with a stable write clock and supplies the digital signal to a memory circuit 4 and a time axis error detection circuit 3.
The time axis error detection circuit 3 detects a time axis error from a synchronization signal or a color burst signal of the input digital signal, and reads out the time axis error information and supplies it to the read clock generation circuit 6. The memory circuit 4 temporarily stores an input signal digitized according to a signal from the memory control circuit 5. The memory control circuit 5 controls to write or read a digitized image signal to or from a memory according to a write clock and a read clock.

The read clock generating circuit 6 generates a read clock at a timing obtained by correcting the time phase of the write clock by the value of the time axis error based on the time axis error information. The D / A converter 7 converts the digital image signal read from the memory circuit 4 into an analog signal with the read clock whose time axis has been corrected, and outputs the analog signal.

Next, the principle of correcting the time axis fluctuation will be described with reference to FIG. When the horizontal synchronization of the luminance signal is observed, a delay occurs on the time axis by Δ in the following lines with respect to the and lines. In this case, since the period of the sampling clock is T, the line is Δ /
This means that the number of clocks of T is delayed. To correct the time axis, it is only necessary to read out earlier by the clock of Δ / T. Δ /
The value of the integer value of T is read earlier by the number of clocks, and the value below the decimal point is subjected to time axis correction by shifting the phase of the clock. Of the time axis error information, information to be corrected by the number of clocks is directly sent to the memory control circuit 5 as correction information.

When a time axis error is detected based on a color burst signal, the time axis correction is similarly performed. fs = 4
Since it is twice as high as fsc, normal NT with no time axis fluctuation
In the case of an SC signal, since the phase of the subcarrier is inverted for each line, the subcarrier components of the sample values of the color burst at the same distance from the horizontal synchronization have the same amplitude and the polarity is inverted for each line. Will be. This is set as a reference phase. The phase of the color subcarrier for each line is obtained from the digital signal value of the color burst section of the image signal including the time axis fluctuation, and the deviation from the reference phase is obtained.

The phase correction of the color subcarrier will be described with reference to FIG. In the line with respect to the line, the phase is just inverted, but in the line, the phase of the color subcarrier is delayed by θ from the inverted phase. For the color burst phase of the line
The phase angle of the subcarrier of the image signal is changed from the reference phase to the phase angle θ (= 2π · f) by the time axis fluctuation in the time axis error detection circuit.
sc.t), that is, when it is detected that the time t = .theta ./ (2.pi..multidot.fsc) is delayed, it is supplied to the read clock generation circuit as time axis error information, and control is performed by the memory control unit. When the image signal is read out from the memory and reproduced, the signal is read out earlier by the time t and D / A converted. As a result, the phase of the color subcarrier of the image signal to be analog-converted is corrected correctly and output.

FIG. 4 shows a case where the continuity of the image signal is deteriorated by switching the field because the track is scanned for each field in the VTR. Is a correct signal, it is assumed that discontinuity occurs when the head is switched, and a time delay occurs in the middle of the 520th line as shown in FIG.
After the 521 line, the image signal shifts backward and is delayed, and as it is, discontinuity is seen on the screen, and the image quality is greatly deteriorated.

The same correction processing as described with reference to FIG. 2 is performed. That is, the time axis error detection circuit 3 detects the delay time Δ as time axis error information, divides it into the clock number of the integer part of Δ / T and the decimal point part, and sends the error of the integer part to the memory control circuit 5 as it is. The error of the decimal part is generated by a read clock generation circuit 6 which generates a read clock whose delay time has been corrected, reads out the memory circuit 4 earlier by a time Δ and converts it into an analog signal, thereby obtaining a corrected image signal.

FIG. 5 shows a configuration example of the clock generation circuit 1. The clock generation circuit 1 includes a synchronization separation circuit 11 and a VCXO
It comprises a circuit 12 and a PC circuit 13. Sync separation circuit 11
Separates the horizontal synchronization signal and the color burst signal from the input signal. The VCXO circuit 12 generates a clock in phase synchronization with horizontal synchronization or color burst. In order to generate a stable clock, the time constant is increased or the loop gain of the PLL is reduced so as not to sensitively follow the fluctuation of the input signal. A PG (pulse generator) circuit 13 supplies a clock and a reference horizontal synchronization signal obtained by dividing the clock, and also generates and supplies necessary pulse signals.

FIG. 6 illustrates a detection method of the time axis error detection circuit 3. A delay time Δ from the reference horizontal synchronization signal H to a point 50% of the horizontal synchronization signal of the image signal is calculated.
Assuming that sample points in the horizontal synchronization portion of the image signal are indicated by circles and the value of each sample point is Xi, it is a level intermediate between the blanking level (X1 and X2) and the synchronization start level (X4 and X5). Estimate the sampling time of the marked point. X3 and X4
The position of the point で き can be estimated from the value of, and the delay time Δ from the reference horizontal synchronization signal H is calculated.

FIG. 7 illustrates another detection method of the time axis error detection circuit 3. The phase of the color burst is detected with reference to a sample point separated by a predetermined number from the reference horizontal synchronization signal H. Since the sampling frequency is set to four times the average color subcarrier frequency, the angular velocity of the sampling period is π / 2, that is, 90 degrees (π /
The phase of 2) is advanced. Since the number of sample points in one line is 910, the phase advances by 180 degrees at the same sample point in the next line. The amplitude of the color subcarrier is C, the angular velocity of the sampling period is π / 2,
Assuming that the delay phase angle of the subcarrier is θ, the sample value of the i-th sample point of the sample point indicated by a circle is Ci = C · sin
(I · π / 2−θ).

At the sampling point of the color subcarrier in FIG. 7, the phase angle θ of the phase delay is 0 degree in the reference line, and Ci = C · sin (i · π / 2). Therefore, when the amplitude value of the subcarrier component at the sample point in the color burst section of the digitized image signal is obtained, the sample values of C1, C3, C5, and C7 of the sample points should be zero. When a time axis error occurs and the phase delay shifts by θ, as shown by the lines, C1, C3, C5, C5
The value of 7 will not be 0.

When i = 1 and 2, there is the following relationship: C1 = C · sin (π / 2−θ) C2 = C · sin (π−θ)

Equation of trigonometric function sin (A + B) = cosA
Using sinB + cosB · sinA, C1 = C · sin (π / 2−θ) = C · (cos (π / 2) · sin (−θ) + cos (−θ) · sin (π / 2)) = −C · cos θ C2 = C · sin (π−θ) = C · (cos (π) · sin (−θ) + cos (−θ) · sin (π)) = − C · sin θ

From both equations, tan (θ) = C2 / C1, that is, the value of θ can be obtained from the values of C1 and C2 by referring to the inverse table of the trigonometric function. C1 and C
Not just two sample points, but two consecutive two sample values,
For example, the phase angle θ of the phase delay can be obtained in the same manner from C2 and C3 or from C3 and C4. If the phase angle is obtained not only at two points but also at an average value from many points, Although the number of calculation processes increases, the accuracy of the phase angle θ can be increased.

FIG. 8 shows a configuration example of the read clock generation circuit 6. It has a function of generating a read clock whose phase is corrected by the delay phase angle. The basic clock circuit 21 generates a basic clock fb = M / L.fs which is at least twice as large as the sampling clock fs. By synchronizing the basic clock with the sampling clock, there is a temporal variation, but on average, the number of data written to the memory circuit matches the number of data read. Assuming that M = 4 and L = 1, a basic clock 4fs which is four times the sampling clock is generated and supplied to the phase angle generator 23. The angular velocity generator 22 generates an angular velocity ω at which the phase angle of the sampling clock advances in the period of the basic clock, and supplies it to the phase angle generator.

The angular velocity is given by ω = 2 · π · L / M,
In this case, it is π / 2. The phase angle generator 23 generates a phase angle 読 出 of the read clock for each basic clock. The phase angle advances by an angular velocity ω = π / 2 for each basic clock, and the initial phase is corrected to a phase angle advanced by the delay phase angle θ. That is, the phase angle of the read clock at the j-th basic clock is given by ψ = ω · j + θ.

FIG. 9 shows a configuration example of the clock generator 24 of the clock generation circuit 6. The clock generator 24 has a phase angle ψ
Generates a read clock whose delay time has been corrected.
The sine wave table 31 has a conversion table (ROM) for outputting a PCM sine wave having an amplitude of 8 bits corresponding to an angle value of one cycle from 0 to 2π, and corresponding to the input phase angle ψ. A PCM sine wave is output and supplied to the D / A circuit 32.

The D / A circuit 32 is an 8-bit sine wave PC.
The M signal is converted into an analog signal, output, and supplied to the rectangular wave circuit 33. The rectangular wave circuit 33 amplifies the amplitude of the sine wave and converts the sine wave into a rectangular wave by performing clipping to generate a read clock in which the delay phase angle θ is corrected. The phase angle is represented by a binary number, and 2π is expressed by 10 bits, and an arithmetic process of obtaining an angular velocity ω by a 10-bit modulo operation is performed. 2π is 1024, π is 512, and π / 2 is represented by 256. The angular velocity advances by π / 2, that is, by 256 every cycle of the basic clock.

When it is necessary to reduce the memory size in LSI or the like, if the characteristics of the trigonometric function are used, 0 to π
If there is a sine wave conversion table of / 2, then by using addition and subtraction, a sine wave for a phase angle from 0 to 2π can be obtained, and the size becomes １ ／.

Another configuration example of the configuration of the clock generation circuit 1 of FIG. 5 will be described. The basic clock circuit 21 of the read clock generating circuit 6 in FIG. 8 needs a function of generating a basic clock four times the sampling clock. Therefore, in FIG. 5, the VCXO circuit 12 does not generate the sampling clock fs, but has a function of generating a basic clock fb four times as large as fs.

In the PG circuit 13, the basic clock fb is reduced to 1 /
The sampling clock fs is obtained by dividing the frequency by 4 and supplied to each unit. The basic clock fb is directly supplied to the phase angle generator 22 in the configuration diagram of the read clock generator shown in FIG.
That is, the VCXO circuit 12 of FIG. 5 and the basic clock circuit 21 of FIG. 8 can be combined into one VCXO circuit, and the basic clock circuit 21 of FIG. 8 can be unnecessary.

The configuration of the memory circuit 4 will be described. When the average number of data for writing and reading does not match, the memory circuit 4 needs to synchronize the frames by using two frames of memory (the NTSC signal has two frames in phase). If the clocks for writing and reading are synchronized on average, even if there is a large time distortion in the V synchronization section, it is sufficient to have a memory for time correction for at most one line. Is estimated to be not so large.

However, the processing time from the time when the error is detected by the time axis error detection circuit 3 to the time when the read clock is generated by the read clock generation circuit 6 needs to delay the image signal, and the memory circuit 4 requires extra time. Memory capacity is required.

FIG. 10 shows the configuration of the second embodiment of the present invention. In this embodiment, a write clock is generated by correcting a sampling clock for A / D conversion from a digital signal using a delay error θ detected as a time axis error, and sampling is performed using this clock. That is, the feedback loop is configured to correct the time axis error. The write clock circuit 8 has the same function as the read clock circuit 6 of FIG.
Generates a write clock in which the time error is corrected. Other blocks have the same functions as the blocks in FIG.

The clock generation circuit 1 generates a basic clock fb and a sampling clock fs synchronized with an input signal. The sampling clock fs is N times the averaged horizontal synchronizing signal fh,
For example, the frequency of N = 910 and the basic clock are set to four times the frequency (fb = 4 · fs).

In the case of the configuration of the time axis error correction control by the feedback loop of the second embodiment, the time axis error detection by the horizontal synchronizing signal can be compared only at one point of the synchronization edge in the line, and the correction of that part is performed. Since the synchronization signal used as the reference for comparison can be configured digitally,
If the configuration is such that the synchronous part is replaced, the time axis can be corrected with higher accuracy.

Also in the case of the first embodiment, the television signal output from the VTR is a synchronous signal or a color burst signal having N signals.
It may be distorted with respect to the TSC signal standard,
If the reference synchronization signal is newly replaced in order to reduce the influence of the distortion on the subsequent device, the waveform distortion of the synchronization signal and the like can be improved.

[0048]

As described above, according to the present invention, the time axis correction detection circuit is digitally configured and a clock in which the detected error is corrected is generated by digital processing. A stable and highly accurate time axis correction can be performed without receiving. Further, since the clock is generated by shifting the time to the time at which the time axis error is corrected, it is not necessary to obtain data between the clocks by an interpolation circuit by an interpolation process, and a digital filter for the interpolation process is not required. In the conventional example shown in FIG. 12, even if it is possible to implement an LSI, in order to construct a high-performance interpolation filter extending flat to a 4.2 MHz band, the number of stages of the interpolation filter becomes very large, and a large scale Although this is an LSI, the present invention does not require an interpolation filter and the configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram for explaining a time axis error of a horizontal synchronization signal and its correction.

FIG. 3 is a diagram for explaining a time axis error of a color burst signal and its correction.

FIG. 4 is a diagram for explaining a time axis error near a V synchronization signal section and its correction.

FIG. 5 is a diagram showing a specific configuration of a clock generator 1 of FIG. 1;

FIG. 6 is a diagram illustrating a method of detecting a time axis error using a horizontal synchronization signal.

FIG. 7 is a diagram illustrating a detection method of detecting a time axis error using a color burst signal.

8 is a diagram showing a specific example of the read clock generation circuit 6 of FIG.

9 is a diagram showing a specific example of the clock generator 24 of FIG.

FIG. 10 is a block diagram of another embodiment of the present invention.

FIG. 11 is a diagram illustrating an example of a conventional time axis correction device.

FIG. 12 is a diagram showing another example of the conventional time axis correction device.

[Explanation of symbols]

 Reference Signs List 1 clock generation circuit 2 A / D converter 3 time axis error detection circuit 4 memory circuit 5 memory control circuit 6 read clock generation circuit 7 D / A converter 8 write clock generation circuit 9 input terminal 10 output terminal 11 synchronization separation circuit 12 VCXO circuit 13 PG circuit 21 Basic clock generation circuit 22 Phase angle generator 23 Angular velocity generator 24 Clock generator 31 Sine wave table 32 A / D conversion circuit 33 Rectangular wave circuit

Claims (6)

[Claims] 1. An A / D converter for converting an input image signal into a digital signal, a storage means for storing the digital signal, and detecting a time axis error of the image signal from the digital signal to obtain time axis error information. , A read clock generating means for generating a read clock whose time axis is corrected based on the time axis error information, and converting a digital signal read from the memory into an analog signal based on the read clock. And a D / A conversion means for converting. 2. The read clock generating means includes: means for generating a basic clock synchronized with the input image signal in a cycle longer than a horizontal line cycle of the input image signal; 2. The time axis correction device according to claim 1, further comprising: means for generating phase angle information; and means for generating a read clock according to the phase angle information. 3. A storage means for storing a digital signal of an input image signal, a time axis error detection means for detecting a time axis error of the image signal from the digital signal and generating time axis error information, Write clock generating means for generating a write clock whose time axis is corrected based on the error information, and A / D converting means for converting the input image signal into the digital signal based on the write clock. Time axis correction device. 4. A writing clock generating means for generating a basic clock synchronized with the image signal in a period longer than a horizontal line period of the input image signal, and the basic clock based on the time axis error information. 4. The apparatus according to claim 3, further comprising: means for generating phase angle information, and means for generating a write clock according to the phase angle information.
The time axis correction device as described. 5. A time axis correction device for performing time axis correction of an image signal by sequentially writing a digital image signal to a memory based on a read clock while sequentially writing a digital image signal to a memory based on a write clock. A time-axis error detecting means for detecting a time-axis error from the image signal converted to and outputting time-axis error information; and correcting a phase angle of an angular velocity of the read clock based on the time-axis error information to obtain a time-axis error. And a D / A converter for converting a read signal from the memory into an analog signal by a clock generated from the clock generator. Characteristic time axis correction device. 6. A time axis correction device for sequentially writing a digital image signal to a memory based on a write clock and sequentially reading the digital image signal based on a read clock to thereby correct the time axis of the image signal. A time-axis error detecting means for detecting a time-axis error from the image signal converted to and outputting time-axis error information; and correcting a phase angle of an angular velocity of the write clock based on the time-axis error information to obtain a time-axis error. And a A / D converter for converting the input image signal into a digital signal based on a clock generated from the clock generator. Characteristic time axis correction device.