JP3082292B2 - Time axis correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device suitable for application to, for example, a digital time axis correction device called an open TBC (time base collector).

[0002]

2. Description of the Related Art Conventionally, a reproduced video signal is written in a memory by a write clock, and the reproduced video signal written in the memory is read out by a read clock to correct a time axis error such as a jitter of the reproduced video signal. Digital time base correction device
It is mounted on players, video tape recorders, etc. The digital time axis correction apparatus is roughly classified into a so-called closed TBC (time base collector) and an open TBC (time base collector). In the closed TBC, the frequency of the write clock is varied according to the synchronization signal of the reproduced video signal, and the read clock is a fixed clock signal synchronized with the reference signal. On the other hand, in the open TBC, the frequency of the write clock is changed according to the synchronization signal of the reproduced video signal, and the read clock is obtained by comparing the phase of the burst signal of the reproduced video signal with the burst signal of the reference video signal. It is made variable based on a given error signal (velocity error signal).

FIG. 3 shows a time axis correction device called an open TBC. In FIG. 3, reference numeral 1 denotes an input terminal to which a reproduced video signal is supplied, and a reproduced video signal reproduced through the input terminal 1 is supplied to an AD converter 2. The A / D converter 2 converts a reproduced video signal supplied via the input terminal 1 into a digital video signal based on a write clock from a write clock generating circuit 3 described later. The write clock generation circuit 3
A write clock is supplied to the D converter 2 and the line memory 7 to which the digital video signal is written.
The generation of the write clock by the write clock generation circuit 3 is performed as follows. That is, the reference synchronizing signal from the reference signal generating circuit 4 and the synchronizing signal of the digital video signal from the A / D converter 2 are compared in phase by the simultaneous signal phase comparing circuit 5, and the signal of this comparison result is written. Oscillation corresponding to the comparison result signal is supplied to the clock generation circuit 3.
It is done by being done by. Reference numeral 6 denotes a burst signal phase comparison circuit. The burst signal phase comparison circuit 6 has a phase between a reference burst signal from the reference signal generation circuit 4 and a burst signal in the digital video signal from the A / D converter 2. And supplies the result of the comparison to an interpolation circuit 9 described later as an error signal (velocity error signal). The interpolation circuit 9 performs primary and secondary interpolation of the error signal from the burst signal phase comparison circuit 6, and supplies the error signal after the interpolation to the read clock generation circuit 10. The read clock generation circuit 10 generates a read clock based on the error signal from the interpolation circuit 9 and supplies the generated read clock to the DA converter 11 and the line memory 7, respectively.

A digital video signal written to a line memory (for example, a so-called first-in / first-out memory) 7 by a write clock from a write clock generator 3 is read by a read clock from a read clock generator 10. D
-A converter 11 is supplied. On the other hand, the burst signal phase comparison circuit 6 compares the phase of the burst signal in the reproduced video signal converted into the digital signal with the phase of the burst signal in the reference video signal. Then, the comparison result is supplied to the interpolation circuit 9 as an error signal.
The error signal (0th order) supplied to the interpolation circuit 9 is subjected to, for example, linear interpolation (1st order) and further to curve interpolation (2nd order). The interpolated error signal is supplied to the read clock generation circuit 10. Then, the read clock generation circuit 10 generates a read clock having a frequency corresponding to the error signal, and supplies the read clock to the DA converter 11. Thus, DA converter 1
According to 1, the digital video signal from the video signal processing circuit 8 is converted into an analog video signal by the read clock from the read clock generation circuit 10. This analog video signal is supplied to the outside (for example, another circuit such as a video disk player) via the output terminal 12.

As described above, conventionally, a read clock is generated based on the result of comparison between the phase of the burst signal in the reproduced video signal and the phase of the burst signal in the reference video signal, and this read is performed. Reading the digital video signal written to the line memory 7 by the clock,
And by converting it to an analog video signal,
The so-called residual jitter is removed, thereby improving the accuracy of time axis correction.

[0006]

The above-described FIG.
As shown by a broken line in the time axis correction device, in the time axis correction device, for example, a separation circuit for luminance Y and chroma signal C, a field memory, a frame memory, a video signal processing circuit, an enhancer, etc. In many cases. However, when these video signal processing circuits 8 are arranged between the line memory 7 and the DA converter 11 of the conventional time axis correction device,
Due to the delay time caused by the processing time of the video signal processing circuit 8, the time axes of the video signal and the error signal cannot be matched, and there is a disadvantage that the correction characteristics of the time axis deteriorate. When a field memory or the like is used to adjust the time axis, for example, 263
Bytes (262.5 bytes) are required, resulting in inconvenience that the circuit scale becomes large and the price of the device becomes expensive.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is capable of preventing the deterioration of the correction characteristics of the time axis without increasing the circuit scale even if the delay time is caused by various circuits. It is intended to propose a correction device.

As shown in FIGS. 1 and 2, for example, the time axis correcting device of the present invention includes a reference signal generating circuit 4 for generating a reference synchronizing signal and a reference burst signal, and an analog / digital converter for converting a supplied video signal into a digital signal. Digital conversion circuit 2
And a memory 7 in which the digital signal from the analog / digital conversion circuit 2 is written, and a phase comparison between the synchronization signal of the digital signal from the analog / digital conversion circuit 2 and the reference synchronization signal from the reference signal generation circuit 4. Based on the result, this analog / digital conversion circuit 2
And a write clock signal generating circuit 3 for generating a write clock signal for the memory 7, a phase comparison between a burst signal of a digital signal from the analog / digital conversion circuit 2 and a reference burst signal from the reference signal generating circuit 4. An error signal generating circuit 6 for generating an error signal based on the result; a mixer 13 for superimposing an error signal from the error signal generating circuit 6 on a horizontal synchronization portion of the digital signal read from the memory 7; A signal processing circuit 8 that performs signal processing on a superimposed signal from the mixer 13
A separating circuit 14 for separating an output signal from the signal processing circuit 8 into a digital video signal and an error signal; and a digital / analog converting circuit for converting the digital video signal separated by the separating circuit 14 into an analog video signal. 11 and the digital / analog conversion circuit 1 based on the error signal separated by the separation circuit 14.
1 and a read clock signal generating circuit 10 for generating a read clock signal for the memory 7.

[0009]

According to the present invention described above, a mixer 13 for superimposing an error signal as a comparison result at a predetermined position of a reproduced video signal read from the memory 7, and a superimposed signal formed by the mixer 13 for reproducing a reproduced video signal A separation circuit 14 is provided to separate the reproduced video signal from the error signal after the signal processing of the reproduced video signal is performed on the superimposed signal from the mixer 13. Since the reproduced video signal is output and a read clock is generated based on the error signal, it is possible to prevent the deterioration of the time-axis correction characteristic due to the delay of various circuits.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the time axis correcting apparatus according to the present invention will be described below in detail with reference to FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, a mixer 13 is provided next to the line memory 7 described in FIG.
-The separator 14 is arranged before the A converter 11. The mixer 13 converts, for example, an 8-bit digital reproduced video signal read by the read clock from the line memory 7 with the read clock from the clock generator 10 into an 8-bit error signal from the burst signal system phase comparator 6. The signal (see FIG. 2B) is superimposed. this is,
For example, it corresponds to the horizontal synchronization portion of the reproduced video signal shown in FIG. 2A. In FIG. 2, the reproduced video signals a, b, and c correspond to the error signals e1, e2, and e3, respectively. The superimposed signal (mixed 8-bit data) is as shown in FIG. 2C. That is, error data (shown by hatching in FIG. 2C) preceding the reproduced video signal a is superimposed on the data sequence corresponding to the reproduced video signal a, and the reproduced video signal a is superimposed on the data sequence corresponding to the reproduced video signal b. Error data of the reproduced video signal b is superimposed on the data sequence corresponding to the reproduced video signal c, and the data sequence corresponding to the next reproduced video signal (not shown) of the reproduced video signal c is superimposed. Is superimposed with error data of the reproduced video signal c. Reference numeral 14 denotes a separator. The separator 14 is a digital video signal (video data) superimposed by the mixer described above.
And the error signal (error data) is again separated into a digital video signal and an error signal.

Now, as shown by a broken line in FIG.
The operation in the case where a video signal processing circuit 8 such as a separation circuit for luminance Y and chroma signal C, a field memory, a frame memory, a video signal processing circuit, an enhancer, etc., is arranged between the 3 and the separator 14 will be described. Line memory (for example, so-called first-in first-out memory)
The digital video signal written in 7 by the write clock from the write clock generator 3 is read by the read clock from the read clock generator 10 and supplied to the mixer 13. On the other hand, the burst signal phase comparison circuit 6 compares the phase of the burst signal in the reproduced video signal converted into the digital signal with the phase of the burst signal in the reference video signal. The comparison result is supplied to the mixer 13 as an error signal. The error signal is superimposed on the digital video signal by the mixer 13 as described above. The superimposed signal from the mixer 13 is supplied to the separator 14 via the video signal processing circuit 8. The separator 14 separates the superimposed signal from the video signal processing circuit 8 into an original digital video signal and an error signal, and converts the digital video signal into a digital signal.
The error signal is supplied to the interpolation circuit 9 while being supplied to the A converter 11. The error signal (0th order) supplied to the interpolation circuit 9 is subjected to, for example, linear interpolation (1st order) and further to curve interpolation (2nd order). The interpolated error signal is supplied to the read clock generation circuit 10. Then, the read clock generation circuit 10 generates a read clock having a frequency corresponding to the error signal, and supplies the read clock to the DA converter 11. Thus D
The -A converter 11 converts the digital video signal from the separator 14 into an analog video signal in accordance with the read clock from the read clock generation circuit 10. This analog video signal is supplied to the outside (for example, another circuit such as a video disk player) via the output terminal 12.

As described above, in this embodiment, the error signal is superimposed on the digital video signal read from the line memory 7 to form a superimposed signal, and then the above-described luminance Y and chroma signal C separation circuit, field memory The superimposed signal is supplied to a video signal processing circuit 8 such as a frame memory, a video signal processing circuit, and an enhancer, and the superimposed signal from the video signal processing circuit 8 is separated into an original digital video signal and an error signal by a separator 14. And the interpolation circuit 9
A read clock is generated based on the interpolated error signal, and a separator 1 is generated based on the read clock.
4 is converted to an analog video signal. For example, even if the video signal processing circuit 8 is a so-called line-correlated digital YC (luminance and chroma signal) separation circuit, a delay may occur. No (conventionally, 0.5 for 2 lines and 1 for 3 lines)
H) and a memory (field memory, frame memory, etc.) for adjusting the error signal system to the video signal system delay can be dispensed with, and the circuit arranged as the video signal processing circuit 8 It is not necessary to change the design of the time axis correction device each time. Therefore, it is not necessary to change the circuit or increase the circuit configuration by using a delay memory or the like.
It is possible to obtain a time axis correction device which is inexpensive and does not deteriorate the time axis correction characteristics.

It should be noted that the present invention is not limited to the above-described embodiment, but may take various other configurations without departing from the spirit of the present invention.

[0014]

According to the present invention described above, a superimposing circuit for superimposing an error signal as a comparison result on a predetermined position of a reproduced video signal read from a memory, and a superimposed signal formed by the superimposing circuit are reproduced. A separation circuit for separating the video signal and the error signal is provided, and after performing the signal processing of the reproduced video signal on the superimposed signal from the superimposition circuit, the separation circuit separates the reproduced video signal and the error signal, Since the reproduced video signal is output and the read clock is generated based on the error signal, the deterioration of the time axis correction characteristics due to the delay of various circuits can be prevented without increasing the circuit scale. There are benefits that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a time axis correction device according to the present invention.

FIG. 2 is a timing chart for explaining one embodiment of a time axis correction device of the present invention.

FIG. 3 is a block diagram showing an example of a conventional time axis correction device.

[Explanation of symbols]

 7 line memory 13 mixer 14 separator

Claims (1)

(57) [Claims] A reference signal generation circuit for generating a reference synchronization signal and a reference burst signal; an analog / digital conversion circuit for converting a supplied video signal into a digital signal; and a digital signal from the analog / digital conversion circuit. A memory to be written, and a write clock between the analog / digital conversion circuit and the memory based on a phase comparison result between a synchronization signal of a digital signal from the analog / digital conversion circuit and a reference synchronization signal from the reference signal generation circuit. A write clock signal generation circuit for generating a signal; and an error signal for generating an error signal based on a phase comparison result between a burst signal of a digital signal from the analog / digital conversion circuit and a reference burst signal from the reference signal generation circuit. Generating circuit and the error signal generating circuit A mixer that superimposes an error signal on a horizontal synchronization portion of the digital signal read from the memory; a signal processing circuit that performs signal processing of a superimposed signal from the mixer; and a digital video signal that outputs an output signal from the signal processing circuit. A separating circuit for separating a signal and an error signal, a digital / analog converting circuit for converting a digital video signal separated by the separating circuit into an analog video signal, and a digital / analog converter based on the error signal separated by the separating circuit. A time axis correction circuit comprising: an analog conversion circuit; and a read clock signal generation circuit that generates a read clock signal for the memory.