JPH03224382A - Time base error correction device - Google Patents

Abstract

PURPOSE:To prevent the deviation of a display picture by measuring a pulse width of a horizontal synchronizing signal separated from a 2nd video signal read from a memory, detecting a difference to a normal synchronizing signal width, setting a front edge of a reference decoding synchronizing signal and outputting the result as a 3rd video signal. CONSTITUTION:A horizontal synchronizing signal separator circuit 21 separates a horizontal synchronizing signal I of a video signal output H of a D/A converter 20 and gives the signal to a width detection circuit 22. The width detection circuit 22 detects a time width of the horizontal synchronizing signal I and gives a control signal according to the width to a phase adjustment circuit 23. The phase adjustment circuit 23 receives the control signal to output a reference composite synchronizing signal J equal to a time width of the horizontal synchronizing signal I by adjusting the time width of the horizontal synchronizing signal in the reference composite synchronizing signal G generated in advance at its front ridge. A replacement circuit 24 replaces a composite synchronizing signal of a waveform H with the composite synchronizing signal J generated separately while matching the trailing edge.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time axis error correction device suitable for a video tape recorder (hereinafter abbreviated as VTR).

Conventional technology In recent years, with the rapid development of semiconductor technology, large-scale digital circuits have been converted to LSIs, and A/Ds that can operate at video rates have become available.
, D/A converters can be realized at low cost, and consumer VT
Even in R, etc., it has become possible to perform time base correction (time base corrector) of a reproduced video signal using digital memory.

This conventional time axis correction device is a device that corrects fluctuations in the time axis caused by waveform disturbances of a horizontal synchronization signal of a reproduced video signal. - During boat fishing, the leading edge of the horizontal synchronization signal of the reproduced video signal is easily disturbed by the influence of the preceding video waveform. However, since the time reference for image display is the leading edge of the horizontal synchronization signal, fluctuations occur at the front and rear ends of the horizontal IH on the image plane. Regarding this time axis correction means, the following proposal has already been made, and that was to replace it with a horizontal synchronization signal with a well-defined waveform.

The conventional time axis correction device will be described below with reference to FIGS. 3 and 4.

As shown in the figure, the horizontal synchronizing signal separation circuit (H8S) 4 separates the horizontal synchronizing signal of the reproduced video signal a from the input terminal 1, and transfers the separated signal to the write clock generating circuit (W-CL).
K) 5 and write reset pulse generation circuit (R-R8T) 6
is supplied to. The write clock generation circuit 5 generates a write clock d which starts in phase synchronization with the trailing edge of the horizontal synchronization signal d.
is generated and supplied to an A/D converter (A/D) 2 and memory 3. Further, the write reset pulse generation circuit 6 generates a reset pulse C that is phase-synchronized with the trailing edge of the horizontal synchronization signal and supplies it to the memory 3.

The A/D converter 2 samples the reproduced video signal a at the timing of the write clock d using the reset pulse C as a time axis reference, and inputs the data to the memory 3.

On the other hand, the reference oscillator 8 generates a reference clock e and supplies it to the memory 3, the D/A converter 7, and the synchronization signal generation circuit 9. A synchronization signal generator 9 generates a reference reset pulse f and a reference composite synchronization signal g formed by frequency-dividing the reference clock e. A D/A converter (D/A) 7 converts the data in the memory 3 into a video signal and inputs it to the switching circuit 10. This data reading is performed at the timing of the reference clock e using the reset pulse f as a time axis reference.

The replacement circuit 10 replaces the composite synchronization signal of the video signal with the reference composite synchronization signal g generated by the synchronization signal generation circuit 9.

The operation of the above conventional configuration will be explained. Note that the waveforms in FIG. 4 show the output waveforms of each circuit block in FIG. 3, and the same signals correspond to the same symbols.

The principle of this operation is to replace the horizontal synchronizing signal with a distorted waveform of the reproduced video signal with another horizontal synchronizing signal with a regular waveform. However, this replacement is not possible in real time, and it is necessary to manipulate the waveform of the video signal by delaying it by at least the time width of the horizontal synchronization signal. As this delay means, it is possible to obtain a certain waveform delay by first A/D converting the reproduced video signal, writing it into the memory, reading the memory again, D/A converting it, and reproducing the waveform. can. This delay operation can be performed accurately by digital processing using a clock.

The reproduced video signal a input to the input terminal 1 is input to the A/D converter 2, and is sequentially sampled at the timing of the write clock d and converted into digital data. By sequentially writing the digital data into the memory 3 at the timing of the reset pulse C, the data in the memory 3 becomes each sample data of the video signal waveform starting from the trailing edge of the horizontal synchronizing signal.

When this data is read out sequentially according to the reference clock e at the timing of the reference reset pulse f and converted into an analog signal by the D/A converter 7, the output is the reproduced video signal a.
The waveform whose starting point is the trailing edge of the horizontal synchronization signal is delayed in time. This time delay is the time required for the A/D conversion, memory writing and reading, and D/A conversion. This delayed waveform is input to a replacement circuit 10, where the composite synchronization signal of the waveform and the separately generated composite synchronization signal g are replaced by matching their trailing edges. Since the composite synchronization signal g is formed based on the reference oscillator 8, its waveform is regular. Furthermore, since the waveform g is a composite synchronization signal that includes not only the horizontal synchronization signal but also the synchronization signal of the vertical blanking section, it is possible to replace the horizontal synchronization signal of the entire reproduced video signal with a regular waveform.

Problems to be Solved by the Invention In such a conventional configuration, the time width of the replaced horizontal synchronization signal is set to a standard value in advance by the synchronization signal generation circuit 9. For example, in the NTSC system, the standard 4.7μse
Let it be c. This time width does not necessarily match the time width of the horizontal synchronization signal of the original reproduced video signal. Therefore,
In a video signal waveform with a synchronization signal that is replaced by matching the trailing edge of the synchronization signal, the leading edge of the horizontal synchronization signal does not necessarily match the leading edge of the original synchronization signal, and a shift occurs. do.

On the other hand, when displaying images on a television screen, display operations are performed based on the leading edge of the synchronization signal. Therefore, with the video signal obtained with the above configuration, there is a problem in that the displayed image is shifted left and right by the time difference of the shift.

The present invention solves the above-mentioned problems, and while correcting the time axis error based on the trailing edge of the horizontal synchronization signal in the same manner as described above, the leading edge of the synchronization signal of the obtained video signal waveform is It is an object of the present invention to provide a time base error correction device that matches the leading edge of a synchronization signal.

Means for Solving the Problems In order to achieve the above object, the present invention provides a writing means for writing an inputted first video signal into a memory, a synchronization signal generation means for generating a reference composite synchronization signal, and a synchronization signal generation means for generating a reference composite synchronization signal, and a first video signal inputted from the memory. reading means for reading out the video signal of the second video signal at the timing of the reference composite synchronization signal and outputting it as a second video signal; and a time axis correction means for outputting the replaced third video signal, and the time axis correction means detects the time width of the horizontal synchronization signal of the second video signal and outputs a control signal corresponding to the width. and a phase adjustment means that uses a control signal to adjust the time width of the horizontal synchronizing signal in the reference composite synchronizing signal at its leading edge.

According to the above configuration, the present invention separates the horizontal synchronizing signal from the second video signal read from the memory, measures the pulse width of the separated horizontal synchronizing signal, detects the difference from the normal synchronizing signal width, and detects the detected signal. The leading edge of the reference composite synchronizing signal for replacement is set so that it always matches the leading edge of the horizontal synchronizing signal of the second video signal, and is output as the third video signal. It is something.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

In the figure, horizontal synchronization signal separation circuit (H8S) 14, write clock generation circuit (W-CLK) 15° write reset pulse generation circuit (W-R8T) 16° A/D converter (A
/D)13. Memory 17. D/A converter (D/A)
20. Reference oscillator 18. Synchronous signal generation circuit 19. The switching circuits 24 perform the same functions and operations as those shown in the conventional example shown in FIG. 3, and their explanations will be omitted. In addition, the A/D converter 13. Horizontal synchronization signal separation circuit 14. Write clock generation circuit 15. The write reset pulse generation circuit 16 constitutes a write means 30, the reference oscillator 18° synchronization signal generation circuit 19 constitutes a synchronization signal generation means 32, and the synchronization signal generation means 32 and the D/A converter 20 constitute a read means. 31, horizontal synchronizing signal separation circuit 219 width detection circuit 222
Phase adjustment circuit 23. The switching circuit 24 constitutes a time axis correction means 33.

In one embodiment of the present invention, newly provided means compared to the conventional example are a horizontal synchronizing signal separation circuit 21, a width detection circuit 22, and a phase adjustment circuit 23.

The horizontal synchronization signal separation circuit 21 separates the horizontal synchronization signal that the video signal output H of the D/A converter 20 has and outputs it to the width detection circuit 2.
Enter 2. The width detection circuit 22 detects the time width of the horizontal synchronization signal I, and inputs a control signal corresponding to the width to the phase adjustment circuit 23.

In response to the control signal, the phase adjustment circuit 23 adjusts the time width of the horizontal synchronization signal in the reference composite synchronization signal G generated in advance at its leading edge, thereby adjusting the time width of the horizontal synchronization signal equal to the time width of the horizontal synchronization signal ■. A composite synchronization signal J is output.

The operation of the above configuration will be explained with reference to FIGS. 1 and 2. However, FIG. 2 shows the output waveforms of each circuit block in FIG. 1, and the same signals are given the same symbols. The principle of operation is the same as in the conventional example in that the horizontal synchronizing signal with a distorted waveform of the reproduced video signal is replaced with another horizontal synchronizing signal with a regular waveform. However, the horizontal synchronizing signal to be replaced is improved over the conventional example. This replacement operation involves manipulating the waveform of the reproduced video signal by delaying it by the width of the horizontal synchronization signal.
As the delay means, the process of A/D converting the reproduced video signal, writing it into the memory, reading the memory again, D/A converting it, and reproducing the waveform is the same as in the conventional example.

The reproduced video signal A input to the input terminal 12 is input to the A/D converter 13, where it is sequentially sampled at the timing of the write clock D and converted into digital data. By sequentially writing the digital data to the memory 17 at the timing of the reset pulse C, the data in the memory 17 becomes each sample data of the video signal waveform starting from the trailing edge of the horizontal synchronizing signal. This data is read out sequentially according to the reference clock E at the timing of the reference reset pulse F, and
When converted into an analog signal by the A converter 20, the output H
The waveform starting from the trailing edge of the horizontal synchronization signal of the reproduced video signal A is delayed in time. This time delay is caused by the above-mentioned A/D conversion, memory writing and reading, and D/D conversion.
This is the time required for A conversion. This delayed waveform is input to a replacement circuit 24, where the composite synchronization signal of waveform H is replaced by matching its trailing edge with a composite synchronization signal J generated separately. The composite synchronization signal J is configured by changing the time width of the horizontal synchronization signal in the reference composite synchronization signal G based on the reference oscillator 18 to the time width of the horizontal synchronization signal of the reproduced video signal at its leading edge by the phase adjustment circuit 23. Equally adjusted. Therefore, the output of the switching circuit 24 is such that the trailing edge of the horizontal synchronizing signal is equal to the trailing edge of the original horizontal synchronizing signal, and the leading edge thereof is also equal to the leading edge of the original horizontal synchronizing signal. Of course.

Note that this time width adjustment may include timing deviations due to other causes not mentioned above, and it is not always best to just make the time widths equal. Therefore, the function of adjusting the time width of the horizontal synchronization signal in conjunction with that of the reproduced video signal is important. Since this composite synchronization signal J has been formed in advance, its waveform is regular. Furthermore, since the waveform J is a composite synchronization signal that includes not only the horizontal synchronization signal but also the synchronization signal of the vertical blanking section, it is possible to replace the horizontal synchronization signal of the entire reproduced video signal with a regular waveform.

As described above, according to the time axis error correction device of the embodiment of the present invention, the width detection circuit and phase adjustment circuit of the horizontal synchronization signal of the reproduced video signal are provided, and the time width of the horizontal synchronization signal in the replaced composite synchronization signal is adjusted. By doing this, even though the waveform is manipulated based on the trailing edge of the horizontal sync signal of the reproduced video signal, the timing of the leading edge of the horizontal sync signal can be made the same as that of the original reproduced video signal. .

Effects of the Invention As is clear from the above embodiments, the present invention provides a time axis correction means for replacing a composite synchronizing signal of a reproduced video signal with a composite horizontal synchronizing signal separately provided with the trailing edge of the horizontal synchronizing signal as a reference. , comprising means for adjusting the time width of the horizontal synchronization signal in the composite synchronization signal to be replaced, so as to make the timing of the leading edge of the horizontal synchronization signal of the time-base corrected reproduced video signal equal to the timing of the original reproduced video signal. It is possible

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time axis error correction device according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the output waveforms of each block in FIG. 1, and FIG. 3 is a block diagram of a conventional time axis error correction device. The block diagram, FIG. 4, is a waveform diagram showing the output waveforms of each block in FIG. 3. 12...Video signal input terminal, 17...Memory,
19... Synchronization signal generation circuit, 22... Width detection circuit, 23... Phase adjustment circuit, 24... Swapping circuit, 25... Output terminal, 30... Writing means,
31... Reading means, 32... Synchronization signal generation means, 33... Time axis correction means.

Claims (1)

[Scope of Claims] Writing means for writing an input first video signal into a memory; synchronization signal generating means for generating a reference composite synchronization signal; and writing means for writing the first video signal from the memory into the reference composite synchronization signal. reading means for reading the signal at a timing of and outputting it as a second video signal; and a time axis correction means for outputting a video signal of the second video signal, the time axis correction means detecting a time width of a horizontal synchronization signal of the second video signal and outputting a control signal corresponding to the width. and phase adjustment means for adjusting the time width of the horizontal synchronization signal in the reference composite synchronization signal at its leading edge using the control signal, the time width of the horizontal synchronization signal of the third video signal being adjusted by the time width of the horizontal synchronization signal in the third video signal. A time axis error correction device characterized in that the time axis error correction device is adjusted by the time width of a horizontal synchronization signal of a video signal of No. 2.