JPS6145697A - Time base error correcting device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a read signal by calculating and predicting a current velocity error from that before several lines, modulating a write clock by the predicted value and suppressing a residual error component at the write side. CONSTITUTION:A start-stop type voltage control oscillator 21 is started from zero phase with the aid of a start signal from a timing signal generator 10 to which a reproduction video signal for accompanying the time base fluctuation is inputted. A signal for dividing the oscillation frequency of the oscillator 21 is compared with a synchronizing burst signal having the time base fluctuation from a signal generator 10 by means of a phase comparator 24. Phase fluctuation components from the comparator 24 are extracted by line, and with use of a secondary or more approximate curve a velocity error is predicted in an arithmetic circuit 30. Then a write clock from the oscillator 21 is phase-modulated by a phase modulator 50 and caused to have the velocity error component.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention provides a method for converting a video signal with time axis fluctuations, such as a video signal reproduced from a magnetic recording/reproducing device (VTR), into a video signal with time axis fluctuations. The present invention relates to a time axis error correction device for converting into a standard video signal (for example, a standard video signal in a broadcasting station).

[Conventional technology]

A time axis error correction device (Time Ba) that corrects a video signal with time axis fluctuations output from a playback device
5e Error Corrector) is especially
This is necessary for broadcasting stations to time-code various video signals.

Such a time axis error correction device, as shown in Fig. 5,
A write clock signal with time axis variation is generated by the write clock signal generator 1 according to a synchronous burst signal extracted from the input video signal Vin with time axis variation, and the input video signal Vin is converted into an A/D converter by this output. Sample at 2.

Then, the write address and the address signal output from the signal generator 3 are supplied to the memory control circuit 4 and written into the main memory 5.

On the other hand, the data written in the main memory 5 is sequentially read out according to the address of the read address signal generator 6 formed by the read clock signal generator 7 to which the standard synchronization signal is input, and 8 into an analog signal.

Then, as is well known, this converted analog signal is obtained from which time-base fluctuation components (jitter) have been removed.

In this case, as shown in FIG. 6, the synchronized burst signal SB is separated from the input video signal Vin with time axis fluctuation,
Nine burst lock generators (Burs tq (Iljyol)) are locked by this synchronized burst signal SH.
The write clock WCK is formed by the burst lock generator (BCO), and the signal output from the burst lock generator (BCO) is generated during one horizontal period (l
At the end of the line (line), the phase gradually deviates from the frequency at which it was locked, so a phase difference occurs at time T2 when it is synchronized with the next synchronized burst signal SB (such an error is called a velocity error).

Therefore, as shown in Japanese Patent Application Laid-Open No. 53-148317, the velocity error is temporarily stored in an error memory, and the read clock is phase-modulated by this velocity error signal, and the main memory 5 shown in FIG. The video signal of the corresponding line stored in is being read out. Note that the invention described in the above publication further stores the rate of change in the time axis fluctuation of the input video signal Vin, and adjusts the input video signal Vi based on the rate of change.
The readout clock signal is modulated by a velocity error signal based on the differential coefficient of the approximate tangent for each horizontal synchronization signal to the time axis fluctuation curve of n, and the advantage is that input time axis fluctuations can be reliably removed. There is.

However, since such a conventional time axis error correction device corrects the read clock using a velocity error signal, the input video data read from the main memory 5 is converted into an analog signal by /A conversion. If the output video signal is not corrected, the time axis fluctuations will not be accurately removed, so if the output video signal that has been corrected for the axis is processed by digital equipment, an A/D converter is required again. There is a problem in that it causes image deterioration.

Furthermore, as shown in Fig. 7, the video signal is separated into a luminance signal Y and a chroma signal (RY, B-Y), and the chroma signal (
If the time axis of the chroma signal (R-Y, B-Y) is compressed and recorded within one line, and then the time axis fluctuations are removed after playback, the velocity error will be caused by the chroma signal (R-Y, B-Y).
Since the first part of the chroma signals (R-Y', B-Y') is different, this is corrected by the clock on the readout side and read out as a time-extended chroma signal (R-Y', B-Y'). must be corrected with different velocity errors as shown by X and Y in the figure, making control extremely difficult.

[Problem that the invention seeks to solve]

This invention was made in view of the actual situation,
゛In the time axis error correction device, the residual error of velocity error is also suppressed by modulating the clock on the input side, and the readout side can be read out with a constant clock synchronized with the period of the standard video signal. It is intended to do so.

[Means for solving problems]

The time axis fluctuation component can be detected by a synchronized burst signal that is usually inserted every 10000 period (hereinafter referred to as 1 line), but the velocity error of that line can be detected by the video signal of the next line. is detected only after it has been played.

Therefore, in the time axis error correction device of the present invention, first, the synchronization z<
- Construct a PLL circuit that locks the start/stop oscillator using the stop signal.

Then, an arithmetic circuit is provided that calculates the velocity error for each line obtained from the phase detector of this PLL circuit by referring to the velocity error several lines earlier.

Furthermore, the current velocity error is predicted from the output of this arithmetic circuit, and the phase of the output frequency of the start/stop oscillator is modulated based on this predicted value to form a write clock.

An embodiment of the present invention will be described below with reference to the block diagram of FIG.

In this figure, 10 is a timing signal generator to which a video signal (playback video signal) with time axis variation is input, and 20 is a start-stop EE control oscillator (SS-VCO). 21, first and second frequency dividers 22, 23 . A PLL circuit consisting of a phase comparator 24° loop filter 25, 30 is an IH delay circuit 31
．． X(-1) coefficient circuit 32. X2 coefficient circuit 33. A velocity error calculation circuit consisting of an adder circuit 34; 40 an integrator circuit 41. An integrator 50 composed of the reset switch circuit 42 receives the divided output of the start-stop type voltage controlled oscillator 21.

A phase modulator for phase modulation, 60, 70.

80 is a PLL circuit that is locked to the output signal of the phase modulator 50 and generates different frequencies; 60 is a phase comparator; 70 is a voltage controlled oscillator; 80 is a frequency divider (1/N
3) is shown.

[Effect]

In this circuit, a timing signal generator 10 extracts a synchronous burst signal and a start signal having time variations, and a start-stop type voltage controlled oscillator (SS-VCO) 21 starts from phase 0 by the start signal.

If this oscillation frequency and number are fs, then 1. Since the signal converted to (1/Nl The signal is supplied to a start-stop type voltage controlled oscillator 21 via a loop filter 25.

Therefore, this voltage-controlled oscillator 21 generates a clock signal that changes in accordance with the time axis fluctuation for each line of the video signal, and this clock signal is used to input the clock signal as shown in the conventional example in FIG. When the video signal Vin is sampled and written into the main memory 5, it is recorded in the main memory 5 with time axis fluctuation components removed line by line.

However, as described above, the frequency output from the start-stop type voltage controlled oscillator 21 includes a velocity error. This velocity error causes a residual time axis error.

Therefore, in the present invention, a phase variation component is extracted from the phase comparator 24 for each line to detect velocity errors.

This velocity error, that is, the phase fluctuation, becomes a continuously changing curve as shown in FIG. 2, for each life n-2, n-1, n, n+1, .・・・・・・A every time
It is thought that it changes as l + at + al r &6.

Here, the phase variation in n lines is al, n-1
The phase fluctuation of the line is az, and the phase fluctuation of the n-2 line is a
l, then this range is expressed by the general formula of the quadratic curve y=Ax2+
The phase fluctuation of the n+1 line can be predicted by approximation from Bx+C.

In other words, the curve showing the change in velocity fist error is n
Up to the line (T, al +b), (2T.

az +a3 +b), (3T, al +a2 +&
Since the curve originates from the point 30b), the quadratic equation representing this change is an answer that satisfies (1).

Therefore, by solving the simultaneous equations (1),
This curve is the next point (4T, a□ +a1+a2 +a3
+b), ao+at +a2. +&3 +b = 16AT2+4BT+C =8 (a, -&2)+2 (-3a, +5a2)
+al-2a2'+a3+b =3a++a3+b Therefore, ao=2a1-a2.

In other words, the sum of twice the velocity error a1 of the previous line and (-1) times the velocity error of the line before the previous line can be seen as the value of the next velocity error approximated by a quadratic curve. .

Therefore, in the time axis error correction device of the present invention, the velocity Φ error a1 of N lines is calculated by ×2 in the arithmetic circuit 3o.
It is doubled by the coefficient circuit 33, and the velocity error a1 of the N-1 line is extracted from the IH delay circuit 31 and
-t) Inverted by the coefficient circuit 32 and added to the addition circuit 3
4 and calculates the velocity error aO that is predicted to occur on the N+1 line.

The current velocity error a calculated in this way
0 is integrated in the integrator 40 for each IH period, and this integrated value is used as the write clock (
WCK) is phase modulated by a phase modulator 50 to include a velocity error component. In this case, the first frequency divider 22 divides the frequency fs of the voltage controlled oscillator 21 (
1/Nl), phase modulation becomes easy.

Then, this phase-modulated write clock is input to the phase comparator 6o, and the voltage controlled oscillator 70 is controlled to be locked and a predetermined write clock (14, 3181
8MH2).

Therefore, if a video signal with time axis fluctuations is sampled by the output of the voltage controlled oscillator 70, converted into a digital value, written to the main memory 5, and read out using a standard read clock (RCK), the time axis fluctuations can be detected. The data of the video signal from which the components and velocity errors have been removed is output from the main memory 5.

In this case, the data read from the main memory 5 is
Since the signal can be directly inputted from the terminal to another digital video signal processing circuit without performing D/A conversion, the signal can be processed by the digital circuit without deteriorating the video signal.

Also, when removing time axis fluctuations of a chroma signal that has been time axis compressed as described above, R-Y is used.

Since the B-Y signal can be read out using a read clock with the same period and the time axis can be expanded at this time, the TB
This has the advantage that the configuration of C is simplified.

〔Example〕

Although the embodiment in which the velocity error during writing is predicted by approximating a quadratic curve has been described above, the current velocity error may also be predicted by approximating a cubic curve.

The prediction in this case is the general formula y=Ax3+BX2+Cx+
For D (0+ b) + (T + a3 + b)
.

(2T, a2 +a3 +b), (3T, al +
a2 + a3 + b) If it passes through the point, then the following holds true. Therefore, when the above simultaneous equations are solved, this curve further becomes the point (4T, ao + a I+
a2+a3+b), then aQ +a1+a2 +a3 +b =64AT3+16BT2+4CT+D=64/6 (
at -2a2 +ri3 )+a (a+ +3a2-
2a3) +4. /E3 (2a1-7a2+11a3)+b=4
a, -2a2 +2a3 +b Therefore, ao =3a1-3a2 +a3.

Figure 3 shows the arithmetic circuit 3o that calculates the third-order velocity error, and 31.35 is an IH delay circuit;
6 is Xi coefficient circuit-137 is ×(-3) coefficient circuit, 39
is an adder circuit.

The output of the adder circuit 39 outputs ao=3a1-3a2+a3 indicating the current velocity error.

Figure 4 shows the residual time axis error when the velocity error is predicted by such an approximation and the writing side clock is phase modulated based on this prediction (a sine wave with an amplitude of 100 is given as the velocity conflict error). The data is shown in which the vertical axis is the frequency component of one time axis fluctuation and the horizontal axis is the frequency component.

Curve v whose predicted value is the velocity error before l line
1, a curve V 2 whose predicted value is the velocity error predicted by the quadratic or cubic equation described above.
It can be seen that the effect of suppressing the residual time axis error is greater in the case of +”3.

Note that the part where the frequency component of time axis fluctuation is high (f c'=
2.7 KHz or higher), there is no suppression effect, but such time axis fluctuations in high frequency components do not occur due to mechanical causes in the video signal playback device, and are usually mostly below IKHz, so they are hardly a problem. It will never be.

〔Effect of the invention〕

As explained above, the time axis variation error correction device of the present invention corrects the velocity error occurring in a PLL circuit that generates a write clock signal having a time axis variation of 1 by 2.
The prediction is made using an approximation curve greater than or equal to the following, and the write clock is modulated with this predicted value to write the reproduced video signal to the main memory, so residual error components due to velocity errors are suppressed on the writing side. The advantage is that it can be done.

Therefore, the signal read from the main memory can be input to the signal processing circuit in the form of digital data, and signal deterioration can be reduced.

Further, in the case where a video signal is separated into a luminance signal and a chrominance signal, and the chrominance signal is band-compressed, jitter removal is particularly advantageous in that the circuit is simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram for forming a write clock showing an embodiment of the present invention, FIG. 2 is a diagram showing phase fluctuation, and FIG. 3 is a block diagram showing a calculation circuit for a third-order velocity conflict error. Fig. 4 is a frequency characteristic diagram showing the residual time axis error, Fig. 5 is a block diagram of the time axis error correction device, Fig. 6 is a diagram of the relationship between the phase of the reproduced video signal and the write clock,
FIG. 7 is a diagram showing the relationship between a video signal separated into a luminance signal and a chroma signal and the amount of phase variation. In the figure, 1 is a write clock signal generator, 2 is an A/D converter, 3 is a write address signal generator, 4 is a memory control circuit, 5 is a main memory, 6 is a read address signal generator, and 7 is a read clock A signal generator, 8 a D/A converter, 10 a timing signal generator, 2o a PLL circuit,
21 is a voltage controlled oscillator, 22 is a first frequency divider, 23 is a second frequency divider, 24 is a phase comparator, 25 is a loop filter, 30 is a velocity error calculation circuit, 31.35 is an IH delay circuit, 32 is x(-i) coefficient circuit, 33 is x2
Coefficient circuit, 34.39 is an addition circuit, 36 is a ×1 coefficient circuit, 37 is an X(-3) coefficient circuit, 4o is an integrator, 41 is an integration circuit, 42 is a reset switch circuit, 50 is a phase modulator, 60 is a phase comparator, 70 is a voltage controlled oscillator, and 8o is a frequency divider. Figure 2 Figure 3

Claims (1)

[Claims] A PLL circuit that controls the oscillation frequency of the start/stop voltage controlled oscillator using a synchronized burst signal of a video signal and an error output of a phase comparator to which the divided output of the start/stop voltage controlled oscillator is input, and the phase comparison circuit. an arithmetic circuit that calculates the error signal output from the device at a predetermined ratio over at least two lines of the video signal; and an integrator circuit that integrates the output of the arithmetic circuit for each line of the video signal; A time-base error correction device characterized in that the output frequency of the PLL circuit is phase-modulated to produce a write clock signal.