JPH01293787A - Delay error correcting device - Google Patents

Abstract

PURPOSE:To automatically correct a delay error with high accuracy by converting plural signals to digital signals with a sampling clock, whose phase is synchronized to a self-synchronizing signal, and executing the detection and correction of the delay error between the signals. CONSTITUTION:A ternary signal is added to input signals R, G and B. The R signal is converted to the digital signals by the sampling clock, which is synchronized to the self-synchronizing signal, in a synchronous separating circuit 4a, a PLL circuit 5a and an A/D converter 3a. Now, when the G signal is operated with defining the R signal as reference, the phase of the sampling point of the G signal is synchronized to the phase of the sampling point of the R signal by a timing circuit 6b and the delay error between the R signal and G signal for the unit of a clock period is detected by an error detecting circuit 8b. Then, since the R signal and G signal are passed through shift registers 7 and 9b, whose delay quantity is fixed and variable, the error is caused to be '0'. Thus, the delay error is automatically corrected with the high accuracy.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a device for processing a plurality of input signals, in which delay errors between input signals and delay errors between each signal occurring within the processing device are The present invention relates to a delay error correction device that eliminates.

[Conventional technique #i] Hereinafter, television signal (hereinafter referred to as rTVTV signal)
This will be explained using a processing device as an example.

A TV @ that can provide a TV screen with higher definition and a sense of realism in place of conventional TV signals such as NTSC and PAL.
The practical application of the number is being considered.

One of them, the high-definition signal, has 11 scanning lines.
The aspect ratio of one 25-inch screen is 9:16, the bandwidth of the luminance signal is 20 MHz, and it is possible to transmit five times the amount of information as the NTSC signal.

For transmission of high-definition signals, one-channel transmission is possible, and a time division multiplex signal (hereinafter referred to as rTCI signal) that does not cause crosstalk between luminance signals and color difference signals.
) is used.

FIG. 4 is a block circuit diagram showing the configuration of a conventional TCI encoder for TV signals, and FIG. 5 is a signal waveform diagram of each part for explaining its operation.

In FIG. 4, (la), (Ib), and (lc) are low-pass filters (hereinafter referred to as "rLPF") that limit the bandwidths of input R, G, and B signals, respectively, (2a),
(2b).

(2c) is a clamp circuit that reproduces the DC component of each signal, (
3a), (3b), and (3c) are A/D converters that convert analog R, G, and B signals into digital R, G, and B signals, and (10) is an input R, G, and B signal. , a luminance signal (hereinafter referred to as "Y signal") and two color difference signals (hereinafter referred to as "Y signal")
The matrix circuit (11) separates and outputs the rPB and PR signals.

FB, a time division multiplex circuit that converts PR into a TCI signal;
(54) is a synchronization separation circuit that separates and outputs a horizontal synchronization signal H3 and a vertical synchronization signal S from a synchronization signal (hereinafter referred to as "rSYNC signal"), and also outputs a clamp pulse Pc; (55) is a horizontal synchronization This is a PLL circuit that generates a clock signal synchronized with the signal H5, and the matrix circuit (10) includes a digital LPF that limits the bandwidth of the P[1,PR signal to the Y signal station.

Next, the operation will be explained. Input analog R, G
, the form of the B signal is shown in Fig. 5 (a), (b), (
C), where IH represents one horizontal scanning period. The IH period of each signal consists of a video signal period and a horizontal blanking period.

As shown in FIG. 5(d), the 5YNC signal has a negative polarity pulse during the horizontal blanking period and the vertical blanking period (not shown). PLL circuit (
55) receives the horizontal synchronization signal H5 separated by the synchronization separation circuit (54) and generates a clock signal synchronized therewith. On the other hand, L P F (la), (lb), (l
The R, G, and B signals band-limited by c) are clamped by clamp circuits (2a), (2b), and (2c), respectively, and the DC components are regenerated. The clamp pulse Pc used at this time is output from the synchronous separation circuit (54). A/D converter (3a), (3b), (3c)
Here, the R, G, and B signals are sampled by the clock signal output from the PLL circuit (55) and converted into digital R, G, and B signals. Matrix circuit (10
) converts digital R, G, B signals to digital Y, FB
, a PR signal, and then restricts and outputs the bandwidth of this FB and PR signal to the station using a built-in digital LPF. The time division multiplexing circuit (55) operates in units of IH. , digital Y, Pa, and PR signals are subjected to IH small unit time axis compression, time division multiplexed, and a synchronization signal is added to create the TCI signal shown in FIG. 5(e). Here, the time axis compression ratio of the FB and PR signals is three times that of the Y signal. The TCI signal is then transferred to a D/A (not shown).
The signal is D/A converted by a converter and transmitted in the form of an analog signal.

When the TCI encoder configured as described above is applied to high-definition signals, the following problems occur. In other words, Television Society Technical Report Vol. 1.11,
No. 9, pp. 13-18, +987, As stated in "About high-definition synchronization signal standards", in high-definition signals, the detection limit for delay errors between each channel (for example, R, G, B signals) is 3.5n
It is s.

On the other hand, when R, G, and B signals are transmitted over 100 m using a coaxial cable, a delay time deviation of approximately ±15 ns may occur. The TCI encoder shown in Fig. 4 uses coaxial cables that transmit R, G, and B signals and L P F (la), (
Since processing is performed regardless of the error in delay time caused by lb) and (lc), the time axis of each signal remains shifted from Y,
It may happen that it is converted into PR, PR signal, or even TCI signal. And - ICT with the variable time axis shifted
Once converted to a signal, it is impossible to restore the original signal.

In the above literature, in order to detect the delay time difference of each signal,
It is proposed to add a ternary opening signal to each signal.

FIG. 6 is a block circuit diagram of the synchronous separation circuit shown in the document, and FIG. 7 is a signal waveform diagram of each part for explaining its operation. In Figure 6, (61)
is LPF, (62) is peak clamp circuit, (Ei3)
, (6G) is a comparator circuit, (64) is a monomulti circuit, (85) is a pedestal clamp circuit, and (67) is an AND circuit.

Next, the operation will be explained. The input signal is a video signal to which a ternary opening signal as shown in FIG. 7(a) is added. Here, the three-value opening signal is a signal that changes in both positive and negative directions around the vedestal level LP. When the comparator circuit (83) in FIG. 6 detects that the input signal has become equal to or less than the negative threshold Ln shown in FIG. 7(a),
The next-stage monomulti circuit (64) generates a high-level pulse for a predetermined period of time from that point on, as shown in FIG. 7(b). On the other hand, the pedestal clamped input signal is compared with the pedestal level Lp by the comparator (68), and the output of the comparator (6B) has an output waveform as shown in FIG. 7(c), and the AND circuit (67) At , the output of the monomulti (64) and the logical AND operation are performed, and the result shown in Fig. 7 (
The output shown in d) is obtained. The rise of this output becomes the phase reference of the video signal. That is, by adding a ternary opening signal to each input signal, the phase reference of each input signal can be detected.

Note that the synchronization signal added to the input signal is not limited to a ternary waveform, but the above document shows that it is superior in terms of phase reference detection accuracy when compared to a binary waveform or a black burst. It has been reported.

In addition to the above-mentioned literature, there has also been a proposal to add a synchronization signal to each of multiple input signals to obtain a phase reference for each signal. It has not been disclosed whether any amendments will be made.

[Problems to be Solved by the Invention] In conventional processing devices that receive a plurality of input signals, the delay error between each input signal is not corrected.1 For example, when processing a high-definition signal, the delay error between each signal is There is a problem in that there is a high possibility that the detection limit will be exceeded and the image quality will deteriorate.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a delay error correction device that can automatically and accurately correct delay errors between a plurality of input signals.

[Means for Solving the Problems] A delay error correction device according to the present invention converts a plurality of input signals having the same type of synchronization signal into digital signals using sampling clocks whose phases are synchronized with each own synchronization signal. means for converting these digital signals into signals whose phases are synchronized with any one of the sampling clocks; and a means for converting these digital signals into signals whose phases are synchronized with one of the clocks among the sampling clocks, and a position in clock period units between the synchronization signals of each of the digital signals whose phases are synchronized. The apparatus includes means for detecting a phase difference, and means for correcting a phase difference between each digital signal in units of clock cycles so that each of these detected phase differences becomes 0.

[Operation] The means for converting an input signal into a digital signal converts the input signal into a digital signal using a sampling clock whose phase is synchronized with its own synchronization signal.

The means for converting into a digital signal whose phase is synchronized with the reference clock corrects the phase difference between each sampling point of each digital signal. The phase difference detection means between the synchronization signals of each digital signal detects the phase difference in clock cycle units between the synchronization signal of the reference digital signal and the synchronization signal of another digital signal. The phase difference correcting means corrects the phase of each digital signal so that each detected phase difference becomes O.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings. FIG. 1 is a block circuit diagram showing the configuration of a TCI encoder, and the portion surrounded by a dashed line is the delay error correction device of this embodiment. In the same figure, (la) to (3c)
, (10) and (11) are the same as those in FIG. 4, so their explanation will be omitted. (4a), (4b), and (4c) are synchronous separation circuits, and (5a), (5b), and (5c) are PLL circuits that output clocks synchronized with each video signal (R, G, and B signals). . (8b) and (8c) are timing circuits that can perform writing and reading asynchronously.
It consists of an IFO circuit. (7) is a shift register that delays input data in units of a predetermined clock cycle.

(8b) and (8c) are error detection circuits, and R
The delay error (phase difference) of the G signal and the B signal in units of clock cycles is detected when the signal is used as a reference. (!3b
) and (9c) are shift registers whose delay amounts change according to the outputs of the delay error detection circuits (8b) and (8c), respectively.

Figure 2 is a block circuit diagram showing an example of the configuration of the error detection circuit (8b). In Figure 0, the error detection circuit (8c) is similarly configured. A comparator circuit that determines the magnitude of a signal, (32) is a comparator circuit (31a), (31b)
), the counter control circuit (34) receives the output of the counter (33) and generates a control signal for the next stage counter (33).
) The latch circuit t' (35) is a ROM circuit that uses the output of the latch circuit (34) as an address signal.

In this embodiment, a synchronous separation circuit (4a).

The PLL circuit (5a) and the A/D converter (3a) constitute means for converting the R signal into a digital signal using a sampling clock synchronized with its own synchronization signal, and the G signal system and B signal system are also converted into digital signals. The same is true.

Further, the timing circuits (6b) and (6c) constitute means for synchronizing the phase of each sampling point of the digital G signal and the digital B signal with the phase of the sampling point of the digital R signal, respectively.

Further, the error detection means (8b) and (8C) are means for detecting a phase difference (delay error) in clock cycle units between the synchronization signal of the digital R signal and each synchronization signal of the digital G and B signals. It consists of

Further, the shift registers (8b) and (8C) constitute means for correcting the phase difference between the digital R signal and the digital signal and the B signal in units of clock cycles so that the phase difference becomes O.

Next, the operation of this embodiment will be explained.

The input signals R, G, and B signals are shown in Fig. 7 (a).
) is added to the three-value opening signal.

It is also assumed that the synchronization separation circuits (4a), (4b), and (4c) have the configuration shown in FIG. Therefore, each A/D converter (3a), (3b), (3c
), the phases of the R, G, and B signals and the sampling clocks are synchronized with each other. In this embodiment, the R signal is used as a reference, and the G signal and B signal are manipulated to make the delay error between the three signals zero.

Note that since the same signal processing is performed on the G signal system and the B signal system, the G signal system will be explained below.

The timing circuit (6b) is configured as described above (FIFO circuit), writing control is performed using the output clock of the PLL circuit (5b), and reading is performed using the PLL circuit (5a).
) using the output clock. PLL circuit (5a
) and (5b) have the same frequency but generally different phases. The delay time Td between input and output signals of the timing circuit (6b) is expressed as Td = (M±α)T.

Note that if the value of 1M is set large, the delay error that can be corrected increases in this example, but here, the output of the timing circuit (6b) is always higher than the output of the A/D converter (3a). It is assumed that the value of M is set so that there is a delay.

Now, the output of the timing circuit (6b) and the A/D converter (
Comparing the outputs of 3a), the delay time difference is an integral multiple of the clock period T. Namely.

The correction for the clock cycle T or less is completed, and what remains is the correction for each clock cycle T unit. This T unit correction is performed as follows.

The R signal passes through a shift register (7) with a fixed delay amount, while the G signal passes through a shift register (8) with a variable delay amount.
via b). Therefore, the delay amount of the shift register (9b) is adjusted between the A/D converter (3a) and the timing circuit (6b).
), the delay error between the R and G signals can be eliminated by making a decision in the error detection circuit (8b) based on the relationship between the outputs of the R and G signals. Here, as a matter of course, the amount of delay of the shift register (9b) is smaller than the amount of delay of the shift register (7).

Next, the operation of the error detection circuit (8b) shown in FIG.
This will be explained using signal waveform diagrams of each part shown in the figure.

Although this circuit is not shown in the figure, the synchronous separation circuit (4
a) It is configured to be in an operating state when at least one of the three-value opening signals of the R signal and the G signal is input in response to the horizontal synchronizing signal H3 which is the output of the ing. The output of the A/D converter (3a) (shown in FIG. 3(a)) and the output of the timing circuit (8b)
The comparators (31a
) and (31b) and are compared with a common threshold Lg. Figures 3(a) and 3(b) show the ternary opening signal part of the input waveform of the comparators (31a) and (31b) in the form of an analog signal, and the 0 mark in the figure is the sample point. It represents. In addition, the waveform of the three-value opening signal is
The rise time from the pedestal level Lp to the level Lt on the upper side of the positive polarity synchronous part and the fall time from Lp to the level Lb on the lower side of the negative polarity synchronous part are both one clock period T, and the threshold value Lg is It is assumed that the level Lp is set to an intermediate value between the level Lp and the level Lt of the upper side of the positive pulse. The output of the comparator (31a) and (
The crabs in 31b) are shown in Figures 3(C) and (d)', respectively.
become that way. The counter control circuit (32) has two outputs from the comparators (31a) and (31b).

The output clock of the PLL circuit (5a) and the output clock of the PLL circuit (5a) are input, and the signals shown in FIGS. 3(e), (f), and (g) are
Output key. Here, the signal O is a signal that specifies the counting operation period of the counter (33), the signal power is a signal that gives the timing to preset the count value of the counter (33) to a predetermined value, and the signal K is a signal that specifies the counting operation period of the counter (33). (3
This is the signal used as the latch clock in step 4). That is, the counter (33) is preset to a predetermined value in synchronization with the rising edge of the output signal of the comparator (31a), and a counting operation is started. Then, the counting operation is stopped in synchronization with the rise of the output signal of the comparator (31b), and the count value at that point is held in the latch circuit (34). The ROM circuit (35) uses the output of the latch circuit (34) as an address input, and outputs data written in advance at each address. This data determines the amount of delay of the shift register (8b) shown in Figure 1, and is set so that the delay error between the output of the shift register (7) and the output of the shift register (8b) is O. The shift register (9C) outputs a digital G signal whose delay error with respect to the digital R signal has been corrected.

Similarly, the shift register (8C) also outputs a digital B signal with the delay error corrected, so as a result,
Digital R,G without delay error.

The B signal will be input to the matrix circuit (10).

In addition, in the above embodiment, the case where each signal has a three-value open signal is explained, but the synchronization signal is not limited to a three-value open signal, and may be a negative polarity synchronization signal or a negative polarity synchronization signal. Other synchronization signals may be used, such as a combination of a synchronization signal and a sinusoidal burst signal.

In addition, although the above embodiment shows the case where R, G, and B video signals are input, the input signal is not limited to this, and the same effect can be obtained as long as the signal has the same type of synchronization signal added. play.

Furthermore, the phase detection circuit shown in FIG. 2 and the synchronization separation circuit shown in FIG. 6 may have any configuration as long as they have the same function.

[Effects of the Invention] As described above, according to the present invention, after converting a plurality of signals into digital signals using a sampling clock whose phase is synchronized with its own synchronization signal, each digital signal is converted into a digital signal whose phase is synchronized with a reference clock. The system is configured to convert these digital signals into digital signals, detect delay errors between these digital signals, and correct the delay errors using a variable shift register.
This has the effect of providing a delay error correction device that can automatically and highly accurately correct delay errors between a plurality of signals.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of a delay error correction device and a TCI encoder using the device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of an error detection circuit of this embodiment. , Fig. 3 is a signal waveform diagram of each part to explain its operation, Fig. 4 is a block circuit diagram showing the configuration of a conventional TCI encoder, and Fig. 5 is a signal waveform diagram of each part to explain its operation. , FIG. 6 is a block circuit diagram showing the configuration of a synchronous separation circuit described in a known document, and FIG. 7 is a signal waveform diagram for explaining its operation. (3a), (3b), (3c)... A/D converter, (
4a), (4b), (4c) --- Synchronization separation circuit, (
5a), (5b), (5c)...PLL circuit, (
Elb), (8c), , timing circuit, (7)
, (!3b), (9c)...shift register circuit, (8b), (8c)...error detection circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) means for converting a plurality of input signals having the same type of synchronization signal into digital signals using sampling clocks whose phases are synchronized with their own synchronization signal; and means for converting these digital signals into digital signals using one of the sampling clocks mentioned above. means for converting the signals into signals whose phases are synchronized with the clocks of the digital signals; means for detecting the phase difference in clock period units between the synchronization signals of the respective phase-synchronized digital signals; A delay error correction device comprising means for correcting a phase difference between each digital signal in clock cycle units so that the phase difference becomes zero.