JP3063480B2 - Digital color signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for handling video signals, such as a video tape recorder (hereinafter referred to as VTR) or a television, and mainly to a digital color signal processing method for transmitting a color difference signal by time division multiplexing. It is.

[0002]

2. Description of the Related Art In recent years, VTRs that achieve high image quality by applying digital signal processing technology to video signals have been announced one after another.

[0003] Most of them have improved noise elimination effect by performing inter-line processing or inter-field processing, and some have improved basic performance by digitizing all recording and reproduction processing.

Although the above-mentioned processes cannot be realized without advance in the semiconductor process, it goes without saying that efficient use of memory is indispensable for executing a compact LSI design. No.

Since the color signal has a narrower band than the luminance signal, it is possible to perform processing with a reduced sampling frequency.

Therefore, as long as the sampling theorem is satisfied, it is possible to perform the thinning process by a fraction, and the memory usage can be reduced in proportion to the thinning rate. If the sampling points are not thinned out, the sampling points in the vertical direction are shifted, so that the vertical calculation process represented by the comb filter cannot be performed correctly.

This will be described with reference to a simple timing chart shown in FIG. FIG. 4A shows a sampling clock, and FIG. 4B shows a signal sampled by the aforementioned clock.

FIG. 4D shows a case where the signal shown in FIG. 4C obtained by dividing the sampling clock of FIG. 4A by half is at "H" level. The data sequence in which the data of b) is selected is shown.

[0009] A data string is shown next after the data of the (n + 1) th line is continuously thinned out after the nth line.

[0010] In order to simplify the explanation, the data symbols between the lines are the same. As described above, when data of 9 lines / line is thinned out based on a signal obtained by dividing the sampling clock by ２, the continuity of the data is maintained in one dimension, so that the calculation in the horizontal direction is performed. Can be run without problems.

However, when viewed two-dimensionally,
Original (data on line n, data on line n + 1)
Should be (D0, D0), (D2, D2),..., But the data phase is shifted by one clock (D0
0, D8), (D0, D1),..., And the calculation in the vertical direction cannot be performed as it is.

Therefore, when two-dimensionally processing the thinned data by such a method, it is necessary to align the timing of starting the writing of the memory at the head of the video signal.

In order to solve this problem, conventionally, the operation of resetting the timing of thinning out the video signal with the horizontal synchronization signal as a trigger at the beginning and performing the operation of aligning the sampling points in the vertical direction has been performed.

However, if such processing is adopted, the number of sampling data in one line may be different, and it is necessary to control the address of the memory according to the excess or deficiency from the number of reference data.

One means for solving the above-mentioned problems by digitizing and processing the color signal of the VTR is disclosed in, for example, Japanese Patent Publication No. 4-38195 entitled "Video signal digital processing method".

Hereinafter, a conventional video signal digital processing method will be briefly described. This conventional example provides a method of performing signal processing with substantially the same circuit by utilizing the similarity of both the NTSC and PAL systems that are the current television broadcasting systems.

That is, the subcarrier frequencies of the color signals of the NTSC system and the PAL system are both converted to a common frequency, and the signal processing is performed by thinning out the data by one third.

As a result, for example, the memory capacity of the comb filter is reduced to one third, and the increase in the number of circuits required for the thinning process can be sufficiently compensated.

The condition for thinning out to one-third is that the sampling frequency is N times the horizontal synchronization signal frequency (N is an integer), and the integer N is divided by 4 to obtain N = 4K + M
(K is an integer, M is any number of 0, 1, 2, 3), and the integer N is divided by 3 to obtain N = 3L + Q (L is an integer, and Q is any of 0, ± 1) , P = M
This is to select N such that the integer P + Q becomes an even number.

By selecting such a frequency,
Even if the sampling point in the vertical direction shifts because N is not a multiple of 3 and is thinned to one third, it becomes data of one clock, and since it has a phase, it can be configured as a comb filter. And

[0021]

However, in the above conventional configuration, since the sampling frequency is limited, for example, the most frequently used 4 bits in the NTSC system are used.
There is a problem that the clock frequency of fsc (fsc is the color subcarrier frequency) cannot be used, and the baseband signal (two color difference signals) cannot be handled. I was

The present invention solves the above-mentioned conventional problems. A frequently used sampling frequency can be selected, and color signal processing can be performed in the form of a color difference signal. It is an object of the present invention to provide a digital color signal processing method in which vertical processing of a comb filter or the like can be performed without requiring address control of a memory even if the occurrence of a color error occurs, and the memory capacity of the memory can be further reduced.

[0023]

In order to achieve this object, a digital chrominance signal processing method according to the present invention uses a clock frequency for sampling two color difference signals which is n times the horizontal synchronization signal frequency (n is a positive integer). And n / m = k +
The polarity of the first frequency- divided signal obtained by dividing the clock frequency by an integer value m that satisfies the relationship of 0.5 (m is a positive integer and a multiple of 2 and k is a positive integer) is expressed by 2 of the integer value n. Double value before
Using a flag signal switching the inversion / non-inversion of the serial clock frequency at a second frequency divided signal obtained by frequency-dividing said clock division
An object of the present invention is to provide a method of thinning out the two color difference signals sampled by the wave number to form a time-division multiplexed data string .

[0024]

According to the present invention, two color difference signals sampled at n times the horizontal synchronizing signal frequency by the method described above are converted into n color difference signals.
Time division multiplexing is performed by thinning out the first frequency-divided signal divided by an integer value m satisfying the relationship of /m=k+0.5.

At this time, since n / m does not become an integer value, if it is simply thinned out, the sampling point in the vertical direction shifts. Therefore, the first divided signal for each line is divided by the second divided signal divided by the integer value 2n. Invert the polarity of the cycle signal.

As a result, the timing of the thinning process changes, and even if a fraction of 0.5 occurs, transmission in a signal form in which the sampling points in the vertical direction match can be realized. Do not need.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital color signal processing method according to the present invention will be described below with reference to the drawings.

When the color signals are digitized and processed,
In particular, the NTSC system employs a sampling frequency of 4fsc (fsc is the color subcarrier frequency: 14.3 MHz).

This is a frequency suitable for performing so-called Y / C separation for separating a color signal and a luminance signal at the time of recording processing by digital processing. It is common to use frequencies.

Therefore, the sampling frequency n is set to 4fsc =
910fH (fH is the horizontal synchronization signal frequency), and n /
4 is selected as an integer value m that satisfies m = k + 0.5.

In this setting, when data is thinned out, the timing usually becomes as shown in FIG.

FIG. 1A shows a sampling clock of 4 fsc, and FIGS. 1B and 1C show two color difference signals sampled by the aforementioned clock.

FIG. 1E shows a data sequence obtained by selecting the data shown in FIGS. 1B and 1C when the signal shown in FIG. 1D is at the "H" level, and performing time-division multiplexing. Is represented.

That is, this corresponds to (R0, B0), (R
2, B2),..., (R908, B908) is a time-division multiplexed data sequence of 455 color difference signals thinned out to one half.

FIG. 1 (g) shows the waveform when the signal shown in FIG. 1 (f) obtained by dividing the sampling clock of FIG. 1 (a) by 1/4 is at "H" level. (E) represents a data string which is selected and time-division multiplexed.

That is, this corresponds to (R0, B0), (R
4, B4), ..., (R904, B904), R90
This is a time-division multiplexed data sequence of 227 + 0.5 color difference signals thinned out to one fourth by a combination of eight.

Next, in the processing of the (n + 1) -th line following the processing of the n-th line in (b) to (g) of FIG. 1, if the signal of (f) in FIG. B908,
It becomes a time-division multiplexed data sequence of 227 + 0.5 color difference signals thinned out to one fourth by the combination of (R2, B2),..., (R906, B906).

In order to simplify the description, the data symbols (R0, B0, etc.) between the lines are the same.

As described above, when data of 910 / line is thinned out based on a signal obtained by dividing the sampling clock by ４, the continuity of data is maintained in one dimension, so that the horizontal direction is maintained. Can be executed without any problem.

However, when viewed two-dimensionally,
Original (data on line n, data on line n + 1)
Where (R0, B0), (R4, B4), ... should be (R0, B908), (B0, R2),
, The calculation in the vertical direction cannot be performed as it is.

Even if the data is shifted by one, (R
(0, R2), (B0, B2),..., Which is an operation with data separated by two sampling points, which also poses a problem in terms of accuracy.

That is, the same problem as that shown in FIG. 4 occurs. FIG. 2 is a timing chart for explaining the operation of the digital color signal processing method of the present invention which has solved the above-mentioned problems.

FIGS. 2A, 2B and 2C are the same as FIGS. 1A, 1E and 1F.

In the method shown in FIG. 1, the polarity is inverted at the beginning of each line in order to continue thinning out 910 data by a signal obtained by dividing the data by ９, and the data is not aligned in the vertical direction.

Accordingly, the polarity of the 1/4 frequency-divided signal shown in FIG. 2C is inverted with the 1/820 frequency-divided signal inverted for each line shown in FIG. 2D. If
Data is aligned at the beginning of each line.

For example, if the polarity is inverted when the polarity of (d) in FIG. 2 is "H" level, the leading data of the data on the n-th line and the (n + 1) -th line are both (R0, B0).

Further, if this method is applied to the data sequence shown in FIG. 4, the data frequency becomes 2 at the boundary where the polarity of the divided signal is inverted.
As for the problem of doubling, the multiplexing continuity deteriorates due to time division multiplexing, but the data frequency is constant and no problem occurs.

FIG. 3 shows a color signal processing apparatus realized by using the digital color signal processing method of the present invention, in which the sampling clock is 4 fsc and the thinning-out processing is 1/4.

The low-frequency conversion color signal applied to the input terminal 1a is demodulated into two color difference signals by the demodulation circuit 101 based on the carrier signal applied to the input terminal 1c.

The demodulated two chrominance signals are band-limited by low-pass filters 102 and 103, and then decimated by a decimating circuit 104 to 1/4 for multiplexing.

The multiplexed two color difference signals are processed by the comb filter 105 and the reproduction processing circuit 106 for controlling the phase and amplitude directions, and are interpolated by the interpolation circuit 107 to four times the frequency.

Then, the low-pass filters 108 and 109
After being band-limited, the signal is modulated by the modulation circuit 110 to obtain a reproduced color signal at the output terminal 1d.

Here, the thinning circuit 104 and the interpolation circuit 107 are controlled by a flag signal generated by a flag signal generating circuit 111.

In the flag signal generating circuit 111, the input terminal 1
The horizontal synchronizing signal given to b is frequency-divided to generate a signal corresponding to (d) in FIG. 2, and inversion / non-inversion of the signal obtained by dividing the sampling clock by 切 り 換 え according to the polarity is switched. , As a flag signal.

Since the thinning circuit 104 thins out the data shown in FIG. 2 based on this signal, the number of memory stages of the next stage comb filter 105 is 455 for one line.

That is, 227 for one color difference signal
Since a + 0.5-stage memory is required, multiplexing two signals results in an integer of 455 stages, eliminating the need for address control and the like.

In the interpolation circuit 107, a flag signal is required to increase the frequency four times and output the signal in two parts. This signal takes into account the processing delay of the comb filter 105 and the reproduction processing circuit 106. It has become something.

[0058]

As described above, according to the present invention, the clock frequency for sampling two color difference signals is set to n times (n is an integer) the frequency of the horizontal synchronizing signal, and n / m = k + 0.5 (m
Is a positive integer and a multiple of 2, and k is a positive integer).
By using a flag signal switched between inversion and non-inversion with a frequency-divided signal divided by a double value, two sampled color difference signals are thinned out, time-division multiplexed, and transmitted, so that the number of data thinned out is reduced to 0. Even if it has a fraction of 5, the data peripheral fraction is constant and the sampling points in the vertical direction are aligned, so that a memory such as a comb filter may be simply a shift register type memory, and it is not necessary to perform complicated address control.

Further, since the data can be thinned out by a factor of 1/2 from the integer, the used capacity of the memory can be further reduced by half.

[Brief description of the drawings]

FIG. 1 is a timing chart for explaining the operation principle of a digital color signal processing method according to the present invention.

FIG. 2 is a timing chart for explaining the operation principle of the digital color signal processing method of the present invention.

FIG. 3 is a block diagram of an embodiment of a circuit to which the digital color signal processing method of the present invention is applied.

FIG. 4 is a timing chart for explaining the operation principle of a conventional digital color signal processing method.

[Explanation of symbols]

 Reference Signs List 101 demodulation circuit 102, 103, 108, 109 low-pass filter 104 thinning circuit 105 comb filter 106 reproduction processing circuit 107 interpolation circuit 110 modulation circuit 111 flag signal generation circuit

Claims (1)

(57) [Claims] 1. A clock frequency for sampling two color difference signals is set to n times (n is a positive integer) a horizontal synchronization signal frequency, and n / m = k + 0.5 (m is a positive integer and 2
Multiple, k is pre-integer value m that satisfies a positive integer) the relationship
A flag signal in which the polarity of the first frequency- divided signal obtained by frequency- dividing the clock frequency is inverted / non-inverted by the second frequency- divided signal obtained by frequency- dividing the clock frequency with a value twice the integer n. A digital color signal processing method characterized in that the two color difference signals sampled at the clock frequency are thinned to form a time-division multiplexed data sequence .