JPH029757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device that compensates for dropout of an input color video signal, and in particular,
The present invention relates to a memory device in which a frame synchronizer or the like that corrects the time axis of a color video signal to obtain an output signal asynchronous to an input signal has a dropout compensation function.

A typical application example of a memory device in which the memory clock and address can be given independently to the writing side and the reading side is as follows.
There is a frame synchronizer. This frame synchronizer is used to transmit and receive television signals between different synchronization systems, such as between a TV relay van and a broadcasting station, or between one broadcast station and another broadcast station. By sequentially writing data into the memory using a clock and sequentially reading it using the clock of another synchronous system, the frequency and phase differences between the two synchronous systems are compensated for, and effective synchronization between the two synchronous systems is achieved. It is a memory device that achieves

The signal input to such a memory device is
When a so-called dropout such as a partial dropout or a drop in level occurs, dropout compensation is required to replace this dropout portion with another normal signal.

Dropout compensation in conventional frame synchronizers is generally performed by replacing the dropout portion with a television video signal from one horizontal period ago (1H ago). This is because the line correlation on the screen is generally high. , is considered to be an effective method.

However, in the case of color television video signals, the carrier phase of the chroma component (color signal component) is inverted every 1H, so the 1H delayed signal cannot be directly replaced, and the luminance component ( Separate the Y component) and chroma component (C component),
It is necessary to replace the dropout portion with a signal obtained by inverting the carrier of the chroma component and then adding it to the luminance component. Therefore, Y-C separation is inevitably required, and signal deterioration at this time cannot be avoided, resulting in adverse effects such as image quality deterioration. Also,
The circuit configuration also requires a Y-C separation circuit and a color subcarrier inversion circuit, and in particular, when the input color video signal is digitized, the D-A
In addition, an A-D conversion circuit or a Y-C separation circuit using complicated digital processing is required, making it impossible to avoid increasing the size of the device and complicating the circuit configuration.

In view of these conventional circumstances, the present invention makes it possible to provide a dropout compensation function to a memory device such as a small frame synchronizer, thereby making it possible to reduce the amount of hardware required for miniaturization, and reducing image quality deterioration. The purpose of the present invention is to provide a memory device that realizes spatially better dropout compensation.

Hereinafter, preferred embodiments of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 1 is a block circuit diagram showing a first embodiment of the present invention. In FIG. 1, a frame memory 1 is provided as a main memory for storing at least one frame (=2 fields) of a color video signal. This frame memory 1
For example, RAM (Random Access Memory)
Consists of. The analog color video signal supplied to the input terminal 2 is sampled in the analog-to-digital converter 3 (hereinafter referred to as the A-D converter) using a sampling clock with a frequency of 4 _sc , which is four times the color subcarrier frequency _sc . One sample data is converted into, for example, an 8-bit digital encoded signal. The digital output from this A/D converter 3 is sent to a shift register 5 via a replacement switching circuit 4. This shift register 5 is
For example, as shown in FIG. 2, it is composed of eight lower shift registers 5 ₀ , 5 ₁ , ..., 5 ₇ corresponding to each bit D ₀ , D ₁ , ..., D ₇ of the 8-bit data. . These lower shift registers 5 ₀ ,
5 ₁ ,..., 5 ₇ are each 24 bits long (or
It has an internal capacity of 24 steps), and these
24 bits are output in parallel and supplied to eight lower latch circuits 6 ₀ , 6 ₁ , . . . , 6 ₇ . That is, the shift register 5 performs serial-parallel conversion, and the above 24 bits of data are stored in the respective lower shift registers 5 ₀ , 5 1 , 5 ₁ ,
..., ₅₇ , each of the lower latch circuits ₆₀ , ₆₁ , ..., ₆₇ of the latch circuit 6 immediately latches the 24-bit data. This latch operation is performed using the above sampling clock (frequency 4 _sc ).
24 cycles (this is one block of data)
This is done once per session. Further, the write operation from the latch circuit 6 to the frame memory 1 is performed by one write cycle W during 24 cycles of the sampling clock, which is one data block.
Let's do it.

The above write side (or input side) operations are performed by clock pulses synchronized with the synchronization signal and color subcarrier signal in the color video signal supplied to the input terminal 2. That is, a part of the color video signal from the input terminal 2 is sent to the write clock generation circuit 7, where the color subcarrier signal and horizontal and vertical synchronization signals from this input color video signal are extracted, and these signals are further processed. The above 4 _sc sampling clock synchronized with the signal and the write start signal STW which instructs the start of writing to frame memory 1.
is generated. For example, FIG. 3A shows a signal obtained by extracting the color subcarrier signal from the input color video signal and shaping the signal into a rectangular wave pulse with a duty of 50%. Based on the pulse signal of FIG. 3A, a signal as shown in FIG. 3B having four times the frequency 4 _sc and synchronized with the signal of FIG. 3A is generated using, for example, a PLL circuit. can be obtained. The signal shown in FIG. 3B is used as the sampling clock. Next, the pulse signal shown in FIG. 3B is frequency-divided by 1/6, for example, to obtain the pulse signal shown in FIG. 3C. This pulse signal shown in FIG. 3C is used to form the write cycle W described above, the read cycle R described later, and the like. Third
Divide the pulse signal in Figure B to 1/24 (or divide the pulse signal in Figure 3 C)
By dividing the pulse signal by 1/4), the pulse signal shown in FIG. 4D is obtained. Data for one period of the pulse signal (8.times.24 bits) shown in FIG. That is, for example, the third
The pulse signals shown in Figures B to D are sent to the control circuit 8, which supplies clock pulses to the shift register 5 and the latch circuit 6, and as shown in Figure 3E, the control circuit 8 supplies the clock pulses to the shift register 5 and latch circuit 6. Let the period T _B be the third
In any one of the four sections S ₁ to _{S 4} obtained by dividing into four sections by the pulse in Figure C,
It controls writing and reading operations of the frame memory 1. A dropout detection signal is also supplied to the control circuit 8 via a terminal 9, and based on this dropout detection signal, the replacement switching circuit 4 is switched and controlled to convert the dropout portion of the input color video signal with a delay of one field. Replace with color video signal.

Next, on the read side (or output side) of the memory device shown in FIG. 1, an operation symmetrical to that on the write side is performed. However, two systems, synchronous output and asynchronous output, are provided, and the latch circuit 11, shift register 12, etc. of the synchronous output system are
In response to the write-side clock pulse, that is, the clock pulse that is synchronized with the synchronization signal, color subcarrier signal, etc. in the input color video signal supplied to input terminal 2, the readout operation of the color video signal with a one-field delay is performed. Let's do it. This one
The field-delayed color video signal is sent to a replacement switching circuit 4, and is replaced with the input color video signal when a dropout occurs. In addition, the latch circuit 21, shift register 22, and D-A converter 23 of the asynchronous output system respond to the clock pulse on the read side, that is, the signal supplied to the asynchronous input terminal 25 from the output side device (not shown). The color video signal is read out with a delay of one frame in accordance with the clock pulse synchronized with the clock pulse.
This one frame delayed analog color video signal is taken out from the output terminal 24. Here, the asynchronous input terminal 25 is supplied with an output side synchronous system signal having an independent synchronous signal with respect to the input side synchronous system, and this signal is sent to the read clock generation circuit 26. This read clock generation circuit 26
The control circuit 8 generates a pulse signal similar to that shown in FIGS. 3A to 3D described above (however, the phase and frequency are independent of the input side) and a read start signal STR that instructs to start reading from the frame memory 1. send to A clock signal synchronized with the output side synchronous system from this control circuit 8 is applied to the latch circuit 21 of the asynchronous output system and the shift register 2.
Supplied to 2nd class.

Next, write and read control of the frame memory 1 by the control circuit 8 will be explained with reference to FIG. In FIG. 4, the write cycle for writing is indicated by W, the read cycle for the synchronous output system among the read cycles for reading is indicated by R ₁ , and the read cycle for the asynchronous output system is indicated by R ₂ . The priority order of these write and read operations is that R ₂ has the highest priority, followed by R 1 , R ₁ ,
It is marked W. In FIG. 4A, the data contents of one block (8×24 bits) latched in the latch circuit 6 are shown as b, c, d, . . . , respectively. Further, FIGS. 4B, C, and D show the write cycle W and read cycles R ₁ and R ₂ . In FIGS. 4A to 4C, the data b, c, d, . . . for each block latched in the latch circuit 6 is written to the frame memory 1 in the write cycle W of each block period. Also, in each block period, the read cycle R ₁ before this write cycle W
Then, 1 for each of the above data b, c, d, etc.
The data before the field is read from frame memory 1. Next, in FIG. 4D, a read cycle _R2 is arranged in the first section of the four sections of each block divided based on the synchronization signal on the output side, and in this read cycle _R2 , Data b, c, d of each block above,
Approximately 1 frame (= 2 fields) for ... etc.
The previous data, that is, one frame delayed, is read from the frame memory 1.

In addition, when all read and write operations of the frame memory 1 by the control circuit 8 are performed in synchronization with the synchronization signal on the output side, for example, each cycle R ₂ , R ₁ , W as shown in FIG. It may be arranged as follows.

Further, the control circuit 8 controls the writing and reading of the write cycle W and read cycles R ₁ and R ₂ and also specifies the address of the frame memory 1 at the same time. In this case, the read cycle
In R ₂ , it is sufficient to always specify the corresponding addresses one frame in advance, but in read cycle R ₁ , it is necessary to shift the read address by 1H depending on whether the field for which dropout compensation is to be compensated is an odd field or an even field. be. this is,
This is to match the phase of the subcarrier of the chroma component in the color video signal between the input color video signal and the 1-field delayed color video signal read out in read cycle _R1 (make them in phase).

That is, the phase of the subcarrier signal of the chroma component in the color video signal is as shown in FIG.
It is reversed every 1H and also every 1 frame (=2 fields). Therefore, the phase of the color subcarrier is 1H between the odd field CFI and the following even field CF.
Lines that are separated, e.g. O ₁ and E ₂ , are in phase, whereas lines with the same number, e.g. E ₁ and O ₁ , are in phase between an even field CF and the next odd field CF. Become. Therefore, for example, if a dropout occurs on the first line O ₁ of an odd field CF,
The control circuit 8 may simply output an address corresponding to the previous field in the frame memory 1, that is, an address specifying the first line _E1 of the even field CF. On the other hand, if a dropout occurs on the second line _E2 of the even field CF, simply using an address one field earlier will specify the second line _O2 of the odd field CF. , the phase of the color subcarriers becomes opposite. For this reason, for example, the third line of an odd field CF can be set by simply shifting the address by 1H in either direction from the previous address.
Specify O ₃ to perform dropout compensation using the color video signal of the in-phase subcarrier signal. Note that the signal FLD output from the write clock generation circuit 7 is a field identification signal for identifying the field of the input color video signal. The control circuit 8 receives this field identification signal.
Based on the FLD, the address of the line to be read from the frame memory 1 at the time of replacement is determined as described above.

As is clear from the above description, the feature of the memory device according to the present invention is that the color video signal of one field before is read out from the main memory such as a frame memory and replaced with the input color video signal to be compensated. The next step is to read out the previous color video signal which is alternately shifted by 1H between odd and even fields so as to match the phase of the subcarrier signal of this input color video signal.

Therefore, compared to the conventional replacement of 1H delayed signals, better compensation is achieved because lines that are spatially closer are used. Furthermore, since the continuity of the subcarrier signal of the chroma component is maintained, conventional Y-C separation is not necessary, and hardware can be reduced and image quality can be improved.

In addition, the main memory does not simply delay the color video signal by one field, but uses a control circuit to shift the readout line depending on whether the input color video signal is even or odd, thereby controlling the color subcarrier phase to match. Therefore, the memory device of the present invention can be applied almost directly to not only the NTSC system but also the PAL and SECAM systems. Moreover, since asynchronous reading is performed using a second read cycle that is synchronized with a synchronous system clock that is independent (asynchronous) from the writing side clock, it is possible to When transmitting and receiving color video signals between the two systems, it is also possible to effectively synchronize by absorbing the phase difference between the two synchronization systems, and is particularly useful for so-called frame synchronizers with dropout compensation function. Can be used.

Note that the present invention is not limited to the above-mentioned embodiments. For example, as the frame memory 1 serving as the main memory, an analog memory such as a CCD that stores analog data may be used. In this case, The input analog color video signal can be processed without performing AD conversion or DA conversion, and the circuit configuration is further simplified. In addition, various configurations are possible without departing from the gist of the present invention.

[Brief explanation of drawings]

All figures show embodiments according to the present invention; FIG. 1 is a block circuit diagram, FIG. 2 is a block diagram showing an example of the structure of the shift register 5 and latch circuit 6 in FIG. 1, and FIGS. Time chart showing clock pulse and data block units, Figure 4A
~E is write cycle W, read cycle R ₁ ,
Time chart to explain the allocation of R ₂ ,
FIG. 5 is a schematic diagram showing the relationship between odd and even fields and subcarrier phase. 1... Frame memory, 2... Color video signal input terminal, 4... Replacement switching circuit, 7... Write clock generation circuit, 8... Control circuit, 9... Dropout detection signal input terminal, 26... Read clock generation circuit.

Claims (1)

[Scope of Claims] 1. A main memory that stores color video signals for at least one field; and outputs the input color video signal to the main memory, and outputs the input color video signal to the main memory in accordance with a switching signal. a replacement switching circuit that replaces the color video signal read out from the main memory; and a color that is in phase with the color subcarrier of the line of the input color video signal to be replaced as the color video signal of the main memory that is replaced by the replacement switching circuit. and a control circuit for controlling the color video signal of a line preceding one field, which is a subcarrier phase, to be selected and read from the line memory in relation to the odd-evenness of the fields of the input color video signal. A memory device featuring: