JPH0435575A - Synchronizing signal separating circuit for muse signal - Google Patents

Abstract

PURPOSE:To easily separate the horizontal synchronizing signal of a MUSE signal with a simple circuit constitution by providing a comparing means which compares the A/D converted MUSE signal with all or partial bits of the output signal of a signal converting means and outputs a horizontal synchronism detection signal in the case of coincidence. CONSTITUTION:Signal converting means (9-bit S/P converters) 20 to 27 and 70 to 77 which delay the A/D converted MUSE signal by one horizontal period use inverters 60 and 80 to convert the pattern of the horizontal synchronizing signal outputted from delay means (480 bit shift registers) 50 to 57a to the same pattern as the horizontal synchronizing signal after one horizontal period. Comparing means (9-bit comparators) 40 to 47 compare the A/D converted MUSE signal with all or partial bits of the output signal of means 20 to 27 and 70 to 77 and output the horizontal synchronism detection signal in the case of coincidence. Consequently, the horizontal synchronism detection signal is outputted from comparing means to separate the synchronizing signal each time when the MUSE signal is the horizontal synchronizing signal. Thus, the horizontal synchronizing signal of the MUSE signal is easily separated with the simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a synchronization separation circuit that separates a horizontal synchronization signal from a MUSE signal.

[Prior Art] As a method for compressing the transmission signal band of a television signal, a multiple subsample transmission method using interfield and interframe offset subsampling is known. As one of the multiple subsample transmission methods, M
US E (Multiple 5ub-nyau
There is something called ist Sampling Encoding).

In the decoder of this MUSE transmission method, for still images, the signal for the past three fields that have been transmitted and the signal that has been transmitted for the current field are combined, that is, interframe interpolation processing and interfield Image reproduction is performed by performing interpolation processing. On the other hand, in the case of moving images, in order to prevent long edge blurring, image reproduction is performed using only the signals transmitted in the current field, that is, by performing intra-field interpolation processing. .

FIG. 3 shows the format of a television signal (MUSE signal) transmitted by the MUSE transmission method.

The sampling frequency of the MUSE signal is 16.2 MHz, and one line is sampled at 480 points.

As shown in the figure, the first 11 points of each line are horizontal synchronization signals HD.

The horizontal synchronization signal HD in the MUSE signal is not a negative polarity synchronization signal like a conventional television signal, but a positive polarity synchronization signal that exists on the same side as the video signal, and is roughly l
The waveform has a phase inversion for each line (as shown in FIG. 4).

The reason for this is to prevent the required dynamic range of the transmission line from being widened by the synchronization signal, to improve the S/N ratio, and to cancel the DC component of the synchronization signal to avoid the influence of even-numbered special harmonic distortion.

[Problems to be Solved by the Invention] Negative polarity synchronization signals can be well separated using a comparator or the like as is well known in the art, but since the horizontal synchronization signal HD is a positive polarity synchronization signal, this It was difficult to separate the horizontal synchronization signal HD.

Therefore, the present invention provides a synchronization separation circuit that can easily separate the horizontal synchronization signal of the %MUSE signal with a simple circuit configuration.

[Means for Solving the Problems] The present invention provides a delay means for delaying an A/D-converted MUSE signal by one horizontal period, and a pattern of a horizontal synchronization signal outputted from the delay means using an inverter. A signal conversion means for converting the signal so that it has the same pattern as the horizontal open lJl signal after the horizontal period, and an A/D converted MUSE.
Comparing means compares the signal with all or some bits of the output signal of the signal converting means and outputs a horizontal synchronization detection signal when they match.

[Operation] According to the above-described configuration, when the horizontal synchronizing signal is supplied to the signal converting means, the output signal is the same as the pattern of the horizontal synchronizing signal after the horizontal period.

Therefore, at the timing when the MUSE signal becomes equal to the horizontal synchronization signal, the signal conversion means outputs a signal having the same pattern as the synchronization signal.

As a result, each time the MUSE signal becomes a horizontal synchronization signal, the comparison means outputs a horizontal synchronization detection signal, and synchronization separation is performed.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

First, using Fig. 4, the horizontal synchronization signal H of the MUSE signal is
The waveform of D will be explained.

The waveform of the horizontal synchronization signal HD has an amplitude of 50% of the video signal, and when A/D conversion is performed using 8 bits per sample as described above, the video signal has a level of 1/256 to 256/256. Against, 64/256 to 192/256
has a level of Converting this value to hexadecimal data,
The price ranges from $40 to $CO ($ means 16 numbers).

Of the 11 points that make up the waveform of the horizontal synchronization signal HD, the 1st point and the 11th point are the boundaries between the video signal, so the level is not specified, and the level of the synchronization signal (i.e. $co or 40) is generally the average value of the video signal.

Therefore, the points that can be used for synchronization determination are nine points from the second point to the tenth point. Of these nine points, the first four points and the last four points are SCO or $40, and the middle point is $80.

FIGS. 2A and 2B show waveform data of odd-numbered and even-numbered horizontal synchronizing signals HD arranged in time series, respectively. Note that E in the figure shows the clock CK.

FIG. 1 shows an embodiment of the present invention, which utilizes the waveform data of the horizontal synchronizing signal HD as described above.

In the same figure, A/D conversion (not shown) is 16.2M.
MUSEIitSM (7) signals converted to 8-bit digital signals of 1 sample in synchronization with the Hz clock CK (bit 7 is MSB)
are supplied to input terminals 17 to 10, respectively.

Bit signals b1t7~ supplied to input terminals 17~10
bitO is supplied to serial input terminals of 9-bit serial/parallel conversion circuits (S/P conversion circuits) 27 to 20, respectively. A clock CK is supplied from an input terminal 30 to the S/P conversion circuits 27 to 20, and this clock CK
A shift operation is performed in the serial direction in synchronization with .

The signals output from the parallel output terminals of the S/P conversion circuits 27 to 20 are sent to 9-bit comparators 47 to 20, respectively.
40 is supplied to one parallel input terminal.

Further, the bit signal bi supplied to the input terminals 17 to 10
t7-bito are supplied to 480-bit shift registers 57-50, respectively. Shift register 57-5
Clock CK is supplied to input terminal 30, and a shift operation is performed in synchronization with this clock CK.

The output signal of the shift register 57 is inverted by an inverter 60 and then sent to a 9-bit serial/parallel conversion circuit (S
/P conversion circuit) 77 is supplied to the serial input terminal.

Further, the output signals of the shift registers 56-50 are supplied to serial input terminals of 9-bit serial/parallel conversion circuits (S/P conversion circuits) 76-70, respectively. S
A clock CK is supplied from the input terminal 30 to the /P conversion circuits 77 to 70, and a shift operation is performed in the serial direction in synchronization with this clock CK.

Signals output from the parallel output terminals of the S/P conversion circuits 77-70 are supplied to the other parallel input terminals of the comparators 47-40, respectively.

However, 5 of the parallel output terminal of the S/P conversion circuit wi77
The bit-th signal is inverted by an inverter 80 and then supplied.

The comparators 47 to 40 compare the signals supplied to one and the other parallel input terminals, and when they match, a high level "H" signal is output, and when they do not match, a low level "L" signal is output. Ru.

The output signals of the comparators 47 to 40 are the Nant gates 90
The output signal of this Nant gate 90 is supplied to a 4-bit shift register 100. A clock CK is supplied to the shift register 100 from an input terminal 30, and a shift operation is performed in the serial direction in synchronization with this clock CK.

Then, from the output side of the shift register 100, output terminal 1
10 is derived.

Next, the operation of the example shown in FIG. 1 will be explained.

Consider a case where waveform data of a horizontal synchronizing signal HD as shown in FIG. 2A is supplied to the input terminals 17 to 10.

MUSE signal SM supplied to input terminals 17-10! ,
t, and is delayed by one horizontal period by shift registers 57-50. Therefore, the waveform data of the signals output from the shift registers 57 to 50 becomes as shown in FIG.

Then, since the MSB signal output from the shift register 57 is inverted by the inverter 60, the S/P conversion circuit 7
The waveform data of the signals supplied to terminals 7 to 70 are as shown in FIG. 2C.

Since the 6th bit output signal from the parallel output terminal of the S/P conversion circuit 77 is inverted and supplied to the inverter 80, the waveform data of the signal supplied to the other parallel input terminals of the comparators 47 to 40 is , as shown in the second diagram, is the same as the waveform data of the MUSE signal S signal S child synchronization signal HD (shown in Figure A) supplied to the input terminals 17 to 10.

Therefore, when the waveform data of the horizontal synchronizing signal HD as shown in 211 mA is supplied to the input terminals 17 to 10, the output signals of the comparators 47 to 40 are all at high level rHJ, and from the Nant gate 90, As shown in FIG. 2F, a detection signal of the horizontal synchronization signal HD is output.

In this case, the output signal of the Nant gate 90 becomes low level "L" when the second point of the horizontal synchronizing signal HD is at the rightmost end of the comparators 47 to 40, so it takes 4 clocks to reach the 6th point which is the HD point. It is necessary to phase shift.

In this example, this phase shift is performed with a shift register 100. As a result, as shown in FIG. 2G, a signal that becomes low level "L" at the HD point is output to the output terminal 110 as a horizontal synchronization separation output.

Although the explanation is omitted, the second
T! The same operation occurs when the waveform data of the horizontal synchronizing signal HD as shown in IB is supplied, and the output terminal 110 has the following information:
As shown in Fig. 2G, the low level “L” at the HD point
” is output as the horizontal synchronization separation output.

As described above, according to this example, the horizontal synchronization signal HD can be separated with a simple circuit configuration.

In addition, since two inverters 60 and 80 are installed in the topmost pixel MSH, the Nantes gate 9 is used in areas other than the horizontal synchronization signal HD, for example, the video signal
The output of 0 becomes low level "L", and erroneous synchronization separation will not be performed.

Note that in the above embodiment, the A/D converted MUS
All 8 bits of the E signal SM are used to perform synchronization separation, but considering the influence of noise etc., it may be possible to configure the system without using, for example, the lower 2 bits. It will be done. According to this, the circuit scale can be reduced by the number of unused bits.

[Effects of the Invention] As described above, according to the present invention, synchronous separation can be reliably performed with a simple circuit including a shift register, an S/P conversion circuit, a comparator, and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the example shown in FIG. 1, FIG. 3 is a diagram showing the format of the MUSE signal, and FIG. 4 is a diagram showing the MUSE signal. FIG. 2 is a diagram showing a horizontal synchronization signal waveform of FIG. 10-1711...Input terminal 20-27.70-77...◆Serial/parallel conversion circuit 40-47...Fist comparator 50-57゜60.80-- 90 φ ・ 110 ・ ・ ・Shift register/inverter dispute Nant Gate/Output terminal 1111 → Sample number

Claims (1)

[Claims] (1) Delay means for delaying the A/D converted MUSE signal by one horizontal period; and an inverter to convert the horizontal synchronization signal pattern outputted from the delay means into the horizontal synchronization signal pattern after one horizontal period. Comparing all or part of the bits of the A/D converted MUSE signal and the output signal of the signal converting means with a signal converting means that converts them so that they are the same,
A synchronization separation circuit for MUSE signals, comprising comparison means for outputting a horizontal synchronization detection signal when they match.