JPH01303987A - Delay error correction device - Google Patents

Abstract

PURPOSE:To automatically correct a delay error with high accuracy by converting each input signal into a digital signal, converting the result into a signal phase-locked to a reference clock, detecting the delay error between signals and using a variable shift register so as to correct the error. CONSTITUTION:A synchronizing separator circuit 4 and a PLL circuit 5 generate a reference clock. Moreover, a phase detection circuit 6a, a phase modulation circuit 7a and an A/D converter 3a convert each signal of R, G, B into a digital signal by using a sampling clock phase-locked to its own synchronizing signal. Error detection means 12b, 12c detect a phase difference in the unit of clock period between a synchronizing signal of the digital R signal and each synchronizing signal of digital G and B signals. Then shift registers 13b, 13c apply correction in the unit of clock period so that the phase difference between the digital R signal and the digital G and B signals is zero.

Description

Detailed Description of the Invention [Field of Application in Business A] The present invention relates to a device that processes a plurality of human-generated signals, in which a delay error between input signals and a delay between each signal occurring within the processing device are detected. The present invention relates to a delay error correction device that removes errors.

[Prior art] Hereinafter, television signal (hereinafter referred to as rTVTV signal)
This will be explained using a processing device as an example.

In place of conventional TV signals such as NTSC and PAL, the practical use of TV signals that can provide higher definition and more realistic TV screens is being considered.

One of them, the high-definition signal, has 11 scanning lines.
It has 25 lines, a screen aspect ratio of 9:16, and a luminance signal bandwidth of 20 MHz, making it possible to transmit five times the amount of information as an NTSC signal.

For transmission of high-definition signals, a time division multiplex signal (hereinafter referred to as rTC14) is used, which allows single channel transmission and does not cause crosstalk between luminance signals and color difference signals.
No. X) is used.

FIG. 6 is a block circuit diagram showing the configuration of a conventional TCI encoder for TV signals, and FIG. 7 is a signal waveform diagram of each part for explaining its operation.

In Figure 6, (la), (lb), (lc
) are low-pass filters (hereinafter referred to as rLPFJ) that limit the bandwidth of the human-powered R, G, and B signals, respectively.
(2a), (2b).

(2c) is a clamp circuit that reproduces the DC component of each signal, (
3a), (3b), (3c) are analog R,
A/B converts G and B signals into digital R, G and B signals.
The D converter (lO) converts the manually generated R, G, and B signals into
A matrix circuit (U) that separates and outputs a luminance signal (hereinafter referred to as "Y signal") and two color difference signals (hereinafter referred to as "rPB and PR signal") is Y.

A time division multiplexing circuit (54) that converts the PB and PR signals into TCI signals separates and outputs a horizontal synchronization signal H3 and a vertical synchronization signal S from a synchronization signal (hereinafter referred to as "rSYNC signal"), and also outputs a The synchronization separation circuit (55) that outputs the pulse Pc is a PLL circuit that generates a clock signal synchronized with the horizontal synchronization signal H3. A digital LPF is included to limit the

Next, the operation will be explained. Input analog R, G
, the form of the B signal is shown in Fig. 7 (a), (b), (
° as shown in c). Here, IH represents one horizontal scanning period. of each signal! The H period consists of a video signal period and a horizontal blanking period.

As shown in FIG. 7(d), the 5YNC signal has a negative polarity pulse during the horizontal blanking period and the vertical blanking period (not shown). The PLL circuit (55) receives the horizontal synchronization signal HS separated by the synchronization separation circuit (54) and generates a clock signal synchronized therewith. On the other hand, L P F (la), (lb), (
The R, G, and B signals band-limited by lc) are clamped by clamp circuits (2a), (2b), and (2c), respectively, and the DC components are regenerated. The clamp pulse Pc used for this trimming is output from the synchronous separation circuit (54). A/D converter (3a), (3b)
, (3c), the R, G, and B signals are connected to the PLL circuit (55)
sampled by a clock signal that is the output of
Converted to digital JG, B signals. The matrix circuit (10) converts the digital R, G, B signals into digital Y, PB, PRrg signals, and then converts the Pa,
A built-in digital LPF limits the bandwidth of the PR signal and outputs it to the station. The time division multiplexing circuit (55) is an IH
The unit is digital Y, PB, PR.
The time axis of the signal is compressed to 184th order, time division multiplexed, and a synchronization signal is added to create the TCI signal shown in FIG. 7(e). Here, the time axis compression ratio of the PB and PR signals is Y
The signal is three times as large. The TCI signal is then D/A converted by a D/A converter (not shown) and transmitted in the form of an analog signal.

When the TCI encoder configured as described above is applied to high-definition signals, the following problems occur. That is, Television Society Technical Report Vol. 1.11. N
o, 9. l) D, 13-18.1987, "About high-definition synchronization signal standards", in high-definition signals, between each channel (e.g.
The detection limit for delay errors for R, G, and B signals is 3.5 ns.

On the other hand, when R, G, and B signals are transmitted over 100 m using a coaxial cable, a delay time deviation of approximately ±15 ns may occur. In the TCI encoder shown in Fig. 6, coaxial cables and L P F (la), (
Since processing is performed regardless of the error in delay time caused by lb) and (lc), the time axis of each signal remains shifted from Y,
It may happen that it is converted to PR, PR signal or even TCI signal. And - ICT with the variable time axis shifted
Once converted to a signal, it is impossible to restore the original signal.

In the above literature, in order to detect the delay time difference of each signal,
It is proposed to add a ternary opening signal to each signal.

FIG. 8 is a block circuit diagram of the synchronous separation circuit shown in the document, and FIG. 9 is a signal waveform diagram of each part for explaining its operation. In Figure 8, (61)
is LPF, (62) is peak clamp circuit, (63)
, (66) is a comparator circuit, (64) is a monomulti circuit, (65) is a pedestal clamp circuit, (67)
) is an AND circuit.

Next, the operation will be explained. The input signal is a video signal to which a ternary opening signal as shown in FIG. 9(a) is added. Here, the three-value opening signal is a signal that changes in both positive and negative directions around the pedestal level LP. When the comparator circuit (63) in FIG. 8 detects that the input signal has become equal to or less than the negative threshold Ln shown in FIG. 9(a),
As shown in FIG. 9(b), the next-stage monomulti circuit (64) generates a high-level pulse for a predetermined period of time from that point onwards. On the other hand, the pedestal-clamped input signal is compared with the pedestal level Lp by the comparator (66), and the output of the comparator (66) has an output waveform as shown in FIG. 9(c), and the AND circuit (67) An AND operation is performed with the output of the monomulti (64) to obtain the output shown in FIG. 9(d). The rising edge of this output becomes the phase reference of the video signal. That is, by adding a ternary opening signal to each input signal, the phase reference of each input signal can be detected.

Note that the synchronization signal added to the input signal is not limited to a ternary waveform, but the above document shows that it is superior in terms of phase reference detection accuracy when compared to a binary waveform or a black burst. It has been reported.

In addition to the above literature, there has also been a proposal to add a synchronization signal to each of multiple input signals to obtain a phase reference for each signal, but after obtaining the reference phase, what method should be used to correct the delay error? It has not been disclosed whether this will be done.

[Problems to be Solved by the Invention] In conventional processing devices that receive a plurality of input signals, the delay error between each input signal is not corrected. For example, when processing a high-definition signal, the delay error between each signal is There is a problem in that there is a high possibility that the detection limit will be exceeded and the image quality will deteriorate.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a delay error correction device that can automatically and accurately correct delay errors between a plurality of input signals.

[Means for Solving the Problems] A delay error correction device according to the present invention includes means for generating a reference clock synchronized with a synchronization signal of a reference input signal among a plurality of input signals having the same type of synchronization signal. and,
A means for converting the reference clock into a digital signal using a sampling clock that is phase-modulated so that the phase of the reference clock is synchronized with the phase of the synchronization signal of each input signal, and converting these digital signals into a signal whose phase is synchronized with the reference clock. means for converting the respective signals; means for detecting a phase difference in units of a clock cycle between the synchronization signals of the respective digital signals whose phases are synchronized; and means for correcting the phase difference between the two.

[Operation] The reference clock generating means generates a reference clock whose phase is synchronized with the synchronization signal of the reference input signal. The means for converting into an input signal phase-modulates the reference clock so that its phase is synchronized with its own synchronization signal, and converts this clock into a digital signal as a sampling clock. The means for converting into a digital signal whose phase is synchronized with the reference clock corrects the phase difference between each sampling point of each digital signal. A phase detection circuit between synchronization signals of each digital signal detects a phase difference in clock cycle units between the synchronization signal of a reference digital signal and the synchronization signal of another digital signal. The phase difference correcting means corrects the phase of each digital signal so that each detected phase difference becomes zero.

[Embodiment of the Invention] An embodiment of the present invention will be described below based on the drawings. FIG. 1 is a block circuit diagram showing the configuration of a TCI encoder, and the portion surrounded by a dashed line indicates the delay error correction device of this embodiment. In the same figure, (la) to (3c
), (10), and (11) are the same as in FIG. 6, so their explanation will be omitted. (4) is a synchronous separation circuit, (5) is a PLL circuit that generates a reference clock, (6a), (
8b) and (6c) are phase detection circuits that detect the phase difference between the reference clock and the synchronization signal of each input signal. (7a
), (7b), (7c) are phase modulation circuits, and phase detection circuits ([ia), (5b), (
The reference clock output from the PLL circuit (5) is phase-modulated in accordance with the output of the PLL circuit (5). (8a), (8b)
, (8c) is a timing circuit, which is composed of a FIFO circuit that can perform writing and reading asynchronously. (9) is a shift register with a fixed delay amount, (
12b) and (12c) are error detection circuits, each of which detects a delay error (phase difference) in clock cycle units of the G signal and the B signal when the R signal is used as a reference; (+3b);

(13c) is a shift register whose delay amount changes according to the outputs of the error detection circuits (12b) and (12c), respectively. FIG. 2 is a block diagram showing an example of the configuration of the phase detection circuit (6a) and the phase detection circuit (7a), including the phase detection circuit (6b), (6c) and the phase modulation circuit (7a).
b) , ('Ic) are similarly constructed. In the figure, (41) and (43) are comparator circuits, (
42) is a mono multi circuit, (44), (45a)
, (45b) is a latch circuit, (46a) , (46
b) is a subtraction circuit, (47) is a ROM circuit, and (48) is a delay circuit, where the period of the reference clock is T and M is an integer, and the delay time is from d=T/M to (M-1)d. It consists of (M-1) delay elements that increase in d steps up to d.

(49) is a selector circuit.

FIG. 3 is a block circuit diagram of an example of the configuration of the error detection circuit (12b), and the error detection circuit (12c) is similarly configured. In the figure, Hla) and (31b) are comparator circuits that determine the magnitude of manually input digital signals, and (32) are comparator circuits H1a) and (31b).
), the counter control circuit (34) receives the output of the counter (33) and generates a control signal for the next stage counter (33).
), and (35) is a ROM circuit that uses the output of the latch circuit (34) as an address signal.

In this embodiment, the synchronous separation circuit (4) and the PL
The L circuit (5) constitutes a reference clock generation means.

In addition, the phase detection circuit (6a), phase modulation circuit (7a), and A/D converter (3a) constitute means for converting the R signal into a digital signal using a sampling clock that is phase-synchronized with its own synchronization signal. , G signal system, and B signal system.

In addition, timing circuits (8a), (8b) and (
8C) constitutes means for synchronizing the phase of the sample points of the digital R9G and B signals with the phase of the reference clock.

Further, the error detection means (12b) and (12c) constitute means for detecting a phase difference (delay error) in clock cycle units between the synchronization signal of the digital R signal and each synchronization signal of the digital G signal and B signal. are doing.

Further, the shift registers (13b) and (+3c) constitute means for correcting the phase difference between the digital R signal and the digital G and B signals in clock cycle units so that the phase difference becomes zero.

Next, the operation of the above configuration will be explained.

The R, G, and B signals, which are input signals, are shown in Figure 9 (a).
) is added to the three-value opening signal.

In addition, the synchronization separation circuit (4) includes L P F (61) and peak clamp circuit (62) among the configurations shown in FIG.
, comparator circuit (63) and mono-multi circuit (6
It is composed only of the circuit system of 4), and is a mono multi-circuit (
64) as the horizontal synchronizing signal HS. P.L.
The L circuit (5) receives the horizontal synchronizing signal H5 and generates a reference clock. In this embodiment, the reference clock is R,
The R and G signals are phase-modulated in response to each synchronizing signal of the G and B signals.

It is configured to generate a sampling clock synchronized with the synchronization signal of the B signal.

First, the operations of the phase detection circuit (6a) and phase modulation circuit (7a) shown in FIG. 2 will be explained using the signal waveform diagram of each part shown in FIG.

A negative threshold value Ln is input to one input of the comparator (41). This threshold value Ln is shown in Fig. 4(a).
The level is set to be an intermediate value between the pedestal level Lp shown in and the level Lb of the lower side of the negative polarity synchronization part of the ternary opening signal. Incidentally, the falling time of the ternary open period signal from Lp to Lb and the falling time from the level Lt of the upper side of the positive polarity synchronization part to 1, p are both one period T of the reference clock, and are shown in the figure. Q marks represent sample points in the A/D converter (3a). A comparator (41) detects that the output value of the A/D converter (3a) is a threshold value Ln at time tl.
Detects the following: In response, the monomulti circuit (42) outputs a high-level signal from time tl to t3, as shown in FIG. 4(b). selector(
49) outputs the reference clock as it is, regardless of the output of the ROM (47), when the output of the monomulti (42) is at a high level. Next, at time t2, when the comparator (43) detects that the output value of the A/D converter (3a) has become equal to or higher than the pedestal level Lp, the output value of the A/D converter (3a) at that time Latch B (45b)
In addition, the output value A of one clock previous held in the latch (44) is latched to (45a). Subtractor (46a).

(46b) calculates (Lp-A) and (B-Lp), respectively, and outputs them as addresses of ROM (47).

The ROM (47) has a selector (49) that determines how far the reference clock should be shifted in order to make the reference phase point the sampling point, depending on the value of the address.
), control data is written to select the output of the delay element having the same phase from among M delay clocks with a delay amount of 0 to (M-1)d. Therefore, after the output of the monomulti (42) becomes low level at time t3, the output of the phase modulator (7a) is always in a predetermined phase relationship with the latter half of the ternary opening signal and the video signal part. It becomes a clock. (For example, as shown in FIG. 4(a), the start and end points of the falling part of the positive pulse of the ternary opening signal coincide with the sample points.) In FIG. (8a) is composed of a FIFO circuit, and book loading control is performed using the output of the phase modulation circuit (7a).
That is, it is performed using a phase modulated clock, and reading is performed using a reference clock. Timing circuit (8
The delay time Td between input and output in a) is expressed as Td = (K±α)T where K: an integer of 2 or more α: 0≦α×1.

The operations up to conversion into digital signals in the G signal system and the B signal system are the same, but the timing circuit (8
In b) and (8c), the above value is set to be larger than the ' value of the timing circuit (8a), so that it always lags behind the output of the timing circuit (8b) and (8c). Here, when comparing the output of the timing circuit (8a) with the outputs of the timing circuits (8b) and (8c), the delay time difference is an integral multiple of the clock cycle T. That is, the phase correction for the clock cycle T or less has been completed, and the remaining correction in units of T is performed as follows. Note that the explanation will be given for the G signal system, but the same applies to the B signal system.

The R signal passes through a shift register (9) with a fixed delay amount, while the G signal passes through a shift register (1) with a variable delay amount.
3b). Therefore, the shift register (13b)
The delay error between the R and G signals is eliminated by determining the amount of delay in the error detection circuit 1 (12b) based on the relationship between the outputs of the timing circuits (8a) and (8b). Here, of course, the shift register (1
The amount of delay in 3b) is smaller than the amount of delay in shift register (9).

Next, the operation of the error detection circuit (12b) shown in FIG. 3 will be explained using the signal waveform diagram of each part left in FIG.

Although this circuit is not shown in the figure, the phase detection circuit (6
It is configured to be in an operating state when at least one of the R signal and the G signal is input in response to the output of the mono multi-circuit (42) (shown in FIG. 2) in a). Outputs A (shown in FIG. 5(a)) of the timing circuit (8a) and outputs of timing circuit (8b) (shown in FIG. 5(b)) are input to comparators (31a) and (31b), respectively, and a common It is compared with a threshold value Lq. Figure 5 (a)
, (b) are comparators (31a), (31b
) is shown in the form of an analog signal, and the ○ marks in the figure are sample points. Comparator (31a).

The output of (31b) is shown in Fig. 5(c), respectively.
(d). The counter control circuit (32) is
Using the outputs of the comparators (31a) and (31b) as inputs and the reference clock, Fig. 5(e),
Outputs the signals O, Power, and K shown in (f) and (g). The signal section is a signal that specifies the counting operation period of the counter (33), the signal power is a signal that gives the timing to preset the count value of the counter (33) to a predetermined value, and No. 2 is a latch circuit ( This is a signal used as a latch clock of 34). That is, the counter (3
3) is preset to a predetermined value in synchronization with the fall of the output of the comparator (31a), and a counting operation is started. Then, the counting operation stops in synchronization with the fall of the output of the comparator (31b), and the count value at that point is held in the latch circuit (34).

The ROM circuit (35) uses the output of the latch circuit (34) as an address input, and outputs data written in advance at each address. This data determines the amount of delay of the shift register (13b) shown in Figure 1, and is set so that the delay error between the output of the shift register (9) and the output of the shift register (13b) is 0. has been done. The shift register (13b) outputs a digital G signal whose delay error with respect to the digital R signal has been corrected.

Similarly, the shift register (13c) also outputs the digital B signal with the delay error corrected.1 As a result, the digital R1G and B signals without delay error are input to the matrix circuit (10). Become.

In the above embodiment, each signal has a three-value open signal, but the synchronization signal is not limited to this, and may be a negative polarity synchronization signal or a negative polarity synchronization signal and a sine wave. Other synchronization signals, such as a combination of burst signals, may also be used.

Further, in the above embodiment, a case where R, G, and B video signals are manually input is shown, but the input signal is not limited to this, and the same effect can be obtained if the input signal is a signal to which the same type of synchronization signal is added. is obtained.

Further, in the above embodiment, the reference clock is generated from the synchronization signal of the R signal using the synchronization separation circuit and the PLL circuit.
The configuration is not limited to this.

Further, although the shift register (9) is provided in the above embodiment, it can be omitted if the delay amount of the timing circuit (8a) is set larger than the delay amount of the other timing circuits (8b) and (8c).

Furthermore, the phase detection circuit 1 phase modulation circuit shown in FIG.
The error detection circuit shown in FIG. 3 may have any configuration as long as it has the same function.

[Effects of the Invention] As described above, according to the present invention, a reference clock is phase-modulated using synchronization signals of a plurality of input signals to obtain a clock phase-synchronized with the synchronization signal of each input signal, and these are used as sampling clocks. After each input signal is converted into a digital signal, each digital signal is converted into a signal that is phase-synchronized with the reference clock, and the delay error between each signal is detected and the delay error is corrected using a variable shift register. With this configuration, it is possible to obtain a delay error correction device that can automatically correct delay errors between a plurality of signals with high precision.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of a delay error correction device and a TCI encoder using the device according to an embodiment of the present invention, and FIG. 2 shows an example of the configuration of a phase detection circuit and a phase modulation circuit of this embodiment. 3 is a block circuit diagram showing a configuration example of the error detection circuit of this embodiment, and FIG. 4 is a signal waveform diagram of each part to explain the operation.
Figure 5 is a signal waveform diagram of each part to explain its operation.
Fig. 6 is a block circuit diagram showing the configuration of a conventional TCI encoder, Fig. 7 is a signal waveform diagram of each part to explain its operation, and Fig. 8 shows the configuration of a synchronization separation circuit described in a known document. The block circuit diagram shown in FIG. 9 is a signal waveform diagram for explaining its operation. (3a), (3b), (3c) -A/D
Converter, (4) ... Synchronous separation circuit, (5) ・P
L L circuit, (6a), (6b), (6c)
・-Phase detection circuit, (7a), (7b), (7c
)--phase modulation circuit, (8a), (8b),
(8c) ...timing circuit, (9), (13
b), (13c)...shift register circuit, (1
2b), (12c)...Error detection circuit. In each figure, the same reference numerals indicate the same or corresponding parts. Figure 2 Figure 4

Claims (1)

[Claims] (1) Means for generating a reference clock that is synchronized with the synchronization signal of a reference input signal among a plurality of input signals having the same type of synchronization signal, and the phase of this reference clock is set to the phase of the synchronization signal of each input signal. means for converting each of the input signals into digital signals using sampling clocks that are phase-modulated so as to be synchronized; means for converting these digital signals into signals whose phases are synchronized with the reference clock; means for detecting a phase difference in units of a clock cycle between synchronization signals of respective digital signals synchronized with each other; A delay error correction device comprising means for correcting.