JPH04227164A - Vertical synchronizing signal separation circuit - Google Patents

Abstract

PURPOSE:To accurately and stably obtain a vertical synchronizing signal without changing the decode value of a decoder for a signal of vertical synchronous cycle different from an ordinary NTSC signal. CONSTITUTION:A vertical synchronous cycle detecting counter 12 generates a count synchronized with the vertical synchronous cycle of an inputted composite synchronizing signal (a). A counter 20 for vertical synchronizing signal generation generates a count to obtain the vertical synchronizing signal from the composite synchronizing signal (a). When a count value is not synchronized with the count value of the vertical synchronous cycle detecting counter 12, an AND gate circuit 13 outputs an H level, and the counter 20 for vertical synchronizing signal generation outputs a load (2). Thereby, both count values are phase-synchronized, and a D flip-flop 10 generates the vertical synchronizing signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronization signal separation circuit used in television receivers and the like, which separates and outputs a vertical synchronization signal from a composite synchronization signal.

0002

2. Description of the Related Art In television receivers and the like, a vertical synchronization signal separation circuit is used that separates and outputs a vertical synchronization signal from a composite synchronization signal in which a horizontal synchronization signal and a vertical synchronization signal are transmitted as a composite signal. . FIG. 4 is a block diagram showing a conventional vertical synchronization signal separation circuit, and FIG. 5 is a signal waveform diagram for explaining its operation.

In FIG. 4, a composite synchronization signal a shown in FIG. 5 is input to input terminal 1. In addition, the input terminal 2 is connected to the clock shown in FIG. 5 (hereinafter referred to as
2fh (denoted as clock b) is input. The composite synchronization signal a input to the input terminal 1 is input to the D flip-flop 3, and is also input to the D flip-flop 3 as a clock.
fh clock b is input. The output signal c of the D flip-flop 3 has a waveform shown in FIG. 5, and is input to one terminal of the D flip-flop 4 and the AND gate circuit 5. The above-mentioned 2fh clock b is input as a clock to this D flip-flop 4, and outputs an output signal d having a waveform shown in FIG. Then, it is input to the other terminal of the AND gate circuit 5. As shown in FIG. 5, the output signal d of the D flip-flop 4 is a signal obtained by delaying and inverting the output signal c of the D flip-flop 3 by one clock.

The output signal e of the AND gate circuit 5 has a waveform shown in FIG. 5, and is input to the clear terminal of the vertical synchronization signal generating counter 7. This vertical synchronization signal generation counter 7
If it is a standard NTSC signal, outputs the count g shown in FIG. This counts from 0 to 524 in one vertical period and inputs the count value to the decoder 8. The decoder 8 decodes the count values 523 and 4 of the vertical synchronization signal generation counter 7, and outputs decoded signals V523 and V4 shown in FIG. 5. decode signal V
523 is one NA constituting the RS flip-flop 9
The decode signal V4 is sent to the ND gate circuit, and the decode signal V4 is sent to the other NAND gate circuit.
Input to gate circuit. Then, the RS flip-flop 9 generates a signal k shown in FIG.
Enter 0. A signal obtained by inverting the 2fh clock b by the inverter 6 is input as a clock to the D flip-flop 10, and the D flip-flop 10 generates a vertical synchronizing signal m shown in FIG. 5 and outputs it from the output terminal 11.

[0005]

[Problems to be Solved by the Invention] However, in the above-mentioned conventional vertical synchronization signal separation circuit, it is sufficient if the vertical synchronization period is only a standard NTSC signal, but the vertical synchronization period of personal computers, VTR stills, etc. If the signal differs from the standard NTSC signal, there is a problem in that the decode value of the decoder 8 must be changed.

[0006]

[Means for Solving the Problems] In order to solve the problems of the prior art described above, the present invention provides a vertical synchronization signal separation circuit that separates and outputs a vertical synchronization signal from an input composite synchronization signal. a first counter that generates a count of vertical synchronization cycles using a detection signal generated from the vertical synchronization position detection means; and a first counter that generates a count of vertical synchronization cycles from the composite synchronization signal; a second counter that generates a count to obtain a vertical synchronization signal, a signal for decoding a predetermined count value of the second counter to obtain a vertical synchronization signal, and a count value of the second counter that is a predetermined count value of the second counter. a decoder that generates a signal indicating whether the first counter and the second counter are synchronized with the count value of the counter, and a detection signal generated from the vertical synchronization position detection means when the first counter and the second counter are not synchronized. means for generating a signal to cause a predetermined load to be generated on the second counter by a signal indicating whether or not it is synchronized with the first count value; and the vertical synchronization obtained by the decoder. The present invention provides a vertical synchronization signal separation circuit characterized in that it is configured to include vertical synchronization signal generation means for generating a vertical synchronization signal using a signal for obtaining a signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A vertical synchronization signal separation circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a vertical synchronizing signal separating circuit according to the present invention, and FIGS. 2 and 3 are signal waveform diagrams for explaining the operation of the vertical synchronizing signal separating circuit according to the present invention. In FIG. 1, the same parts as those of the conventional vertical synchronization signal separation circuit shown in FIG. 4 are given the same reference numerals.

In FIG. 1, a composite synchronization signal a shown in FIG. 2 is input to an input terminal 1. Also, input terminal 2 has 2fh
Clock b is input. Here, the operations of the D flip-flops 3, 4 and the AND gate circuit 5 are the same as those of the conventional vertical synchronization signal separation circuit shown in FIG. 4, and their respective output signals have the same waveform as shown in FIG. Omitted. The output signal e of the AND gate circuit 5 is input to the clear terminal of the vertical synchronization period detection counter 12, and is also input to one terminal of the AND gate circuit 13 and the clock terminals of the latch circuits 14 and 15.

The 2fh clock b is input to the clock terminal of the vertical synchronization period detection counter 12, which is cleared by the output signal e of the AND gate circuit 5, as shown in FIG. Outputs the count f. Since the output signal e of the AND gate circuit 5 is not output until the next vertical synchronization signal comes in, the count f of the vertical synchronization period detection counter 12 becomes as shown in FIG. This count f is the standard N
In the case of the TSC signal, that is, one vertical period is 525 counts with 2fh clocks b.

Since the latch circuit 14 uses the output signal e of the AND gate circuit 5 as a clock, it latches the count value 524 immediately before the vertical synchronization period detection counter 12 is cleared, and the latch circuit 15 and the comparison input to one input terminal of the device 17. Similarly to the latch circuit 14, the latch circuit 15 receives the output signal e of the AND gate circuit 5.
is used as a clock, the output of the latch circuit 14 is latched, and input to the other input terminal of the comparator 17. This comparator 17
compares the input output of the latch circuit 14 and the output of the latch circuit 15, and outputs a match pulse signal only when they match.

This coincidence pulse signal is input to the latch circuit 16 as a clock. Latch circuit 16 is latch circuit 1
The output signal of 5 is latched and input to the adder 18. This adder 18 adds 2 to the output signal value of the latch circuit 15 and inputs it to the input terminal Q of the comparator 19.

On the other hand, the vertical synchronization signal generation counter 20 counts up using the 2fh clock b as a clock and outputs a count g shown in FIG. This count g is then input to the input terminal P of the adder 19. The adder 19 compares the values input to the input terminals P and Q, that is, the count value of the count g, and the output signal value of the adder 18, and outputs a match pulse signal h only when they match. This coincidence pulse signal h is as shown in FIG. 2, and is input to the clear terminal of the vertical synchronization signal generation counter 20 to clear the count.

The count g of the vertical synchronization signal generation counter 20 is input to the decoder 21, and the count values 0, 2, and 6 are decoded to produce decoded signals V0, V2, and V6 as shown in FIG. 2, respectively. Output. These decoded signals V0, V2, V6 are sent to the RS flip-flop 2.
It is connected to input terminals 2 and 23 as shown. That is, the decode signal V0 is sent to the set input terminal of one of the NAND gate circuits constituting the RS flip-flop 22, and to the set input terminal of one of the NAND gate circuits constituting the RS flip-flop 22.
Input to the reset input terminal of the gate circuit. The decode signal V2 is input to the reset input terminal of the other NAND gate circuit of the RS flip-flop 22. The decode signal V6 is input to the set input terminal of the other NAND gate circuit of the RS flip-flop 23.

The RS flip-flop 22 generates an output signal i shown in FIG. 2, and inputs it to the D flip-flop 24. The output signal e of the AND gate circuit 5 is input to the clock input terminal of the D flip-flop 24. When the output signal e of the AND gate circuit 5 and the output signal i of the RS flip-flop 22 are maintained in the relationship shown in FIG. 2, the output signal n (not shown in FIG. 2) of the D flip-flop 24 is L.
(low) level. This output signal n is input to one input terminal of the AND gate circuit 13, and the output signal e of the AND gate circuit 5 is input to the other input terminal, but since the output signal n is at L level, the output signal j is at L level as shown in FIG. The output signal j is input to the load input terminal of the vertical synchronization signal generation counter 20,
Since it is at L level, no load occurs in the vertical synchronization signal generation counter 20.

Further, the RS flip-flop 23 generates an output signal k shown in FIG. 2, and inputs it to the D flip-flop 10. A signal obtained by inverting the 2fh clock b by the inverter 6 is input to the clock input terminal of the D flip-flop 10, and the D flip-flop 10 generates the vertical synchronization signal m shown in FIG. 2 and outputs it from the output terminal 11. As a result, a vertical synchronization signal m that is accurately synchronized with the input composite synchronization signal a can be obtained.

Next, when a vertical synchronization signal different from the vertical synchronization signal of the standard NTSC signal is received or when the screen is switched, the vertical synchronization signal generation counter 20 synchronizes with the input composite synchronization signal a. Figure 3 for the case where
Explain using. In this case, the count value of the vertical synchronization signal generation counter 20 is undefined, the output signal i of the RS flip-flop 22 becomes L level, and the timing with the output signal e of the AND gate circuit 5 is synchronized as shown in FIG. do not. In this case, the output signal n of the D flip-flop 24 becomes H (high) level as shown in FIG. Therefore, the output signal j of the AND gate circuit 13 becomes H level as shown in FIG.
Enter 0. If the count value at this time is N, the vertical synchronization signal generation counter 20 is loaded with "2" by the output signal j at H level. Then, the count g (g(1)) becomes as shown in FIG. In this case, the output signal h of the comparator 19 becomes h(1) (L level). Also, after one vertical period, the count g and the output signal h
As shown in FIG. 3, the timings are g(2) and h(2), and the output vertical synchronization signal m is synchronized with the input composite synchronization signal a.

[0017]

[Effects of the Invention] As explained above in detail, the vertical synchronization signal separation circuit of the present invention is configured as described above, so that
Even if the count generated by the vertical synchronization signal generation counter is not synchronized with the input composite synchronization signal, the vertical synchronization cycle detection counter always detects the vertical synchronization cycle and synchronizes with the detected detection signal. Since the vertical synchronization signal is generated using the NTSC signal, there is no need to change the decoding value of the decoder even for a vertical synchronization period different from that of a normal NTSC signal, and an accurate and stable vertical synchronization signal can be obtained. In addition, since everything is composed of digital circuits, I
It has extremely excellent practical effects, such as easy measurement of C conversion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a vertical synchronization signal separation circuit of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the vertical synchronization signal separation circuit of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the vertical synchronization signal separation circuit of the present invention.

FIG. 4 is a block diagram showing a conventional vertical synchronization signal separation circuit.

FIG. 5 is a waveform diagram for explaining the operation of a conventional vertical synchronization signal separation circuit.

[Explanation of symbols]

3, 4 D flip-flop 5, 13 AND gate circuit 10 D flip-flop (vertical synchronization signal generation means)
12 Vertical synchronization period detection counter (first counter)
20 Vertical synchronization signal generation counter (second counter) 21 Decoder

Claims (1)

[Claims] 1. A vertical synchronization signal separation circuit for separating and outputting a vertical synchronization signal from an input composite synchronization signal, comprising: vertical synchronization position detection means for detecting a vertical synchronization position of said composite synchronization signal; and said vertical synchronization position detection means. a first counter that generates a count of vertical synchronization cycles using a detection signal generated from the composite synchronization signal; a second counter that generates a count for obtaining a vertical synchronization signal from the composite synchronization signal; and a predetermined count of the second counter. a decoder that generates a signal for decoding the count value of the second counter to obtain a vertical synchronization signal and a signal indicating whether the count value of the second counter is synchronized with the count value of the first counter; If the counter No. 1 and the second counter are not synchronized, a detection signal generated from the vertical synchronization position detection means and a signal indicating whether or not they are synchronized with the first count value are used. , means for generating a signal to generate a predetermined load on the second counter, and vertical synchronization signal generating means for generating a vertical synchronization signal using a signal for obtaining the vertical synchronization signal obtained by the decoder. A vertical synchronization signal separation circuit comprising: