JP3327968B2 - Semiconductor integrated circuits for display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for display, and more particularly to a MOS digital semiconductor integrated circuit for receiving character data for teletext.

[0002]

2. Description of the Related Art In general, a display semiconductor integrated circuit is used to take in serial data as character data and transfer it to a decoder in order to display teletext on a television.

A conventional display semiconductor integrated circuit has a configuration as shown in FIG. In FIG. 4, data 2 of FIG.
0 ', a phase reference signal 20 transmitted immediately before the serial data 5 and having a phase with the serial data 5
, A comparator 16 that receives the output of the voltage-controlled oscillator 18 and outputs the phase difference between the two signals, a low-pass filter 17 that smoothes the phase difference output to a DC voltage, and a low-pass filter 17 that smoothes the phase difference output. A voltage-controlled oscillator 18 that controls an oscillation frequency by a phase difference output of the comparator 16 and outputs a clock synchronized with the serial data 5;
The output of the voltage controlled oscillator 18 is used as a clock (C). The shift register 19 takes in serial data to a D input. The decoder 21 converts the output of the shift register 19 into a character signal and displays the signal on a television. I have.

Next, the operation of this circuit will be described.
In order to synchronize the clock of the shift register 19 with the serial data, this circuit first uses a comparator 16 to output a reference signal 20 having a phase with the serial data and a voltage controlled oscillator that outputs the clock of the shift register 19. Compare the phase with the output of No. 18 and output the phase difference. By integrating the phase difference output by the low-pass filter 17,
The output is smoothed to DC voltage. The oscillation frequency of the voltage controlled oscillator 18 is changed according to the DC voltage value of the phase difference output, and a clock synchronized with the serial data is output. The shift register 19 captures the serial data by a clock synchronized with the serial data, and transfers the serial data to the decoder 21. The decoder 21 converts the serial data into a character signal and displays the character signal on a television.

[0005]

In this conventional display semiconductor integrated circuit, a circuit for synchronizing a clock for taking in serial data is an analog circuit composed of bipolar transistors. In addition, the output of the voltage controlled oscillator 18 fluctuates due to noise, and there is a possibility that a data capture error may occur.
Further, when the analog circuit is formed of MOS transistors, the frequency control and gain characteristics are poor compared to bipolar transistors, so that the characteristics of the voltage-controlled oscillator deteriorate. In addition, since the characteristics of the low-pass filter change depending on the constant and are externally mounted, there are disadvantages in that the cost of parts increases, the number of terminals increases, and the chip size increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display semiconductor integrated circuit which solves the above-mentioned drawbacks and solves the possibility of causing a data capture error.

[0007]

According to the present invention, there is provided a display semiconductor integrated circuit comprising: serial data which is character data for teletext; and n times asynchronous with the serial data.
Input clock, and the serial data rises
Ri and differentiating circuit for detecting the timing, the reset at the rising edge detection output of said serial data <br/> from the differentiation circuit, divides to 1 / n by the input clock of said n frequency multiplier, the serial data If the 1 / n frequency dividing circuit for outputting a synchronized clock, and a shift register for taking the serial data at the clock output from the 1 / n frequency dividing circuit, the output of the shift register to the character signal conversion And a decoder for displaying on a television. Further, in the display semiconductor integrated circuit of the present invention,
The serial data and the n times
A data flip-flop for inputting a periodic clock,
The Q output of the data flip-flop and the n-times frequency
Data latch that inputs and latches the
The logic of the serial data and the output of the data latch
Circuit, and inverts the output of the NAND circuit
And an INV circuit for performing the operation.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a display semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing components of the embodiment of FIG.
Ru timing diagram illustrating a No. waveform. As is clear from FIGS . 1 and 2, the display semiconductor integrated circuit of this embodiment is
The serial data 5 which is character data for teletext is differentiated, and a differentiating circuit 1 for detecting the rising edge of the serial data 5 is reset (R) by a change timing detection output 6 of the serial data 5 of the differentiating circuit 1, n times the period of the clock for transferring serial data 5, and inputs serial data 5 and asynchronous clock 9, the clock 9
Is divided by 1 / n to output a clock synchronized with the serial data 5, and the serial data 5 is fetched by the clock 7 output from the 1 / n frequency divider 2. It comprises a shift register 3 and a decoder 11 for converting the output of the shift register 3 into a character signal and displaying it on a television. The 1 / n frequency dividing circuit 2
Counts the clock n times by the data circuit and outputs 1 clock
Circuit. Shift register 3 and decoder 11
Is similar to that described in the prior art of FIG.
You.

FIG. 3 is a specific block diagram of the differentiating circuit 1 of FIG. 3, the differentiating circuit 1 includes a data flip-flop 12 for receiving serial data 5 forming the input data 4, a data latch 13 for receiving the output of the data flip-flop 12, and an inverted output of the data latch 13. That is, it is a circuit that takes the logical product of the Q (inverted value) output and the serial data 5 constituting the input data , and includes a NAND circuit 14 and an inverter 15 that output a pulse at the rise of the input data. Note that these NAND circuits 14 and INV15 are logical
It can also be replaced by an AND circuit. Differentiation described above
Serial data 5 is input to the input data of the circuit 1,
The clock is n times the cycle of serial data 5
Is input. That is, the data flip flip
Drop 12 is serial data at the rising edge of the clock.
Incorporate 5 Further, the data latch 13 has a clock
At the rising edge of the data flip-flop 12
Embed. Inverted output of data latch 13 (Q bar)
And the input data to obtain the differentiator
1 is the rising edge of the serial data 5 constituting the input data.
Detect rising.

Next , the operation of this differentiating circuit will be described with reference to FIG.
This will be described more specifically with reference to FIG. Circuit of this embodiment, the serial data 5 is character data for text broadcasting
To synchronize the clock 7 of the shift register 3
(Refer to FIG. 1) First, the serial data 5 is differentiated by the differentiating circuit 1, and the change timing detection output 6 of the serial data 5 is output.
Is output. The 1 / n frequency dividing circuit 2 is reset by the change timing detection output 6 of the serial data 5. 1
The / n frequency dividing circuit 2 divides the frequency of a clock 9 for transferring the serial data 5 (clock multiplied by n) by 1 / n and outputs the frequency. The 1 / n frequency dividing circuit 2 outputs a clock 7 synchronized with the serial data 5 by being reset by the detection output 6 representing the rising of the serial data 5.
The clock 7 causes the shift register 3 to take in the serial data 5. Here, the captured serial data 5
Is converted into a character signal by the decoder 11 and displayed on a television.

In this way, a clock synchronized with the serial data 5 which is character data for teletext can be generated, and the serial data 5 can be extracted and displayed on a television.

In FIG. 2, a time point T of the change timing detection output 6 is a time when the 1 / n frequency dividing circuit 2 newly starts frequency division.

[0013]

As described above, according to the display semiconductor integrated circuit of the present invention, the circuit configuration for synchronizing the clock for taking in serial data can be changed from an analog circuit using bipolar transistors to a digital circuit using MOS transistors. With the change, reduction of current consumption,
Data fetch errors caused by output fluctuations of the voltage-controlled oscillator due to noise are eliminated, and no external low-pass filter is required, eliminating the need for fewer terminals and external components, reducing chip area and cost. The effect of reduction is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a display semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms of respective parts in the embodiment of FIG.

FIG. 3 is a block diagram of a differentiating circuit of the embodiment shown in FIG. 1;

FIG. 4 is a block diagram of a conventional display semiconductor integrated circuit.

FIG. 5 is a timing chart of input data in FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 Differentiating circuit 2 1 / n frequency dividing circuit 3, 19 shift register 4, 20 input data 5 serial data 6, 8 change timing detection output of serial data 4 7 shift register clock 9 n times clock 10 1 / n frequency dividing Circuit counter value 11, 21 Decoder 12 Data flip-flop 13 Binary flip-flop 14 NAND circuit 15 Inverter circuit 16 Comparator 17 Low-pass filter 18 Voltage-controlled oscillator 20 'Input data

Claims (2)

(57) [Claims] 1. Serial data which is character data for teletext and an n-times cycle asynchronous with the serial data
Enter a clock, a differentiating circuit for detecting a rising <br/> timing of the serial data, from the differentiating circuit
A 1 / n frequency divider circuit that is reset by a rising edge detection output of the serial data, receives the n-times cycle clock, divides the frequency by 1 / n, and outputs a clock synchronized with the serial data; a shift register for taking the serial data at the clock output from 1 / n frequency dividing circuit, and converts the output of the shift register to the character signal, a semiconductor display which comprises a decoder to be displayed on the TV Integrated circuit. 2. The method according to claim 1, wherein the differentiating circuit includes the serial data and the serial data.
And a data flip-flop for inputting the clock having the n-times cycle, a Q output of the data flip-flop,
And data to be latched by inputting the clock of n times cycle
Latch, the serial data and the data latch
Circuit that takes the logic of the output of the NAND circuit
2. The display semiconductor integrated circuit according to claim 1, further comprising: an INV circuit for inverting an output of said display.