JP3617375B2 - Image processing apparatus and image display apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and an image display apparatus using the same.
[0002]
[Prior art]
Various electronic devices that handle image signals representing images have been developed. For example, there are a direct-view display device using a liquid crystal panel, a projection display device, a scan converter that converts an input image signal specification into an image signal with a different specification, and outputs the image signal. In these electronic devices, an analog image signal is converted into a digital image signal (hereinafter, this conversion process is referred to as “A / D conversion”), and various digital signal processes are often performed. For such A / D conversion and digital signal processing, a sample clock signal suitable for processing each input image signal is required. Since this sample clock signal is often not supplied, it is usually generated in each apparatus. This sample clock signal is usually generated by using a frequency synthesizer using a PLL to synchronize with a horizontal synchronizing signal among synchronizing signals (horizontal synchronizing signal and vertical synchronizing signal) included in the input image signal.
[0003]
[Problems to be solved by the invention]
FIG. 12 is an explanatory diagram showing an input image signal and a sample clock signal. FIG. 12A shows the analog image signal RGB included in the input image signal. 12B and 12C show the sample clock signal SCLK. The timing at which the signal level of the analog image signal RBG changes indicates the timing at which the luminance level of the image changes. Therefore, in order to realize stable image processing, it is preferable to sample at a stable timing at which the signal level of the analog image signal RGB does not change. Therefore, normally, the sample clock signal SCLK is constant with respect to the timing at which the signal level of the analog image signal RGB in FIG. 12A changes like the sample clock signal SCLK (I) shown in FIG. It is preferable to adjust so as to have a phase. However, the sample clock signal SCLK may be out of phase like the sample clock signal SCLK (D) shown in FIG. If the deviation amount ΔT is large, the analog image signal RGB may not be appropriately sampled. Further, there are cases where subsequent digital signal processing cannot be performed properly. The above problem is the same when the input image signal is not only an analog image signal but also a digital image signal.
[0004]
The present invention has been made to solve the above-described problems in the prior art, and reduces the phase change of the sample clock signal with respect to the input image signal, and performs image processing using the sample clock signal of an appropriate phase. It aims at providing the technology that can do.
[0005]
[Means for solving the problems and their functions and effects]
In order to solve at least a part of the problems described above, an image processing apparatus according to the present invention includes:
A sample clock generator for generating a sample clock signal used to process the input image signal;
A processing unit that processes the input image signal using the sample clock signal,
The sample clock generation unit detects the phase difference between an image signal change position, which is a position where the input image signal reaches a specific signal level, and an edge position of the sample clock signal. Detecting the phase change of the sample clock signal and adjusting the phase of the sample clock signal to absorb the phase change, thereby processing the phase of the sample clock signal with respect to the input image signal It is characterized by adjusting to a phase suitable for the above.
[0006]
In the image processing apparatus of the present invention, the sample clock generator adjusts the phase of the sample clock signal so as to absorb the change in the phase of the sample clock signal with respect to the input image signal. Can be adjusted. Thereby, the phase change of the sample clock signal with respect to the input image signal can be reduced, and image processing can be performed using the sample clock signal having an appropriate phase.
[0007]
In the image processing device, the first aspect of the sample clock generation unit is:
A delay adjusting unit that generates a delay synchronization signal by adjusting a delay amount of the synchronization signal synchronized with the input image signal;
A clock generator that generates the sample clock signal based on the delay synchronization signal,
The delay adjustment unit
A variable delay unit that delays the predetermined synchronization signal by a variable delay amount and outputs the delayed synchronization signal;
And a phase change absorbing unit that controls a delay amount of the variable delay unit so as to absorb a change in phase difference between the input image signal and the sample clock signal.
[0008]
According to the first aspect of the sample clock generating unit, the delay adjusting unit adjusts the delay amount of the delay synchronization signal, so that the clock generating unit converts the sample clock signal adjusted to a phase suitable for processing of the input image signal. Can be generated.
[0009]
In the image processing apparatus, a second aspect of the sample clock generation unit is as follows.
A clock generator for generating a reference clock signal for generating the sample clock signal based on a synchronization signal synchronized with the input image signal;
A delay adjustment unit that outputs the sample clock signal by adjusting a delay amount of the reference clock signal;
The delay adjustment unit
A variable delay unit that delays the reference clock signal by a variable delay amount and outputs the sample clock signal;
And a phase change absorption unit that controls a delay amount of the variable delay unit so as to absorb a change in phase difference between the input image signal and the sample clock signal.
[0010]
According to the second aspect of the sample clock generating unit, the variable delay unit adjusts the delay amount of the reference clock signal generated by the clock generating unit, thereby adjusting the phase adjusted to the phase suitable for the processing of the input image signal A clock signal can be generated.
[0011]
In the first and second aspects,
The phase change absorber is
A signal change detection unit that outputs a binary output signal whose signal level changes when the image signal change position is detected;
A phase comparator that detects a phase difference between the edge position of the binary output signal and the edge position of the sample clock signal;
The phase comparison unit latches the binary output signal from the signal change detection unit at a plurality of timings within a period of one cycle of the sample clock signal, and the latched multi-bit signal is converted into the image It is preferable to output as a phase difference signal indicating a phase difference between the signal change position and the clock signal change position.
[0012]
According to the above configuration, the phase difference between the image signal change position and the edge position of the clock signal can be easily detected. In particular, the binary output signal from the signal change detection unit is latched at a plurality of timings within a period of one cycle of the sample clock signal, and the latched multi-bit signal is converted into the image signal change position and the clock signal. Since it is held as a phase difference signal indicating the phase difference from the edge position, the processing period required to determine and process the change in phase difference between the image signal change position and the edge position of the clock signal is the period of the sample clock signal. There is no limit.
[0013]
Further, it is preferable that the phase change absorption unit controls the delay amount of the variable delay unit so that the phase of the sample clock signal with respect to the input image signal is maintained at a phase in a predetermined appropriate phase state.
[0014]
In this way, it is possible to absorb the change in the phase of the sample clock signal with respect to the input image signal and adjust the phase of the sample clock signal with respect to the input image signal so that the phase is maintained in a predetermined appropriate phase state. . Thereby, the phase change of the sample clock signal with respect to the input image signal can be reduced, and image processing can be performed using the sample clock signal having an appropriate phase.
[0015]
In the first and second aspects, the sample clock generation unit may be provided for each of a plurality of color signals included in the input image signal, and a sample clock signal may be generated for each color signal.
[0016]
According to the above configuration, it is possible to generate a sample clock signal adjusted to a phase suitable for processing for each color signal. Thereby, the phase change of the sample clock signal can be reduced for each color signal, and image processing can be performed using the sample clock signal having an appropriate phase.
[0017]
In addition, an image display apparatus can be comprised by providing the said image processing apparatus and the image display part which displays the image represented by the image signal output from the said image processing apparatus.
[0018]
Since the image display apparatus includes the image processing apparatus of the present invention, the phase change of the sample clock signal can be absorbed and stable image processing can be performed.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
A. First embodiment:
A-1. Configuration of image display device:
FIG. 1 is a block diagram showing a schematic configuration of an image display apparatus to which an image processing apparatus as a first embodiment of the present invention is applied. The image display apparatus 1000 includes an image processing unit 100 and an image display unit 200. The image processing unit 100 is a computer system that includes an input buffer unit 110, a sample clock generation unit 120, an AD conversion unit 130, an image conversion unit 140, a display clock generation unit 150, and a CPU 160. The image display unit 200 includes a liquid crystal panel 210 and a panel drive unit 220. The image processing unit 100 is a device for processing an image formed on the liquid crystal panel 210. The panel driving unit 220 may be provided in the image processing unit 100.
[0020]
The CPU 160 is connected to the sample clock generation unit 120, the image conversion unit 140, and the display clock generation unit 150 via the bus 162. Further, although not shown, the input buffer unit 110 and the AD conversion unit 130 are also connected. The CPU 160 sets processing conditions for each unit and directly controls the processing of each unit.
[0021]
The input buffer unit 110 divides the input image signal VS into three (for example, red (R), green (G), and blue (B)) analog image signals RSA, GSA, and BSA, a horizontal synchronization signal HS, and Output as a vertical synchronization signal VS. Note that these analog image signals RSA, GSA, and BSA may be collectively referred to as an analog image signal AS.
[0022]
When the image signal VS is a composite image signal in which a luminance signal, a color signal, and a synchronization signal are superimposed, the input buffer unit 110 outputs the synchronization signals HS and VS and the analog image signals RSA and GSA from the image signal VS. , BSA are separated from each other, and each signal is output to each supply destination. When the image signal VS is a component image signal that includes three analog image signals RSA, GSA, and BSA, and a horizontal synchronizing signal HS and a vertical synchronizing signal VS, the input buffer unit 110 receives each signal. Output to Each signal is adjusted to a specification that can be input to the supply destination of each signal.
[0023]
The sample clock generation unit 120 includes a delay adjustment unit 170 and a clock generation unit 180. FIG. 2 is a time chart showing the horizontal synchronization signal HS, the delay synchronization signal HSC, and the sample clock signal SCLK. The delay adjustment unit 170 delays the horizontal synchronization signal HS shown in FIG. 2A and outputs a delay synchronization signal HSC shown in FIG. As shown in FIG. 2C, the clock generation unit 180 synchronizes with the delay synchronization signal HSC and generates a clock signal having a frequency N times the frequency of the delay synchronization signal HSC (N is an integer equal to or greater than 1). Output as a sample clock signal SCLK. The sample clock signal SCLK is supplied to the AD conversion unit 130 and the image conversion unit 140. Such a clock generation unit 180 can be realized by a frequency synthesizer.
[0024]
Note that “the delay synchronization signal HSC and the sample clock signal SCLK are synchronized” means, for example, that the rising edge position (timing) of the delay synchronization signal HSC and the rising edge position (timing) of the sample clock signal SCLK are in a constant phase. It means keeping a relationship. Therefore, even if the phase of the delay synchronization signal HSC with respect to the horizontal synchronization signal HS changes according to the delay amount, the phase relationship between the delay synchronization signal HSC and the sample clock signal SCLK maintains a constant relationship. In the present embodiment, as shown in FIG. 2C, the rising edge position of the sample clock signal SCLK is set to be substantially equal to the rising edge position of the delay synchronization signal HSC. As a result, the phase relationship between the horizontal synchronization signal HS and the sample clock signal SCLK can be adjusted by adjusting the delay amount of the delay synchronization signal HSC. Since the analog image signal AS is synchronized with the synchronization signal HS, the phase relationship between the analog image signal AS and the sample clock signal SCLK is also adjusted by adjusting the phase relationship between the synchronization signal HS and the sample clock signal SCLK. can do.
[0025]
The value of the frequency multiplication number N is set by the CPU 160 so that the sample clock signal SCLK having a frequency suitable for the processing of the AD conversion unit 130 is generated according to the input image signal VS. The configuration and operation of the delay adjustment unit 170 will be described later.
[0026]
The AD conversion unit 130 includes three AD converters 130R, 130G, and 130B in the AD conversion unit 130. The three analog image signals RSA, GSA, and BSA output from the input buffer unit 110 are converted into digital image signals RSD, GSD, and BSD based on the sample clock signal SCLK in the corresponding AD converters 130R, 130G, and 130B, respectively. The The digital image signals RSD, GSD, and BSD may be collectively referred to as a digital image signal DS.
[0027]
The image conversion unit 140 has a function of writing and reading the digital image signal DS to and from the image memory 142, and also has a function of enlarging / reducing an image, adjusting a screen display position, and the like. . With these functions, the image conversion unit 140 converts the digital image signal DS output from the AD conversion unit 130 into a digital image signal LDS adapted to the specifications of the liquid crystal panel 210 of the image display unit 200. Various processing conditions of the image conversion unit 140 are set by the CPU 160.
[0028]
The process of writing the digital image signal DS to the image memory 142 is performed in synchronization with the synchronization signals HS and VS and the sample clock signal SCLK. Further, the process of reading the image data from the image memory 142 is performed in synchronization with the horizontal synchronization signal RHS, the vertical synchronization signal RVS, and the display clock signal RCLK output from the display clock generation unit 150. Normally, the synchronization signals RHS and RVS are asynchronous with the synchronization signals HS and VS. However, the synchronization signals RHS and RVS may be synchronized with the synchronization signals HS and VS.
[0029]
The display clock generation unit 150 generates a horizontal synchronization signal RHS, a vertical synchronization signal RVS, and a display clock signal RCLK. These signals RHS, VHS, and RCLK are generated so as to satisfy specifications such as frequency and timing required for displaying an image on the liquid crystal panel 210. The operating conditions of the display clock generation unit 150 are set by the CPU 160 according to the specifications of the liquid crystal panel 210.
[0030]
The digital image signal LDS output from the image conversion unit 140 and the synchronization signals RHS and VHS and the display clock signal RCLK output from the display clock generation unit 150 are supplied to the panel drive unit 220. An image corresponding to the digital image signal LDS is formed on the liquid crystal panel 210 according to the synchronization signals RHS and VHS and the display clock signal RCLK.
[0031]
Note that a projection optical system for projecting an image formed on the liquid crystal panel 210 may be provided in the image display unit 200 to provide a projection display device. In this case, an image formed on the liquid crystal panel 210 is projected and displayed.
[0032]
A-2. Configuration of delay adjustment unit:
FIG. 3 is a block diagram illustrating an internal configuration of the delay adjustment unit 170. The delay adjustment unit 170 includes a variable delay unit 300, an initial phase setting unit 320, a phase change absorption unit 330, and a data addition unit 310. The variable delay unit 300 outputs the delay synchronization signal HSC by delaying the horizontal synchronization signal HS by a delay amount set according to the delay control data DC.
[0033]
FIG. 4 is a block diagram illustrating an example of the internal configuration of the variable delay unit 300. The variable delay unit 300 includes a delay unit 302 having n-1 (n is an integer of 2 or more) delay elements DLA (1) to DLA (n-1) connected in series, and a selector 304. ing. The horizontal synchronization signal HS is input to the first-stage delay element DLA (1), and the delay elements DLA (1) to DLA (n−1) in each stage sequentially delay the horizontal synchronization signal HS. Synchronization signals HSC (1) to HSC (n-1) are output. The numbers in parentheses indicate the order of series connection. Delayed synchronization signals HSC (0) to HSC (n-1) are sequentially input to n inputs S0 to Sn-1 of the selector 304. The delay synchronization signal HSC (0) is the horizontal synchronization signal HS input to the first-stage delay element DLA (1). The selector 304 has a function of outputting one of the n inputs S0 to Sn-1 from the selection output SLO according to the delay control data DC. Here, assuming that the delay amount of each delay element DLA (1) to DLA (n−1) is Tds, the variable delay unit 300 has a delay range of 0 to ((n−1) · Tds). The delay amount can be set in n stages with the unit delay amount Tds. Therefore, the variable delay unit 300 outputs the delay synchronization signal HSC obtained by delaying the horizontal synchronization signal HS by a delay amount within a range of 0 to ((n−1) · Tds).
[0034]
The variable delay unit 300 can have various configurations other than the configuration illustrated in FIG. For example, the delay amount may be variable by including a plurality of delay elements having different delay amounts and selecting a combination of delay amounts according to the delay control data DC. That is, the variable delay unit 300 only needs to be capable of adjusting the delay amount according to the delay control data.
[0035]
The initial phase setting unit 320 in FIG. 3 outputs initial delay data DCI indicating the delay amount of the variable delay unit 300 in the initial state of the apparatus. In the initial state of the apparatus, the value of the delay absorption data DCD output from the phase change absorption unit 330 is zero, and the initial delay data DCI is output from the data addition unit 310 as delay control data DC.
[0036]
The delay amount of the variable delay unit 300 in the initial state of the apparatus is such that the phase of the sample clock signal SCLK is an appropriate phase for converting the analog image signal AS to the digital image signal DS in the AD conversion unit 130 in the initial state of the apparatus. Is set to be
[0037]
As the initial phase setting unit 320, for example, the configuration described in JP-A-10-133619 can be used. In this case, the phase of the variable clock delay unit 300 is set so that the phase of the sample clock signal SCLK becomes an appropriate phase for converting the analog image signal AS into the digital image signal DS by the AD converter 130 in the initial state of the apparatus. The amount of delay can be set automatically. Note that at least a part of the functions of the initial phase setting unit 320 can be realized by the CPU 160.
[0038]
The initial phase setting unit 320 may be configured to output initial delay data DCI obtained by manual adjustment while viewing an image displayed by the user in the initial state. Further, a configuration may be adopted in which fixed initial delay data DCI set in advance is output. As the fixed data, data set at the time of product shipment or manually set by the user may be used.
[0039]
In the present invention, the “initial state of the device” is a state when the initial delay data DCI is set, and means a state where the analog image signal GSA and the sample clock signal SCLK have an appropriate phase relationship. To do. Such an initial state is also referred to as an “appropriate phase state”.
[0040]
The phase change absorption unit 330 receives a green analog image signal GSA and a sample clock signal SCLK. When the phase relationship between the analog image signal GSA and the sample clock signal SCLK changes, the phase change absorption unit 330 outputs delay absorption data DCD for returning this to the phase relationship in the initial state of the apparatus. The data adder 310 adds the delay absorption data DCD to the initial delay data DCI output from the initial phase setting unit 320 and outputs the result. Details of the phase change absorber 330 will be described later.
[0041]
The delay amount of the delay synchronization signal HSC output from the variable delay unit 300 is adjusted according to the delay absorption data DCD. Thereby, the phase of the sample clock signal SCLK with respect to the analog image signal GSA is adjusted so as to maintain an appropriate phase set in the initial state of the apparatus.
[0042]
A-3. Configuration and operation of phase change absorber:
FIG. 5 is a block diagram illustrating a schematic configuration of the phase change absorber 330. The phase change absorption unit 330 includes a signal change detection unit 420, a phase comparison unit 440, and a phase change control unit 460.
[0043]
The signal change detection unit 420 includes a comparator 422 and a comparison level generation unit 424. Comparison level generation unit 424 outputs comparison level Vr according to level control data RVD output from phase change control unit 460. The comparison level generation unit 424 can be configured with a DA converter. Note that the comparison level generation unit 424 may be provided in the phase change control unit 460 so that the comparison level Vr is output from the phase change control unit 460 to the signal change detection unit 420.
[0044]
FIG. 6 is a timing chart showing the operation of the comparator 422. The comparator 422 compares the input green analog image signal GSA with the comparison level Vr as shown in FIG. 6A, and outputs a detection signal VES as shown in FIG. 6B. The detection signal VES changes from the L (low) level to the H (high) level at the timing Tcu when the signal level of the analog image signal GSA becomes higher than the comparison level Vr, and the signal level of the analog image signal GSA is higher than the comparison level Vr. This is a binary output signal that changes from the H level to the L level at a timing Tcd that becomes smaller.
[0045]
Here, the signal level of the analog image signal represents the luminance level of the image, and the “image signal changing position that is a position that reaches a specific signal level of the input image signal” in the present invention refers to the luminance level of the image. It means the timing when it becomes larger or smaller than a certain luminance level. The signal change detection unit 420 according to the present embodiment compares the timing at which the signal level of the green analog image signal GSA changes with a certain comparison level Vr and the analog image signal GSA by the comparator 422, whereby the rising edge of the detection signal VES. Output as edge (timing) or falling edge (timing). Therefore, the detection signal VES is a signal indicating the timing at which the specific signal level of the analog image signal GSA changes, and the phase relationship between the edge of the detection signal VES and the edge of the sample clock signal SCLK is the same as that of the analog image signal GSA This is almost equivalent to the phase relationship with the clock signal SCLK. Further, normally, when the phases of the three analog image signals are substantially equal, the phase relationship between the edge of the detection signal VES and the edge of the sample clock signal SCLK is the phase between the entire analog image signal AS and the sample clock signal SCLK. It is almost equivalent to the relationship. Therefore, if the change in the phase relationship between the edge of the detection signal VES and the edge of the sample clock signal SCLK is checked, the change in the phase relationship between the analog image signal AS and the sample clock signal SCLK can be checked.
[0046]
Note that, instead of the green analog image signal GSA, the timing at which the signal levels of the red or blue analog image signals RSA and GSA change may be detected. However, as a change in the luminance level of the analog image signal, in general, the change in the luminance level of the green analog image signal is often large. Therefore, the use of the green image signal is advantageous in detecting a change in the luminance level of the image signal.
[0047]
Further, in the signal change detection unit 420 of this embodiment, the timing at which the signal level of the analog image signal GSA, that is, the luminance level of the image signal changes, is detected by comparing the analog image signal GSA with the comparison level Vr. However, the present invention is not limited to this. Any configuration is possible as long as the timing at which a certain luminance level of the analog image signal changes can be detected. For example, the change timing of the analog image signal can be detected by differentiating the analog image signal.
[0048]
The phase comparison unit 440 includes m-1 delay units 442 having delay elements DLB (1) to DLB (m-1) connected in series (m is an integer of 2 or more), and m latches LT ( 0) to LT (m−1), and a phase comparison / determination unit 446. The sample clock signal SCLK is input to the first-stage delay element DLB (1). Delayed clock signals (phase difference clock signals) DCK (1) to DCK (m−1) obtained by sequentially delaying the sample clock signal SCLK are output from the delay elements DLB (1) to DLB (m−1) of each stage. Is done. The numbers in parentheses indicate the order of series connection. Here, the delay amount between the delay clocks, that is, each delay amount of the delay elements DLB (1) to DLB (m−1) is Tdc. Therefore, the delay amounts of the delayed clock signals DCK (1) to DCK (m−1) with respect to the sample clock signal SCLK are (1 · Tdc) to ((m−1) · Tdc).
[0049]
The detection signal VES output from the signal change detection unit 420 is commonly input to the data input terminals of the latches LT (0) to LT (m−1). Further, the delayed clock signals DCK (0) to DCK (m−1) are sequentially input to the clock input terminal CK. However, the delayed clock signal DCK (0) is an input signal of the delay element DLB (1), that is, the sample clock signal SCLK. The enable signal EnS output from the phase comparison determination unit 446 is commonly input to the enable input terminal En, and the reset signal RSTS output from the phase change control unit 460 is commonly input to the reset input RST. Have been entered.
[0050]
Each of the latches LT (0) to LT (m−1) latches the detection signal VES at the rising edge of each of the input delayed clock signals DCK (0) to DCK (m−1), and each data output terminal The latch signals LD (0) to LD (m-1) are output from the QO. The m-bit latch signals LD (0) to LD (m−1) are input to the input terminals ID (0) to ID (m−1) of the phase change control unit 460.
[0051]
The phase comparison / determination unit 446 includes two AND gates 448 and 450 and a selector 452. The latch signal LD (0) is input to the input terminal A of the AND gate 448 and the input terminal B of the AND gate 450, and the latch signal is input to the input terminal B of the AND gate 448 and the input terminal A of the AND gate 450. LD (m-1) is input. The output of the AND gate 448 is input to the first input terminal SI1 of the selector 452, and the output of the AND gate 450 is input to the second input terminal SI2 of the selector 452. The output terminal SO of the selector 452 is connected to the enable input terminals En of the latches LT (0) to LT (m−1). The enable signal EnS input to each of the latches LT (0) to LT (m−1) is negative logic, and when the enable signal EnS is at the L level, each of the latches LT (0) to LT (m−1) Is enabled.
[0052]
The input terminals A of the AND gates 448 and 450 are negative logic inputs, and the input terminal B is a positive logic input. Therefore, the output of the AND gate 448 becomes H level only when the latch signal LD (0) is L level and the signal level of the latch signal LD (m−1) is H level. That is, the output of the AND gate 448 is that the detection signal VES is L level at the rising edge of the sample clock signal SCLK, and the detection signal VES is H level at the rising edge of the last delayed clock signal DCK (m−1). Yes. The output of the AND gate 450 becomes H level only when the latch signal LD (0) is H level and the signal level of the latch signal LD (m−1) is L level. That is, the output of the AND gate 448 is that the detection signal VES is at the H level at the rising edge of the sample clock signal SCLK, and the detection signal VES is at the L level at the rising edge of the last delayed clock signal DCK (m−1). Yes.
[0053]
The selector 452 is switched by the switching signal U / D output from the phase change control unit 460, and either the output of the first AND gate 448 or the output of the second AND gate 450 is used as the enable signal EnS. Output from the comparison determination unit 446. When the phase comparison is performed at the timing when the detection signal VES changes from the L level to the H level, the output of the first AND gate 448 is selected as the enable signal EnS, and the detection signal VES changes from the H level to the L level. When the phase comparison is performed at the timing, the output of the second AND gate 450 is selected. For example, when the output of the first AND gate 448 is selected as the enable signal EnS, each latch is activated when the latch signal LD (0) is at the L level and the latch signal LD (m−1) is at the H level. When disabled, the current output is held.
[0054]
The phase change control unit 460 generates a sample clock for the analog image signal GSA based on the latch signals LD (0) to LD (m−1) output from the m latches LT (0) to LT (m−1). The amount of change in the phase of the signal SCLK is detected, and delay absorption data DCD for adjusting the amount of delay of the variable delay unit 300 according to the amount of change is output.
[0055]
FIG. 7 is a timing chart showing the operation of the phase change absorber 330. In the following, an example will be described in which the phase change of the rising edge of the sample clock signal SCLK with respect to the rising edge (timing) at which the detection signal VES changes from the L level to the H level is detected. FIG. 7A shows the detection signal VES. 7B to 7G show the latches LT (0), LT (i-3), LT (i-2), LT (i) among the latches LT (0) to LT (m-1). -1), LT (i), LT (m-1), and delayed clock signals DCK (0), DCK (i-3), DCK (i-2), DCK (i -1), DCK (i), and DCK (m-1). i is an integer of 4 or more and m-2 or less, and indicates the number of stages of delay elements through which the sample clock signal SCLK passes. 7 (h) to 7 (m) show latches LT (0), LT (i-3), LT (i-2), LT (i-1), LT (i), and LT (m-1). ) Latched signals LD (0), LD (i-3), LD (i-2), LD (i-1), LD (i), LD (m-1) output from each data output terminal QO. Is shown. Further, FIG. 7 (n) shows the enable signal EnS, and FIG. 7 (o) shows the reset signal RSTS.
[0056]
As shown in FIGS. 7B to 7G, the delayed clock signals DCK (0),... DCK (i-3), DCK (i-2), DCK (i-1), DCK (i ),..., DCK (m−1) with respect to the sample clock signal SCLK is 0,... ((I-3) · Tdc), ((i-2) · Tdc), ((i-1) .Tdc), (i.Tdc),... ((M-1) .Tdc). Each delay amount Tdc of the delay elements DLB (0) to DLB (m−1) is set to satisfy Tc ≧ m · Tdc (Tc is one cycle of the sample clock signal SCLK). Therefore, each of the delay clocks DCK (0) to DCK (m−1) corresponds to a phase difference clock signal that is slightly different in phase within one cycle Tc of the sample clock SCLK of the present invention.
[0057]
Each of the latches LT (0) to LT (m−1) latches the detection signal VES at the rising edge of each of the delayed clock signals DCK (0) to DCK (m−1) inputted thereto, and outputs the respective data. Latch signals LD (0) to LD (m-1) are output from the terminal QO.
[0058]
As shown in the left half of FIG. 7A, the detection signal VES is L between the rising timing Ti-1 of the delayed clock signal DCK (i-1) and the rising timing Ti of the delayed clock signal DCK (i). When the level changes from the H level to the H level, the latch signals LD (0) to LD (i-1) based on the delayed clock signals DCK (0) to DCK (i-1) are represented by (h) to (k) in FIG. As shown in FIG. On the other hand, the latch signals based on the delayed clock signals DCK (i) to DCK (m−1) change from the L level to the H level as shown in FIGS.
[0059]
When the phase comparison is performed at the timing when the detection signal VES changes from the L level to the H level, the output of the first AND gate 448 of the phase comparison determination unit 446 is selected by the switching signal U / D. The output of the first AND gate 448 is the same as the enable signal EnS shown in FIG. 7 (n) when the latch signal LD (0) changes to L level and the latch signal LD (m−1) changes to H level. Change to H level. When the enable signal EnS becomes H level, the latches LT (0) to LT (m−1) stop the latch operation until they are reset by the reset signal RSTS shown in FIG. To maintain.
[0060]
At this time, since the levels of the latch signals LD (0) to LD (m−1) are switched between the two latch signals LD (i−1) and LD (i), the rising edge of the detection signal VES. Is between the rising edges of the two delayed clock signals DCK (i−1) and DCK (i) corresponding to these two latch signals LD (i−1) and LD (i). That is, the m-bit latch signals LD (0) to LD (m−1) output from the phase comparison unit 440 have the rising timing of the detection signal VES at any timing within one period of the sample clock signal SCLK. It shows whether there is.
[0061]
Here, the phase relationship changes as shown in the right half of FIG. 7A, and the rising timing Ti-3 of the delayed clock signal DCK (i-3) and the rising timing Ti of the delayed clock signal DCK (i-2). It is assumed that the detection signal VES has changed from L level to H level. That is, it is assumed that the phase of the sample clock signal SCLK changes by ΔT (2 · Tdc <ΔT <3 · Tdc) as shown in FIG. At this time, as shown in FIGS. 7H to 7M, the level of the latch signal is switched between the two latch signals LD (i-3) and LD (i-2). That is, the boundary between the levels of the latch signal is moved by an amount corresponding to the phase change amount ΔT of the sample clock signal SCLK as compared to before the phase change.
[0062]
From the above, among the latch signals LD (0) to LD (m−1) output from the phase comparator 440, the positions of two latch signals having different signal levels (hereinafter referred to as “latch signal boundary positions”). It can be seen that the change in the frequency corresponds to a change in the phase of the sample clock signal SCLK. Therefore, a change in the phase of the sample clock signal SCLK can be detected by detecting a change in the boundary position of the latch signal output from the phase comparison unit 440.
[0063]
FIG. 8 is a flowchart showing the operation of the phase change control unit 460. When the phase change control unit 460 starts the operation, in step S102, by monitoring the signal level of the enable signal EnS, the latch operation is stopped and the state in which the latch signal is maintained before the stop (hereinafter referred to as “stop”). Whether it is called “hold state”). If not in the hold state, monitoring of the signal level of the enable signal EnS is continued in step S102. If it is in the hold state, in step S104, the latch signals LD (0) to LD (m-1) are fetched as input data ID (0) to ID (m-1). Then, phase detection data PDD (PDD is an integer of 0 to (m−1)) indicating the phase difference between the detection signal VES and the sample clock signal SCLK from the input data ID (0) to ID (m−1) that has been taken in. ). For example, as shown in the left half of FIG. 7, when the input data is switched from 0 to 1 between ID (i−1) and ID (i), the value of the phase detection data PDD is i. It is determined. As shown in the right half of FIG. 7, when the input data is switched from 0 to 1 between ID (i-3) and ID (i-2), the value of the phase detection data PDD is (I-2).
[0064]
When setting the initial state of the apparatus, in step S108 of FIG. 8, the phase detection data obtained in step S104 is stored as initial phase data, and the process proceeds to step S114. If it is not the initial state, the difference between the initial phase data and the phase detection data is obtained in step S110. In step S112, delay absorption data DCD for absorbing a delay amount corresponding to the difference obtained in step S110 is output.
[0065]
For example, if the initial phase data that is phase detection data before the phase change (initial state) is i and the phase detection data after the phase change is i-2, the difference between the initial phase data and the phase detection data is determined to be −2. Is done. This is because the sample clock signal SCLK after the phase change is delayed by an amount corresponding to about twice as much as one delay amount Tdc of DLB (1) to DLB (m−1) compared to the phase before the phase change. It is shown that. Accordingly, the delay absorption data DCD for reducing the delay amount of the variable delay unit 300 by the delay amount (2 · Tdc) corresponding to this delay is set. One delay amount Tds of the delay elements DLA (1) to DLA (n−1) of the variable delay unit 300 of FIG. 4 is one of the delay elements DLB (1) to DLB (m−1) of the phase change absorber 330. If it is equal to the delay amount Tdc, -2 is set as the delay absorption data DCD, and the variable delay unit 300 is set so that the delay is reduced by a delay amount (2 · Tds) substantially equal to the delay amount (2 · Tdc). Is done. However, the delay amount Tds and the delay amount Tdc are not necessarily equal. When the delay amount Tds and the delay amount Tdc are not set equal, the delay absorption data DCD may be set according to the relationship between the delay amount Tds and the delay amount Tdc. However, it is convenient for the phase change control unit 460 to obtain the delay absorption data DCD when these delay amounts are equal.
[0066]
After the output of the delayed absorption data DCD, in step S114, as shown in FIG. 7 (o), a one-pulse signal that changes to H level is output as the reset signal RSTS, and the latches LT (0) to LT (m -1) is reset, and the hold state of each latch is released. Then, the processing from step S102 to step S114 is repeatedly executed until an operation end instruction is issued.
[0067]
Note that each of the latches LT (0) to LT (m−1) of the phase comparison unit 440 stops the latch operation and maintains the state before the stop until reset by the reset signal RSTS as described above. Can do. Therefore, the phase change control unit 460 can execute control without depending on the frequency of the sample clock signal SCLK and the change of the detection signal VES from the signal change detection unit 420.
[0068]
The delay absorption data DCD output from the phase change control unit 460 is added to the initial delay data DCI and supplied to the variable delay unit 300 as delay control data DC, as described with reference to FIG. The variable delay unit 300 delays the horizontal synchronization signal HS by a delay amount corresponding to the given delay control data DC until new delay control data DC is supplied, and outputs the delay synchronization signal HSC. The clock generator 180 (FIG. 1) generates the sample clock signal SCLK based on the delay synchronization signal HSC.
[0069]
The main function of the phase change control unit 460 is to change the phase of the sample clock signal SCLK based on the latch signals LD (0) to LD (m−1) output from the phase comparison unit 440 as described above. There is to ask. Therefore, the CPU 160 may execute the function of the phase change control unit 460.
[0070]
As described above, the phase change absorber 330 detects a change in the phase of the sample clock signal SCLK from the initial state, and adjusts the delay amount of the variable delay unit 300 so as to absorb this change. Thereby, the phase change of the sample clock signal SCLK is suppressed, and the sample clock signal SCLK is adjusted so as to maintain an appropriate phase.
[0071]
Note that, as described above, the delay absorption data DCD indicating the delay adjustment amount of the variable delay unit 300 in accordance with the phase change of the sample clock signal SCLK is the sample clock by the plurality of delay elements DLB (1) to DLB (m−1). It is indirectly determined based on the delay amount of the signal SCLK. Therefore, in order to realize highly accurate delay adjustment of the variable delay unit 300, the delay elements DLA (1) to DLA (n-1) of the variable delay unit 300 and the delay element DLB (1) of the phase comparison unit 440 are provided. It is desirable that the relative accuracy of the delay amount of ˜DLB (m−1) is as good as possible. For example, the relative accuracy of each delay is preferably several hundred ppm or less.
[0072]
As described above, the sample clock generation unit 120 operates in the delay adjustment unit 170 so as to absorb the phase change of the sample clock signal SCLK. Thereby, in the image display apparatus 1000 of the present embodiment, the phase change of the sample clock signal SCLK with respect to the analog image signal AS can be reduced, and image processing can be performed using the sample clock signal SCLK having an appropriate phase.
[0073]
In the above-described embodiment, the case where the phase change absorption unit 330 (FIG. 5) detects a change in the phase of the sample clock signal SCLK with respect to the timing at which the detection signal VES changes from the L bell to the H level is described as an example. However, the change of the phase of the sample clock signal SCLK with respect to the timing when the detection signal VES changes from the H level to the L level may be detected. In this case, the output of the second AND gate 450 of the phase comparison determination unit 446 is selected by the switching signal U / D. The enable signal EnS changes to H level when the latch signal LD (0) changes to H level and the latch signal LD (m−1) changes to L level, and the latches LT (0) to LT (m−1). ) Stops.
[0074]
In the above-described embodiment, one delay amount Tdc of the delay elements DLB (1) to DLB (m−1) is set so as to satisfy Tc ≧ m · Tdc (Tc is one cycle of the sample clock signal SCLK). The case where the frequency of the sample clock signal SCLK is a constant frequency is described as an example. However, there are various specifications for the image signal that is actually input, and the frequency of the sample clock signal SCLK often changes in accordance with these specifications. In such a case, the number m of delay elements DLB (1) to DLB (m−1) is set so as to be able to cope with the case where the period Tc is the longest. Then, the latches input to the input terminal B of the first AND gate 448 and the input terminal A of the second AND gate 450 of the phase comparison determination unit 446 from among the latch signals LD (1) to LD (m−1). A selector for selecting one signal is provided. Then, the latch signal is selected so that the delay amount of the delayed clock signal input to the latch that outputs the selected latch signal is smaller than the cycle Tc of the sample clock signal SCLK. In this way, various image signals can be handled.
[0075]
In the above embodiment, each time the latch signals LD (0) to Ld (m−1) are output from the phase comparison unit 440, the phase change control unit 460 detects the phase change and generates the delayed absorption data DCD. The case of outputting is described as an example. However, when a sudden phase change is detected, this change is often a single change due to noise. Therefore, a plurality of times of phase detection data may be stored, and the delay absorption data DCD may be controlled in accordance with changes in these phase detection data. For example, the average value of the phase detection data for a plurality of times may be used as the phase detection data, and the difference between the average phase detection data and the initial phase data may be obtained in step S110. Alternatively, when the next phase change is predicted from the phase change of the phase detection data for a plurality of times and the phase detection data is within a predetermined allowable range with respect to the prediction result, the phase detection data and the initial phase data The difference may be obtained.
[0076]
In the above embodiment, the phase change control unit 460 controls the delay absorption data DCD so as to absorb the difference between the initial phase data and the phase detection data. Instead of this, for example, the delay absorption data DCD may be controlled so as to absorb the difference between the phase detection data and the immediately preceding phase detection data. In this case, the initial phase setting unit 320 in FIG. 3 is not necessary.
[0077]
B. Second embodiment:
FIG. 9 is a block diagram showing a signal change detection unit 420A in the image display apparatus as the second embodiment. The image display apparatus of the second embodiment is the same as the image display apparatus 1000 of FIG. 1 except that a signal change detection unit 420A is used instead of the signal change detection unit 420 of the phase change absorption unit 330 shown in FIG. It is.
[0078]
The signal change detection unit 420A includes a plurality of comparators CMP (0) to CMP (l-1) (l is an integer of 2 or more), a plurality of comparison level generation units CMV (0) to CMV (l-1), An OR gate 426 having a positive logic input, an OR gate 428 having a negative logic input, a selector 430, and a flip-flop 432 are provided. The plurality of comparison level generation units CMV (0) to CMV (l−1) have different comparison levels Vr according to the level control data RVD (0) to RVD (l−1) output from the phase change control unit 460, respectively. (0) to Vr (l-1) are output. Each of the comparators CMP (0) to CMP (l-1) compares the comparison levels Vr (0) to Vr (l-1) inputted thereto with the analog image signal GSA, and the signal level of the analog image signal GSA. Outputs detection signals VES0 to VES1-1 that change from the L level to the H level at the timing when becomes higher than the respective comparison levels Vr (0) to Vr (l-1). Alternatively, the detection signals VES0 to VES1-1 that change from the H level to the L level are output at a timing when the signal level of the analog image signal GSA becomes smaller than the respective comparison levels Vr (0) to Vr (l-1).
[0079]
Each of the detection signals VES0 to VES1-1 is input to the OR gate 426. When any one of the detection signals changes from the L level to the H level, the output signal VES (U) that changes from the L level to the H level. Is output. Each of the detection signals VES0 to VES1-1 is also input to the OR gate 428. When any one of the detection signals changes from the H level to the L level, the output signal changes from the L level to the H level. VES (D) Is output. The selector 430 is controlled by the switching signal U / D, and detects the timing at which the signal level of the analog image signal GSA becomes higher than the respective comparison levels Vr (0) to Vr (l−1). An output signal VES (U) of the OR gate 426 is output. When the timing at which the signal level of the analog image signal GSA becomes lower than the comparison levels Vr (0) to Vr (l−1) is detected, the output signal VES (D) of the OR gate 428 is output. The output signal (VES (U) or VES (D)) of the selector 430 is input to the clock input terminal CK of the flip-flop 432, and the data input terminal D is set to the H level. The output Q of the flip-flop 432 changes to H level at the rising timing of the output signal VES (U) or VES (D) and is output as the detection signal VES. When the output Q of the flip-flop 432 changes to the H level, it maintains the H level until it is reset by the reset signal RSTS output from the phase change control unit 460.
[0080]
With the above operation, the signal change detection unit 420A detects the timing at which the comparison level Vr (0) to Vr (l-1) becomes larger or smaller than any one of the comparison levels Vr (0) to Vr (l-1). Can be output as the detection signal VES.
[0081]
Here, there are various kinds of image signals such as a white image having a high luminance level and a black image having a low luminance level. In the signal change detection unit 420 of the first embodiment, it is impossible to detect a change in luminance level from an image signal having a luminance level lower than the comparison level Vr. However, in the signal change detection unit 420A of the second embodiment, the change in the analog image signal can be detected at a plurality of comparison levels Vr (0) to Vr (l-1). A change in luminance level can be detected.
[0082]
In the signal change detection unit 420 shown in FIG. 5 as well, changes in the luminance level can be detected in various image signals by changing the comparison level Vr. For example, the comparison level Vr may be changed according to the content of the input image, or the comparison level Vr may be changed at an appropriate time interval.
[0083]
C. Third embodiment:
FIG. 10 is a block diagram showing the configuration of the sample clock generator 120A in the image display apparatus as the third embodiment. The image display apparatus of the third embodiment is the same as the image display apparatus 1000 of FIG. 1 except for the configuration of the sample clock generator 120A and the supply destination of the sample clock signal output from the sample clock generator 120A.
[0084]
The sample clock generation unit 120A includes a red sample clock generation unit 120AR, a green sample clock generation unit 120AG, and a blue sample clock generation unit 120AB. The sample clock generation units 120AR, 120AG, and 120AB of the respective colors are provided. The configuration is the same as that of the sample clock generator 120 of the first embodiment. The synchronization signal HS and the corresponding analog image signals RSA, GSA, BSA are input to the delay adjustment unit 170 of each color sample clock generation unit 120AR, 120AG, 120AB, and the delay synchronization signals HSCR, HSCG, HSCB are received. Is output. The clock generator 180 of each color sample clock generator 120AR, 120AG, 120AB generates sample clock signals RSCLK, GSCLK, BSCLK synchronized with the delay synchronization signals HSCR, HSCG, HSCB inputted thereto. The sample clock signals RSCLK, GSCLK, and BSCLK are input to the corresponding color AD converters 130R, 130G, and 130B and the image conversion unit 140.
[0085]
The sample clock signals RSCLK, GSCLK, and BSCLK output from the sample clock generation units 120AR, 120AG, and 120AB for each color are generated so that the phase change with respect to the analog image signals RSA, GSA, and BSA for the corresponding colors is absorbed. As a result, in the image display apparatus according to the second embodiment, stable processing can be performed in the AD converters 130R, 130G, and 130B and the image conversion unit 140 corresponding to the respective colors. Further, stable image processing can be performed by absorbing the phase change occurring between the three analog image signals.
[0086]
D. Fourth embodiment:
FIG. 11 is a block diagram showing a configuration of the sample clock generation unit 120B in the image display apparatus as the fourth embodiment. The image display apparatus according to the fourth embodiment is the same as the image display apparatus 1000 of FIG. 1 except for the configuration of the sample clock generation unit 120B.
[0087]
Similar to the sample clock generation unit 120, the sample clock generation unit 120B includes a delay adjustment unit 170 and a clock generation unit 180, except for the following points. The clock generation unit 180 receives not the delayed synchronization signal HSC but the synchronization signal HS, and the clock generation unit 180 outputs the reference clock signal PCLK. The delay adjustment unit 170 outputs the sample clock signal SCLK by delaying the reference clock signal PCLK.
[0088]
Also in the image display device of the fourth embodiment, the operation can be performed so as to absorb the phase change of the sample clock signal SCLK in accordance with the green analog image signal GSA, so that the generated phase change of the sample clock signal SCLK is absorbed. Thus, stable image processing can be performed.
[0089]
As in the third embodiment, a sample clock 120B may be provided for each color image signal. In this case, any two of the clock generation units 180 included in each color may be omitted, and one clock generation unit 180 may be used in common.
[0090]
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.
[0091]
(1) In the above embodiment, the case where an analog image signal is input as an image signal is described as an example. However, the present invention can also be applied to a case where a digital image signal is input.
[0092]
(2) In the above embodiment, an example in which the image processing apparatus of the present invention is applied to an image display apparatus using a liquid crystal panel has been described. However, the present invention is not limited to this. The present invention can also be applied to a display device using another flat panel such as a plasma display. The present invention can be applied to various electronic devices that process image signals such as scan converters and video captures.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an image display apparatus to which an image processing apparatus as a first embodiment is applied.
FIG. 2 is a time chart showing a horizontal synchronization signal HS, a delay synchronization signal HSC, and a sample clock signal SCLK.
3 is a block diagram showing an internal configuration of a delay adjustment unit 170. FIG.
4 is a block diagram illustrating an example of an internal configuration of a variable delay unit 300. FIG.
5 is a block diagram showing a schematic configuration of a phase change absorber 330. FIG.
FIG. 6 is a timing chart showing the operation of the comparator 422;
7 is a timing chart showing the operation of the phase change absorber 330. FIG.
8 is a flowchart showing an operation of a phase change control unit 460. FIG.
FIG. 9 is a block diagram showing a configuration of a signal change detection unit 420A in the image display apparatus as the second embodiment.
FIG. 10 is a block diagram illustrating a configuration of a sample clock generation unit 120A in an image processing apparatus as a third embodiment.
FIG. 11 is a block diagram illustrating a configuration of a sample clock generation unit 120B in an image processing apparatus as a fourth embodiment.
FIG. 12 is an explanatory diagram showing an input image signal and a sample clock signal.
[Explanation of symbols]
1000: Image display device
100: Image processing unit
110: Input buffer section
120: Sample clock generator
120A ... Sample clock generator
120AR ... red sample clock generator
120AG ... Green sample clock generator
120AB ... Blue sample clock generator
120B ... Sample clock generator
130: AD converter
130R ... Red AD converter
130G ... Green AD converter
130B ... Blue AD converter
140: Image conversion unit
150: Display clock generator
160 ... CPU
162 ... Bus
170: Delay adjustment unit
180: Clock generation unit
200: Image display section
210 ... Liquid crystal panel
220 ... Panel drive unit
300: Variable delay unit
302: Delay unit
DLA (1) to DLA (n-1) ... delay element
304 ... Selector
310: Data addition unit
320: Initial phase setting unit
330... Phase change absorber
420: Signal change detection unit
420A: Signal change detection unit
422 ... Comparator
424 ... Comparison level generation unit
426, 428 ... OR gate
430 ... selector
432 ... flip-flop
440 ... Phase comparison unit
442 ... Delay unit
DLB (1) to DLB (m-1) ... delay element
444 ... Latch part
LT (0) to LT (m-1) ... latch
446 ... Phase comparison / determination unit
448, 450 ... AND gate
452 ... Switch
460 ... Phase change control unit

Claims (5)

An image processing apparatus,
A sample clock generator for generating a sample clock signal used to process the input image signal;
A processing unit that processes the input image signal using the sample clock signal ,
The sample clock generator is
A delay adjusting unit that generates a delay synchronization signal by adjusting a delay amount of the synchronization signal synchronized with the input image signal;
A clock generator that generates the sample clock signal based on the delay synchronization signal,
The delay adjustment unit
A variable delay unit that delays the predetermined synchronization signal by a variable delay amount and outputs the delayed synchronization signal;
A phase change absorber that controls a delay amount of the variable delay unit so as to absorb a change in phase difference between the input image signal and the sample clock signal;
The phase change absorber is
A signal change detection unit that outputs a binary output signal whose signal level changes when the image signal change position is detected;
A phase comparator that detects a phase difference between the edge position of the binary output signal and the edge position of the sample clock signal;
The phase comparison unit latches the binary output signal from the signal change detection unit at a plurality of timings within a period of one cycle of the sample clock signal, and the latched multi-bit signal is converted into the image Output as a phase difference signal indicating the phase difference between the signal change position and the edge position of the clock signal,
The sample clock generation unit detects the phase difference between an image signal change position, which is a position where the input image signal reaches a specific signal level, and an edge position of the sample clock signal. Detecting the phase change of the sample clock signal and adjusting the phase of the sample clock signal to absorb the phase change, thereby processing the phase of the sample clock signal with respect to the input image signal Adjust to a phase suitable for
Image processing device. An image processing apparatus,
A sample clock generator for generating a sample clock signal used to process the input image signal;
A processing unit that processes the input image signal using the sample clock signal ,
The sample clock generator is
A clock generator for generating a reference clock signal for generating the sample clock signal based on a synchronization signal synchronized with the input image signal;
A delay adjustment unit that outputs the sample clock signal by adjusting a delay amount of the reference clock signal;
The delay adjustment unit
A variable delay unit that delays the reference clock signal by a variable delay amount and outputs the sample clock signal;
A phase change absorber that controls a delay amount of the variable delay unit so as to absorb a change in phase difference between the input image signal and the sample clock signal;
The phase change absorber is
A signal change detection unit that outputs a binary output signal whose signal level changes when the image signal change position is detected;
A phase comparator that detects a phase difference between the edge position of the binary output signal and the edge position of the sample clock signal;
The phase comparison unit latches the binary output signal from the signal change detection unit at a plurality of timings within a period of one cycle of the sample clock signal, and the latched multi-bit signal is converted into the image Output as a phase difference signal indicating the phase difference between the signal change position and the edge position of the clock signal,
The sample clock generation unit detects the phase difference between an image signal change position, which is a position where the input image signal reaches a specific signal level, and an edge position of the sample clock signal. Detecting the phase change of the sample clock signal and adjusting the phase of the sample clock signal to absorb the phase change, thereby processing the phase of the sample clock signal with respect to the input image signal Adjust to a phase suitable for
Image processing device. The image processing apparatus according to claim 1 or 2 ,
The phase change absorption unit controls a delay amount of the variable delay unit so that a phase of the sample clock signal with respect to the input image signal is maintained at a phase in a predetermined appropriate phase state;
Image processing device. An image processing apparatus according to any one of claims 1 to 3 ,
The sample clock generation unit is provided for each of a plurality of color signals included in the input image signal, and a sample clock signal is generated for each of the color signals.
Image processing device. An image display device,
An image processing apparatus according to any one of claims 1 to 4 ,
An image display unit that displays an image represented by an image signal output from the image processing device,
Image display device.

Images