JP2001188503A - Image display device, device for detecting number of horizontal effective pixels and picture display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically adjust the frequency of dot clocks, without requiring image signals for adjustment and also to make a device operate at a low cost by suppressing the operating speed of a circuit which adjusts the frequency of the dot clocks. SOLUTION: This picture display device is provided with an input dot clock reproducing circuit 30 reproducing input dot clocks, based on the input horizontal synchronizing signal of input image signals, an A/D conversion means 20 converting the input image signals into digital signals according to the input dot clocks, an image display part driving means 40 which converts the digital signals into display signals suitable for a display by an image display unit 50 and also generates driving timing signals for the display, a means for detecting the number of horizontal effective pixels 60 detecting the number of horizontal effective pixels of the display signals and an input dot clock control means 70 controlling the frequency of the input dot clocks, so that the number of the horizontal effective pixels becomes a desired value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display technique, and more particularly to an optimum dot for converting an analog video signal from a video signal output device such as a personal computer into a digital video signal and outputting the digital video signal to a dot matrix type image display device. The present invention relates to a method for generating or reproducing a clock, and particularly to a method suitable for use in a multi-scan type liquid crystal display, a liquid crystal projector, a plasma display, or the like to which a video signal having an unspecified standard is input.

[0002]

2. Description of the Related Art In recent years, so-called multi-scan type image display devices, such as computer devices, which can display image signals having various frequencies (resolutions) have become mainstream. Therefore, in order to realize a multi-scan type in a dot matrix type image display device represented by a liquid crystal display, a plasma display, or the like, an analog image signal is sampled with a dot clock corresponding to a dot cycle of the image signal, and the memory is sampled. So-called image interpolation processing such as enlargement or reduction of an image to match the resolution of the image display unit. Here, if sampling is performed at a dot clock different from the frequency of the input image signal, the number of horizontal effective pixels after sampling will be different from the number of horizontal effective pixels of the image display unit to be displayed. For example, if sampling is performed at a dot clock frequency higher than the frequency of the input image signal, the number of horizontal effective pixels increases, and conversely, if sampling is performed at a dot clock frequency lower than the frequency of the input image signal, the number of horizontal effective pixels decreases. I do.
In addition, phenomena such as moiré are caused to cause remarkable deterioration of image quality. However, since there are few image signal sources that output the dot clock, the dot clock is generated or reproduced by multiplying the horizontal synchronization signal inside the image display device. Therefore, in order to display an input image signal without image quality deterioration, it is necessary to provide an accurate dot clock generation (or reproduction) means.

In a conventional image display device, the resolution of a connected image signal is determined by using a horizontal synchronization signal and a vertical synchronization signal of an input image signal, and a result is referred to a table prepared in advance. This method employs a method of determining a multiple for dot clock generation or reproduction. However, depending on the image signal source to be connected, the table may have a slightly different dot clock from the prepared table. In such a case, the dot clock is manually adjusted by the user while checking the displayed image visually. The frequency is being adjusted.

[0004] An image display device in which such manual adjustment is automated is disclosed in Japanese Patent Application Laid-Open No. 10-078771. FIG. 7 shows a configuration of a dot clock generation device in the image display device. 5, reference numeral 5 denotes a sampling circuit for sampling a video signal from the video output device 2, 7 denotes a clock generation circuit for generating a sampling clock, 6 denotes a clock phase variable circuit, 4 denotes an image holding memory for clock reproduction, and 8 denotes a clock. A phase control circuit 9 for controlling a frequency of a sampling clock generated by the clock generation circuit 7;
Denotes a video output control device, and these constitute a dot clock generation device 1. The image display device 13 includes the dot clock generation device 1 and an image display circuit 14, and displays a video signal digitally converted using a sampling clock via the image display device 14.

In this configuration, the video output device 2 outputs a video signal including a sampling clock generation image having a predetermined number of dots. Then, the clock frequency control circuit 9 counts the output period of the image for generating the sampling clock in the video signal with a clock having an appropriate period higher than the dot clock frequency of the video signal, thereby obtaining [n dot period The number of clock pulses in one dot period is detected as the number of clock pulses in [1] / [the number of n dots] = [the number of clock pulses in one dot period], and the number of clock pulses in one horizontal scanning period is counted. The total number of dots in one horizontal scanning period is calculated as [number of clock pulses in horizontal scanning period] / [number of clock pulses in one dot period] = [total number of dots in one horizontal scanning period]. Set the sampling clock frequency to the desired dot clock frequency by setting the Automatically adjust.

[0006]

However, in the conventional image display device in which the dot clock frequency is adjusted by the manual adjusting means as described above, the dot clock frequency of the image signal source and the reproduction (or generation) by the image display device are performed. If the dot clock frequency is slightly different, the user must manually adjust while visually checking the displayed image, which not only complicates the work but also
There is a problem that it is difficult to adjust accurately.

Further, in the image display device described in Japanese Patent Application Laid-Open No. 10-078771, although the adjustment is automated, it is necessary to output an image signal for adjustment to an image signal source. Further, a detection clock having a frequency higher than the dot clock frequency of the input image signal is required to detect the total number of dots in one horizontal scanning period. There is a problem that the configuration of the frequency control circuit must cope with a very high frequency, which increases the cost.

The present invention has been made in view of the above points, and an image display apparatus capable of automatically adjusting a dot clock frequency without requiring a specific adjustment image signal.
And an image display method. It is another object of the present invention to provide an image display device having a configuration in which the operation speed of a circuit for adjusting a clock frequency is suppressed and the cost can be easily reduced.

[0009]

According to a first aspect of the present invention, there is provided an image display apparatus for displaying an image on a dot matrix type image display unit based on an image signal having an arbitrary standard. A display device, comprising: input dot clock generation means for generating an input dot clock based on an input horizontal synchronization signal of the input image signal; and AD conversion means for converting the input image signal into a digital signal according to the input dot clock. Image display unit driving means for converting the digital signal into a display signal suitable for display by the image display unit and generating a drive timing signal for the display; and displaying the display based on the display signal and the drive timing signal. Horizontal effective pixel number detecting means for detecting the number of horizontal effective pixels of the signal; Characterized by comprising an input dot clock control means for controlling the frequency of said input dot clock to a value.

A second image display device according to the first image display device, wherein the image display section driving means includes an image memory for temporarily storing the digital signal, and a display horizontal synchronization signal as the drive timing signal. , A display vertical synchronizing signal and a display dot clock are generated.

A third image display device is the first or second image display device, wherein the image display section driving means is arranged so that the number of horizontal and vertical images of the digital signal is the number of horizontal and vertical images of the image display unit. The conversion into the display signal is performed so as to coincide with the above.

In a fourth image display device, in any one of the first to third image display devices, the input dot clock generation means compares the phase of the input horizontal synchronization signal with the phase of an internal feedback signal to determine an error. Phase comparing means for outputting a signal, filter means for smoothing the output of the phase comparing means, voltage controlled oscillating means whose oscillation frequency is controlled by the potential smoothed by the filter means, and voltage controlled oscillating means And 1 / N frequency dividing means for dividing the oscillation signal of 1 / N by 1 / N to obtain the internal feedback signal.

A fifth image display device is the image display device according to any one of the first to fourth image display devices, wherein the input dot clock control means controls the frequency division number N of the 1 / N frequency division means. It is characterized in that the desired number of horizontal effective pixels is obtained.

A sixth image display device is the image display device according to any one of the first to fifth image display devices, wherein the horizontal effective pixel number detecting means determines the horizontal start position of the display signal in each display horizontal scanning period. And the horizontal end position of the display signal as the number of display dot clocks until a valid display image signal is no longer detected in each display horizontal scanning period. It is characterized by detecting.

A seventh image display device is characterized in that in any one of the first to sixth image display devices, the input dot clock control means has a CPU.

Further, the horizontal effective pixel detecting device according to the present invention comprises:
Dot clock counting means for starting counting the number of dot clocks of the image signal in synchronization with the horizontal synchronization signal of the input image signal; and level detection means for determining the presence of a valid image signal in the image signal. Horizontal image start position latching means for latching the smallest one of the dot clock counts until the effective image signal is detected during each horizontal scanning period of the image signal; and In the horizontal scanning period,
Horizontal image end position latch means for latching the largest one of the count numbers of the dot clocks until the valid image signal is no longer detected.

According to a first image display method of the present invention, an input image signal is sampled by the input dot clock, converted into a display signal suitable for display on an image display unit, and a display dot clock is used. In the image display method for displaying on the image display unit, the horizontal start position and the end position of a valid signal in the converted display signal are determined until a valid display signal is detected and is not detected in each display horizontal scanning period. , And the frequency of the input dot clock is controlled so that the number of horizontal effective pixels obtained based on the detection result becomes a desired value.

According to a second image display method, in the first image display method, an input dot clock for generating a dot clock by converting an input horizontal synchronizing signal of the input image signal into a signal corresponding to a frequency division setting value. The input dot clock is generated by generating the input dot clock, and adding the difference between the number of horizontal effective pixels obtained based on the detection result and the desired number of horizontal effective pixels to the division setting value, thereby obtaining the frequency of the input dot clock. Is performed.

In a third image display method, in the first image display method, an input horizontal synchronizing signal of the input image signal is converted into a signal corresponding to a frequency division setting value to generate a dot clock. The input dot clock is generated by generating the input dot clock by a dot clock generating means, and multiplying the frequency division setting value by a ratio of the number of horizontal effective pixels obtained based on the detection result to a desired number of horizontal effective pixels. The frequency is controlled.

In these configurations of the present invention, the number of horizontal effective pixels is detected based on a display signal suitable for display on the image display unit, and the input dot clock is adjusted so that the number of horizontal effective pixels becomes a desired value. , The input dot clock is adjusted without the need for manual adjustment and image signal for adjustment as in the related art. Further, since the detection of the number of horizontal effective pixels is performed by the display dot clock used for the display of the image display unit, it is not necessary to use a circuit corresponding to a very high frequency as in the related art.

[0021]

FIG. 1 is a block diagram showing the configuration of an image display apparatus according to one embodiment of the present invention. As shown in FIG. 1, this image display device has analog image input signals Ra, Ga,
An AD converter 20 for converting Ba into digital image signals Rd, Gd, Bd, and an input dot clock reproducing circuit 3 for reproducing an input dot clock DCK for the AD conversion
0, an image display unit 50, and a drive timing pulse for converting the digitally converted image signals Rd, Gd, Bd into signals R, G, B suitable for the image display unit 50 and for driving the image display unit 50 Display unit driving circuit 40 that generates
, The display image signals R, G, B, the display horizontal synchronization signal H, the display vertical synchronization signal V, and the display dot clock C
A display pixel number detection circuit 60 for detecting the number of horizontal effective display pixels from the horizontal start and end positions of the display image based on K
And an input dot clock reproduction control circuit 70, which automatically controls the frequency of the input dot clock reproduction circuit 30 based on the effective display pixel number information detected by the display pixel number detection circuit 60 to automatically perform dot generation. This makes it possible to adjust the clock.

The clock frequency of the image signal output from the image display unit driving circuit 40 is
, And as a result, a constant frequency corresponding to the resolution of the image display unit 50 can be obtained regardless of the frequency of the input image signal. Therefore, by arranging the display pixel number detection circuit 60 after the image display unit driving circuit 40, even if the resolution of the input image signal is higher than the resolution of the image display unit 50 and the frequency is high, the display pixel The operation speed of the number detection circuit 60 can be suppressed within the driving range of the image display unit 50. Further, in the case where an IC is considered, it is possible to easily realize integration with the image display unit drive circuit 40.

The input dot clock recovery circuit 30 is shown in FIG.
As shown in the figure, a phase comparison circuit 31 for comparing the phases of the input horizontal synchronization signal Hsync and the internal feedback signal.
A filter circuit 32 for smoothing the output of the phase comparison circuit 31, a voltage controlled oscillation circuit 33 whose oscillation frequency is controlled by the potential smoothed by the filter circuit 32, and an oscillation signal of the voltage controlled oscillation circuit 33 / N is divided and used as an internal feedback signal to the phase comparison circuit 31.
And a frequency dividing circuit 34.

The phase comparator 31 receives the input horizontal synchronizing signal H
Sync and the input dot clock DCK reproduced by the voltage controlled oscillation circuit 33 are compared with the signal obtained by dividing the frequency of the input dot clock DCK by the 1 / N frequency dividing circuit 34 by 1 / N, and an error signal corresponding to the phase error is output. . This error signal is used as the control voltage of the voltage controlled oscillation circuit 33 through the filter circuit 32. The voltage controlled oscillation circuit 33 reproduces the input dot clock DCK so that the error from the phase comparison circuit 31 is eliminated. At this time, the input dot clock DCK is the input horizontal synchronization signal Hs
It oscillates at a frequency having the number of clocks N during the period of sync. Therefore, by adjusting the frequency division number N of the 1 / N frequency dividing circuit 34, it becomes possible to reproduce the input dot clock DCK having a desired frequency.

The image display section drive circuit 40 shown in FIG. 1 includes an image memory. The digitally converted image signals Rd, Gd, and Bd are temporarily stored in the image memory according to an input dot clock DCK. A so-called interpolation process is performed so that the number of pixels read out by a clock having a frequency different from that of the input dot clock DCK is equal to the number of display pixels of the image display unit 50. Here, the resolution of the input image signal is the input horizontal synchronization signal Hsy.
nc and the frequency of the input vertical synchronization signal Vsync, or the number of input horizontal synchronization signals Hsync within the period of the input vertical synchronization signal Vsync, and the like. For example, if it is determined that the number of display pixels of the image display unit 50 is 1024 × 768 and the number of pixels of the input image signal is 800 × 600, the image display unit driving circuit 40 performs interpolation processing of the input image signal to 1. Multiply by 28 to match the number of display pixels 1024 × 768 of the image display unit 50. That is, the image signal output from the image display unit driving circuit 40 always has the number of pixels (1024 × 768 in the above example) regardless of the number of pixels of the analog input image signals Ra, Ga, and Ba. ) Is matched. The image display section drive circuit 40 further drives the image display unit 50 with drive timing pulses (display horizontal synchronization pulse H, display vertical synchronization pulse V, display dot clock CK).
The image is displayed by inputting the image signal processed by the image display unit driving circuit 40 to the image display unit 50 in accordance with these timing pulses.

The display pixel number detection circuit 60 includes display image signals R, G, B,
The display horizontal synchronization signal H, the display vertical synchronization signal V, and the display dot clock CK are input. Display pixel number detection circuit 60
Has a counter that counts the display dot clock CK in synchronization with the display horizontal synchronization signal H in the horizontal direction,
As shown in FIG. 3, the number of display dot clocks CK when the display image signals R, G and B are first input is HFC, and the number of display dot clocks CK when the display image signal no longer exists last is HRC. To detect. As a result, the number of display pixels is obtained as HRC-HFC. If the reproduced dot clock frequency matches the frequency of the input image signal, it matches the number of horizontal pixels of the image display unit 50. Therefore, by arranging the display pixel number detection circuit 60 at the subsequent stage of the image display unit drive circuit 40, it is sufficient to always determine whether or not the number of pixels coincides with the number of horizontal pixels of the image display unit. It is possible to detect whether or not the dot clock frequency matches the frequency of the input image signal.

By the way, only the effective image period of the input image signal is stored in the image memory included in the image display section driving circuit 40 as a normal configuration. Therefore, when the reproduced effective dot clock frequency is higher than the frequency of the input image signal and the apparent effective image period becomes long, the display pixel number detection circuit 60 cannot accurately detect the period. Assuming such a case, the timing of taking in the image memory is delayed in advance to detect the head position HFC of the image, and the timing of taking in the image memory is advanced to detect the end position HRC of the image. In consideration of the above, it is possible to detect the exact number of display pixels. That is, assuming that the shift amount is OFS, the image head position is HFC
= HFC'-OFS, image end position is HRC = HRC '
+ OFS, and therefore the number of display pixels is HRC−HF
C = HRC′−HFC ′ + 2OFS. Although not particularly specified in the following description, the image head position is HFC = H
FC'-OFS, image end position is HRC = HRC '+ O
It shall be detected as FS.

FIG. 4 shows the detailed configuration of the display pixel number detection circuit 60, and its operation will be described. The display horizontal synchronizing signal H is shaped into a pulse having a width of one clock by the one-clock pulsing circuit 112, and the display image signal latch 100 and the display dot clock counter 102 are cleared. The display vertical synchronizing signal V is converted into a pulse having a width of one clock by the one-clock pulsing circuit 113, and “High” is set in the latches 106 and 108 and the latch 10 is turned on.
Clear 9 and 111. After being cleared in synchronization with the display horizontal synchronization signal H, the display dot clock counter 102 counts the number of display dot clocks CK. The display image signals R, G, and B are temporarily latched by the latch 100 and then compared with the fixed value TH by the comparison circuit 101 to determine the presence or absence of an image. Here, the fixed value TH is set to a value slightly larger than the black level of the image.

When there is a valid image in the image signals R, G, and B, the output of the comparison circuit 101 becomes "High" and the one-clock pulsing circuit 103 shapes the pulse into a pulse having a width of one clock, and enables the latch 106. Signal. The latch 106 latches the count number HCNT of the display dot clock counter 102 in the enabled state. The count number latched by the latch 106 is compared with the value latched by the latch 108 by the comparison circuit 107. If the value of the latch 106 is small, an enable signal is output to the latch 108, and the count number is latched by the latch 108. Is done. By performing this operation for each horizontal line, the minimum count number is detected, and this value becomes the head position HFC where the image exists.

When there is no valid image in the image signals R, G, and B, the output of the comparison circuit 101 becomes "Low" and is inverted by the inverter 104 and converted into a pulse having a width of one clock by the one-clock pulsing circuit 105. It is shaped and becomes an enable signal of the latch 109. The latch 109 stores the display dot clock counter 10 in the enabled state.
The count number HCNT of 2 is latched. Comparison circuit 110
Indicates the count number latched by the latch 109 to the latch 11
If the value of the latch 109 is larger than the value latched to 1, an enable signal is output to the latch 111. Thereby, the count number is latched by the latch 111. By performing this operation for each horizontal line, the maximum count number is detected, and this value becomes the final position HRC where the image exists. Since the display pixel number detection circuit 60 does not need to be constantly operating, DCST is provided as an enable control signal for the entire circuit.

The position information HFC and HRC detected by the display pixel number detection circuit 60 are input to the input dot clock reproduction control circuit 70. As a result, the input dot clock reproduction control circuit 70 corrects the frequency division number of the 1 / N frequency dividing circuit 34 included in the input dot clock reproduction circuit 30 based on the adjustment flow described later in detail, and converts a desired input dot clock. obtain.

In this embodiment, the display pixel number detection circuit 6
Although the image signals to be input to 0 are three systems of R, G and B, one of R, G and B may be simply used instead.

FIG. 5 shows a flow of adjusting the dot clock DCK in the image display device. As shown in the figure, when the adjustment is started, first, in step S1, the display pixel number detection circuit 60 detects the image start position HFC and the end position HRC in the horizontal direction. Next, in step S2, the number of horizontal effective display pixels DCV = HRC-H
Calculate FC. Next, in step S3, the number of horizontal pixels DT of the image display unit 50 is compared with the number of horizontal effective display pixels DCV in the display image signal. If they are not equal, the process proceeds to step S4. In step S4, an error between the horizontal pixel number DT of the image display unit 50 and the effective display pixel number DCV constitutes the input dot clock reproduction circuit 30.
The frequency dividing number FBD of the / N frequency dividing circuit 34 is corrected. In this correction, it is necessary to consider the scaling factor SCALE of the resolution conversion to be processed or processed by the image display unit driving circuit 40, and FBD = FBD + (DT-DCV) / SCAL
E. Steps S1 to S4 are repeated until the frequency division number FBD of the 1 / N frequency dividing circuit 34 is corrected and the number of horizontal pixels DT of the image display unit 50 becomes equal to the number of effective display pixels DCV. If it is determined in step S3 that the number of horizontal pixels DT of the image display unit is equal to the number of effective display pixels DCV, the adjustment flow ends.

For example, if the resolution of the input image signal is SVGA
(800 × 600), when the number of horizontal pixels DT of the image display unit is 1024, the conversion magnification SCALE = 1.28
Becomes Assuming that the frequency division number FBD at this time is 1056 and the effective display pixel number DCV is 1040, step S3
, DT−DCV = −16, so step S
Proceed to 4. In step S4, FBD = 1056--16
/1.28=1043.5, so round to the nearest
Assuming that BD = 1044, the process returns to step S1. Then, the number of effective display pixels is detected again in steps S1 and S2, and if DCV = 1028, DT-DCV = -4 in step S3.
The program proceeds to FBD = 1044-4 / 1.28 ≒ 1041 and returns to step S1. Further, the number of effective display pixels is detected again in steps S1 and S2, and if DCV = 1025, DT−DCV = −1 in step S3, so the process proceeds to step S4, and FBD = 1041-1 /
1.28 ≒ 1040, and the process returns to step S1. Further, the number of effective display pixels is detected again in steps S1 and S2, and if DCV = 1024, DT-DCV = 0 in step S3, and the flow exits the flow and the adjustment ends.

FIG. 6 shows an adjustment flow of the dot clock DCK in the image display device according to another embodiment of the present invention. When the adjustment is started, first, in step S21, the image start position HFC in the horizontal direction is detected by the display pixel number detection circuit 60.
And the end position HRC are detected. Next, in step S22, the number of horizontal effective display pixels DCV = HRC
Calculate HFC. Next, in step S23, the ratio DT / DCV of the number of horizontal pixels DT of the image display unit 50 and the number of horizontal effective display pixels DCV is calculated. If the ratio is not equal to 1, the process proceeds to step S24. Step S2
In No. 4, the dividing number FBD of the 1 / N dividing circuit 34 constituting the input dot clock reproducing circuit 30 is expressed by FBD using the ratio DT / DCV of the horizontal pixel number DT of the image display unit 50 and the effective display pixel number DCV. = FBD x (DT / DCV). Steps S21 to S24 are repeated until the frequency division number FBD of the 1 / N frequency dividing circuit 34 is corrected and the number of horizontal pixels DT of the image display unit 50 is equal to the number of effective display pixels DCV. In step S23,
When it is determined that the horizontal pixel number DT of the image display unit 50 is equal to the effective display pixel number DCV, the adjustment flow ends.

For example, if the resolution of the input image signal is SVGA
(800 × 600), the horizontal pixel number DT of the image display unit is 1024, and the frequency division number FBD at this time is 105.
6. Assuming that the effective display pixel number DCV is 1040, DT / DCV ≠ 1 in step S23, and the process proceeds to step S24. In step S24, FB
D = 1056 x (1024/1040) = 1039.8
Therefore, the rounding is performed to set FBD = 1040, and the process returns to step S21. If the number of effective display pixels is detected again in steps S21 and S22 and DCV = 1024, DT / DCV = 1 in step S23, so the flow exits the flow and the adjustment ends.

[0037]

As described above, according to the present invention,
Since the number of horizontal effective pixels of the display image signal is detected, it is possible to determine whether the input dot clock frequency is optimal. If the input dot clock frequency is not optimal, the desired number of horizontal effective pixels is obtained by correcting the frequency division ratio of the input dot clock reproduction circuit with an error between the detected number of horizontal effective pixels and the number of pixels of the display unit. The optimal adjustment of the input dot clock frequency as obtained can be realized.

Further, by disposing the horizontal effective pixel number detecting means at the subsequent stage of the image display section driving means, it is possible to make the operating speed of the horizontal effective pixel number detecting means constant irrespective of the input dot clock frequency. Further, the cost can be reduced by forming an IC including the image display unit driving means.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an input dot clock recovery circuit in the device of FIG.

FIG. 3 is a timing chart showing an example of an image position with respect to a horizontal synchronization signal.

FIG. 4 is a block diagram showing a detailed configuration of a display pixel number detection circuit in the device of FIG. 1;

FIG. 5 is a flowchart showing an input dot clock adjustment operation in the apparatus of FIG. 1;

FIG. 6 is another flowchart showing an input dot clock adjustment operation in the apparatus of FIG. 1;

FIG. 7 is a block diagram showing a conventional example of an image display device.

[Explanation of symbols]

20: AD converter, 30: input dot clock reproduction circuit, 31: phase comparison circuit, 32: filter circuit, 33:
Voltage controlled oscillator circuit, 34: 1 / N frequency divider circuit, 40: image display unit drive circuit, 50: image display unit, 60: display pixel number detection circuit, 70: input clock reproduction control circuit, 1
00: display image signal latch, 101, 107, 110:
Comparison circuit, 102: display dot clock counter, 10
3, 105, 112, 113: 1 clock pulsing circuit, 104: inverter, 106, 108, 109, 1
11: Latch.

Claims (11)

[Claims] 1. An image display device for displaying an image on a dot matrix type image display unit based on an image signal having an arbitrary standard, wherein an input dot clock is set based on an input horizontal synchronization signal of the input image signal. Input dot clock generating means for generating, and an A for converting the input image signal into a digital signal in accordance with the input dot clock
D conversion means, image display section driving means for converting the digital signal into a display signal suitable for display by the image display unit and generating a drive timing signal for the display, Horizontal effective pixel number detecting means for detecting the horizontal effective pixel number of the display signal based on the input signal, and input dot clock control means for controlling the frequency of the input dot clock so that the horizontal effective pixel number becomes a desired value. An image display device comprising: 2. The image display section driving means includes an image memory for temporarily storing the digital signal,
2. The image display device according to claim 1, wherein a display horizontal synchronization signal, a display vertical synchronization signal, and a display dot clock are generated as the drive timing signal. 3. The image display section driving means converts the digital signal into the display signal so that the number of horizontal and vertical pixels of the digital signal matches the number of horizontal and vertical pixels of the image display unit. 3. The method according to claim 1, wherein
An image display device according to claim 1. 4. The input dot clock generating means compares a phase of the input horizontal synchronization signal with an internal feedback signal to output an error signal, and a filter for smoothing an output of the phase comparing means. Means, a voltage-controlled oscillating means whose oscillation frequency is controlled by the potential smoothed by the filter means, and 1 / N dividing the oscillation signal of the voltage-controlled oscillating means by 1 / N to obtain the internal feedback signal. The image display device according to claim 1, further comprising a frequency dividing unit. 5. The input dot clock control means for obtaining the desired number of horizontal effective pixels by controlling a frequency dividing number N of the 1 / N frequency dividing means. The image display device according to any one of claims 1 to 4. 6. The horizontal effective pixel number detecting means detects a horizontal start position of the display signal as a display dot clock number until a valid display image signal is detected in each display horizontal scanning period. 6. The method according to claim 1, wherein the horizontal end position of the display signal is detected as the number of display dot clocks until a valid display image signal is not detected in each display horizontal scanning period.
The image display device according to any one of the above. 7. The input dot clock control means according to claim 1, wherein
7. The semiconductor device according to claim 1, wherein the first member has a U.
Item 10. The image display device according to Item 1. 8. A dot clock counting means for starting counting the number of dot clocks of an image signal in synchronization with a horizontal synchronization signal of an input image signal, and for judging existence of a valid image signal in the image signal. Level detection means, in each horizontal scanning period of the image signal, horizontal image start position latch means for latching the smallest one of the count numbers of the dot clock until the effective image signal is detected, Horizontal image end position latching means for latching the largest dot clock count number until the effective image signal is no longer detected in each horizontal scanning period of the image signal. Horizontal effective pixel number detection device. 9. An image display method for sampling an input image signal with an input dot clock, converting the input image signal into a display signal suitable for display on an image display unit, and displaying the display signal on the image display unit using the display dot clock. The horizontal start position and end position of a valid signal in the converted display signal are detected as the number of display dot clocks until a valid display signal is detected and not detected in each display horizontal scanning period, respectively.
An image display method, wherein the frequency of the input dot clock is controlled so that the number of horizontal effective pixels obtained based on the detection result becomes a desired value. 10. An input dot clock generating means for generating a dot clock by converting an input horizontal synchronizing signal of the input image signal into a signal corresponding to a frequency division set value, wherein the input dot clock is generated. 10. The frequency of the input dot clock is controlled by adding a difference between the number of horizontal effective pixels obtained based on the above and a desired number of horizontal effective pixels to the frequency division setting value. Image display method. 11. An input dot clock generating means for generating a dot clock by converting an input horizontal synchronizing signal of the input image signal into a signal corresponding to a frequency division setting value, and generating the input dot clock, 10. The frequency of the input dot clock is controlled by multiplying the division setting value by a ratio between the number of horizontal effective pixels obtained based on the above and the desired number of horizontal effective pixels. Image display method.