JPH11219157A - Sampling clock control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically generate a sampling clock having a period equal to the frequency of an input adjustment pattern signal, and optimally control a clock phase, regarding a device for showing a video signal. SOLUTION: Adjustment pattern signals having an adjustment pattern for a two-picture element period, are sampled through an A/D converter 1 and the number of pulses having maximum and minimum values is counted, regarding signals thinned out via a thinning-out means 2. Also, a dividing ratio is changed and roughly adjusted with a size error detection means 3. Then, a size and a phase are fine adjusted with a maximum and minimum value detection and hold means 4 for detecting and holding the maximum and minimum values of thinned-out signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock control device, and more particularly to a means for reproducing a sampling clock corresponding to the number of pixels of an input video signal.

[0002]

2. Description of the Related Art The frequency of a conventional dot clock signal,
In a device that automatically adjusts the phase, especially when the input signal is configured based on pixels and has discrete information, as shown in JP-A-5-66752, a dot clock signal For the (sampling clock signal), the dot clock signal is reproduced by detecting the horizontal scanning cycle from the horizontal synchronizing signal and determining the frequency division ratio of the PLL circuit from the ratio between the two.

[0003] With respect to a conventional dot clock reproducing circuit,
This will be described with reference to FIG. In FIG. 11, an edge detector 11 detects edge information relating to a change point of a signal from a video signal, and a frequency measuring circuit 12 measures a frequency from the edge information. For example, a configuration is generally employed in which a reference pulse is used to count the intervals between transition points included in the edge information. As for the horizontal synchronization signal, the frequency of the synchronization signal is measured by the frequency measurement circuit 13, and the ratio of the frequencies measured by the measurement circuits 12 and 13, that is, the multiplier, is calculated by the calculation unit 14. , The dot clock signal corresponding to the number of pixels of the input signal is automatically generated.

[0004]

However, in the above conventional configuration, when the edge of the input video signal is detected, the frequency is measured using the reference pulse, and the period is measured, the change point of the edge detection output is determined. If the method of counting the intervals is adopted, the frequency of the reference pulse needs to be higher than the highest frequency included in the input video signal, and the frequency measurement unit needs to operate at the highest frequency. If the maximum frequency of the reference pulse becomes higher, there is a problem that the frequency of the reference pulse must be increased accordingly.

[0005]

In order to solve the above-mentioned problems, a sampling clock control device according to the present invention divides an input video signal having an adjustment pattern of a two-pixel cycle from a VCO output locked to a horizontal synchronizing signal. Means for performing A / D conversion with the sampling clock obtained by the above, a delay circuit for changing the phase of the sampling clock with respect to the horizontal synchronization signal, and thinning means for thinning out the A / D converted video signal of the adjustment pattern section; Size error detection means for counting the number of maximum value pulses and minimum value pulses within a predetermined period of the thinning signal, and maximum value and minimum value detection holding means for detecting the maximum value and the minimum value of the thinning signal. Coarsely adjusting the frequency division ratio of the VCO output so that the counter value of the number of maximum value pulses and minimum value pulses of the thinning signal becomes a predetermined number; Finely adjust the frequency division ratio of the VCO so that the level difference between the maximum value and the minimum value of the thinning signal from the thinning circuit becomes zero, and then change the phase of the sampling clock by the delay circuit. Then, the level difference between the maximum value and the minimum value held in the maximum value / minimum value holding circuit is maximized.

According to the present invention, it is possible to optimize a video signal start position with respect to a horizontal synchronizing signal and automatically reproduce a sampling clock having the number of pixels of an input video signal and an optimal sampling phase. The operating frequency of the circuit can be reduced to half or less.

[0007]

(Embodiment 1) An embodiment of the invention described in claim 1 of the present invention will be described below with reference to FIGS.

Referring to FIG. 1, an example using a predetermined adjustment pattern signal having a pattern of two pixel periods will be described. That is, as shown in FIG. 2, the input video signal of the A / D converter 1 has four pixels in a no-signal period in one horizontal synchronization signal.
A case will be described in which a video signal portion of a 2-pixel periodic pattern uses an adjustment pattern signal in which the total number of pixels is 16 and the total number of pixels is 20. The output of the A / D converter 1 is supplied to a thinning circuit 2 and a position error detection circuit 5.

Here, the amplitude of the input adjustment pattern signal shown in FIG. 2 and the maximum and minimum values of the quantized output level of the A / D converter are known, and the initial phase of the sampling clock during the horizontal period is horizontal. It is after the falling edge of the synchronization signal. Then, the input adjustment pattern signal of a two-pixel cycle is inserted in one predetermined horizontal period in the vertical period.

[0010] The thinning circuit 2 thins out the data of the video signal input in units of sampling clocks to reduce the repetition frequency of the data. Further, by changing the position to be decimated in sampling clock units, the phase with respect to one cycle of the video signal waveform (region d in FIG. 2) changes. Next, the decimated data of the video signal whose repetition frequency is reduced with respect to the sampling clock by the decimating circuit 2 is supplied to a size error detecting circuit 3 and a maximum value minimum value detecting and holding circuit 4.

FIG. 3 shows an internal block configuration of the size error detection circuit 3. As shown in FIG. In FIG. 3, during one horizontal synchronization period (FIG.
A maximum value pulse and a minimum value pulse are detected by the maximum value detection circuit 31 and the minimum value detection circuit 32 from the quantized output of the thinning circuit 2 in the region a + b + c). Each of the maximum value pulse and the minimum value pulse is output to the calculation unit 33 as a HIGH pulse signal of a binary signal. The arithmetic unit 33 and the counter 34 add the number of maximum value pulses and the number of minimum value pulses in one horizontal synchronization period represented by a HIGH pulse signal, and add the frequency division ratio α set in the PLL circuit 8 to the horizontal synchronization signal. The difference in the number of pixels in a period corresponding to one cycle is detected.

The video signal (region b in FIG. 2) occupies about 80% of the horizontal synchronization period a + b + c in FIG. 2, and the video signal output from the A / D converter 1 during one horizontal synchronization period. Is also about 80%. Similarly, the output of the thinning circuit 2 in one horizontal synchronization period is about 80% of the video signal in one horizontal synchronization signal. An image having a signal pattern of a video display area b (a video signal having a pattern of a two-pixel cycle such as an area d) in FIG. 2 configured based on the unit information amount (one pixel) as shown in FIG. When the difference between the frequency division ratio α set in the PLL circuit 8 and the number of pixels in a period corresponding to one cycle of the horizontal synchronization signal (region a + b + c in FIG. 2) is large when the signal is used, the sampling initial phase of the horizontal synchronization period is almost Irrespective of the maximum value of the two gradation signals forming the adjustment pattern,
Since the minimum value is included, the frequency division ratio α set in the PLL circuit 8 based on the output signal from the size error detection circuit 3 and one period of the horizontal synchronization signal (region a + b + in FIG. 2)
The difference in the number of pixels in the period corresponding to c) is output.

If the difference between the frequency division ratio α set in the PLL circuit 8 and the number of pixels in a period corresponding to one cycle of the horizontal synchronizing signal (region a + b + c in FIG. 2) is large, coarse adjustment is performed by the size error detection circuit 3. If the frequency division ratio α set in the PLL circuit 8 is larger than the number of pixels in a period corresponding to one cycle of the horizontal synchronizing signal (the area a + b + c in FIG. 2), the value of the frequency division ratio α is changed. Increasing the size error detection circuit 3
Increases, and when the value of the frequency division ratio α decreases, the output of the size error detection circuit 3 decreases. The PLL circuit 8
Is smaller than the number of pixels in a period corresponding to one cycle of the horizontal synchronizing signal (the area a + b + c in FIG. 2), increasing the value of the frequency division ratio α increases the size error detection circuit. The output of the size error detection circuit 3 increases when the value of the frequency division ratio α decreases. Thus, when the count value of the counter 34 of the size error detection circuit 3 becomes 0, the size error becomes 0. In the case where the size error is a two-pixel cycle pattern, the same applies even if the coarse adjustment is performed by setting the size error to be close to one cycle (within 2 or 3) and the fine adjustment is performed by the next maximum / minimum value detection and holding device. An adjustment result is obtained.

The maximum / minimum value detection and holding circuit 4 finely adjusts the phase of the sampling clock and the size error after the output of the size error detection circuit 3 becomes close to zero. The output data of the maximum value minimum value detection and holding circuit 4 is, for each processing pixel,
Compare the current pixel value with the previous maximum value, save the larger value as the maximum value, and compare the current pixel value with the previous minimum value for each processed pixel, The operation of storing the value as the minimum value is performed for a period corresponding to one cycle of the horizontal synchronizing signal (region a + b + c in FIG. 2), and the maximum value and the minimum value of the video signal are detected. The maximum value and the minimum value of the video signal during one period of the horizontal synchronization signal detected by the maximum value minimum value detection holding circuit 4 are supplied to the determination unit 7 via the selector 6.

The position error detection circuit 5 counts the start position of the video signal of the A / D converter 1 with respect to the horizontal synchronizing signal (region δ in FIG. 4) and outputs a signal representing the display start position on a display device (not shown). It has occurred. This is 2
After adjusting the size and phase of the sampling clock using the pixel period pattern, in order to determine an appropriate display start position on a display device such as an LCD, a predetermined δ indicating the appropriate start position is measured and measured. The transfer of the display video signal is started.

FIG. 4 shows a predetermined video signal typified by an output signal from a personal computer or the like used for sampling clock control, a horizontal synchronizing signal, an output of the A / D converter 1 and signals (A, B, C). In the signal A, the display start position of the video signal on the display device starts from the no-signal period, and the right end of the original video is not displayed on the display device. In the signal C, since the display start position of the video signal on the display device starts in the middle of the video signal output from the A / D converter, the left end of the original video is not displayed on the display device. The signal B is a case where the video signal start position of the A / D converter matches the display start position of the display device, and the sampling data of the input video signal is optimally displayed on the display device. That is, δ, which is the head position of the video signal, is counted by a counter (not shown) in the position error detection circuit 5 for a predetermined clock (not shown) to determine an optimum display position.

The selector 6 selects the output from the size error detection circuit 3, the maximum value minimum value detection holding circuit 4, and the output from the position error detection circuit 5, and selectively switches each output.

The judgment section 7 is constituted by a microcomputer or the like,
By using the size error and the difference between the maximum value and the minimum value obtained by the size error detection circuit 3 and the maximum value minimum value detection holding circuit 4 when the frequency division ratio and the phase change amount to the L circuit 8 are respectively changed, P
It is determined whether the frequency division ratio α set in the LL circuit 8 matches the total number of pixels in a period corresponding to one cycle of the horizontal synchronization signal of the input video signal and whether the phase of the sampling clock is optimal. .

The PLL circuit 8 includes a frequency divider 82, a phase comparator 83, an LPF 84, a VCO 85, a delay circuit 81, and the like, and generates a sampling clock having a period based on the frequency division ratio α set by the determination unit 7. And supplied to the A / D converter 1. The sampling clock is delayed by the delay circuit 81 by the amount of phase change set by the determination unit 7 and outputs sampling clocks having different phases. The horizontal synchronization signal 1 of the input video signal is
The change point of the sampling clock when the total number of pixels in the period corresponding to the cycle matches the frequency division ratio is the same position for all the pixels in the video display area b in FIG. In other words, by giving a certain amount of delay, a certain phase is taken with respect to the pixel of the video signal, and by changing the amount of delay, the phase of the sampled video signal pattern changes. The delay circuit 81 can be realized by being installed at the position of the output line 86 of the frequency divider 82 or the input line 87 to the phase comparator 83, or by being built in the frequency divider 82.

Next, the system shown in FIG.
A case will be described in which a video signal having a signal pattern of a video display area b (a video signal having a two-pixel cycle pattern like the area d) shown in FIG.

Next, the operation in the case where the number of sampling clocks is larger than the number of pixels in one horizontal period and the phase of the sampling clock is optimal for size error detection will be described with reference to FIG. FIG. 5A shows a horizontal synchronization signal, an input video signal having a pattern of two pixel periods, and sampling points of a sampling clock, and FIG. 5B shows the A / D converter 1 shown in FIG. 7 shows an output waveform of the A / D converter 1 when a video signal having a pattern of a two-pixel cycle shown in FIG.

In FIG. 5A, the frequency division ratio α is set to 26, and a period corresponding to one cycle of the horizontal synchronizing signal (region a + b + in FIG. 2)
The difference between c) and the number of pixels 20 is set to 6.

FIG. 5 (c) shows the waveform of FIG. 5 (b) sampled and held by the A / D converter 1 by inputting the output of the A / D converter 1 to the thinning circuit 2. 1, 3, 5, and .DELTA.

FIG. 5D shows the maximum value detection circuit 31 of FIG.
5 (c) is a maximum value pulse which is output by comparing with a previously known maximum value in the maximum value detection circuit 31. FIG. 5 (e) shows the maximum value pulse of FIG. The output of the thinning circuit 2 in FIG. 5C is input to the minimum value detection circuit 32, and the minimum value (zero level in this case) after detection of the maximum value pulse is detected by the minimum value detection circuit 32, and the minimum value is output. It shows a value pulse. In the case of FIG. 5, the sum of the number of maximum value pulses and the number of minimum value pulses is 6, and the absolute value Z of the difference between the frequency division ratio α set in the PLL circuit 8 and the number of pixels in one horizontal period is 26− 20 = 6.

FIG. 6 shows a case where the frequency division ratio α is 20, and the initial phase of the sampling clock is different from that of FIG. FIG. 6A shows the sampling points of the input video signal and the sampling clock, and FIG.
4 is an output waveform of the D converter 1. FIG.
Are the outputs of the thinning circuit 2 when thinning is performed in the positions and in the order of the numbers 1, 3, 5,...

FIG. 6D shows the maximum value detection circuit 31 of FIG.
6 (c) shows the input of the output of the decimation circuit 2 and shows the maximum value pulse signal determined to be the maximum value by the maximum value detection circuit 31. FIG. 6 (e) shows the maximum value detection signal of FIG. 6C shows a minimum value pulse signal which is input from the output of the thinning circuit 2 and is determined to be the minimum value by the minimum value detection circuit 31. As described with reference to FIG. 5, the minimum value pulse is output after detecting the minimum value (zero level) after the output of the maximum value pulse, and the added value of the number of the maximum value pulse and the minimum value pulse becomes 4.

Here, in the case of FIGS. 6D and 6E, the output of the size error detection circuit 3 during one cycle of the horizontal synchronizing signal (the area a + b + c in FIG. 2) is set in the PLL circuit 8. The absolute value of the difference between the number of pixels 20 in the period (area a + b + c in FIG. 2) corresponding to the division ratio α = 26 and one cycle of the horizontal synchronizing signal is output as 4 instead. In this case, the size error cannot be detected accurately. However, the frequency division ratio α set in the PLL circuit 8 is changed without changing the phase of the sampling clock during one horizontal synchronization period, and one cycle of the horizontal synchronization signal (FIG. When the difference in the number of pixels in the period corresponding to the second region a + b + c) is changed, the number of pixels in the period corresponding to one period of the horizontal synchronization signal (region a + b + c in FIG. 2) is equal to the frequency division ratio α set in the PLL circuit 8. Therefore, when the value of the frequency division ratio α is reduced, the output of the size error detection circuit 3 is reduced, and the count value of the counter 34 in FIG.

Similarly, when a video signal having a pattern of two pixel periods as shown in FIG. 2 is input to the circuit of FIG. 1, if the number of sampling clocks is smaller than the number of pixels in one horizontal period, the size error detection circuit 3 horizontal sync signal 1
The output during the period (region a + b + c in FIG. 2) is the absolute value of the difference between the frequency division ratio α set in the PLL circuit 8 and the number of pixels 20 in the period corresponding to one period of the horizontal synchronization signal (region a + b + c in FIG. 2). Let Z be a constant value, or if the phase of the sampling clock during one horizontal synchronization period is not optimal for size error detection and the number of sampling clocks is smaller than the number of pixels in one horizontal period, the size error However, the phase of the sampling clock during one horizontal synchronization period is not changed, and the frequency division ratio α set in the PLL circuit 8 is not changed.
When the difference in the number of pixels in a period corresponding to one cycle of the horizontal synchronizing signal (the area a + b + c in FIG. 2) is changed, the frequency division ratio α set in the PLL circuit 8 becomes one cycle of the horizontal synchronizing signal (FIG. Is smaller than the number of pixels in the period corresponding to the region a + b + c), the output of the size error detection circuit 3 decreases as the value of the frequency division ratio α increases, and the count value of the counter 34 in FIG. (Not shown).

Next, according to FIGS. 7 and 8, when the difference between the division ratio α of the PLL circuit 8 and the number of pixels 20 in the period corresponding to one cycle of the horizontal synchronizing signal (region a + b + c in FIG. 2) is small, the difference is changed. The relationship between the sampling phase and the maximum and minimum values detected by the maximum and minimum value detection and holding circuit 4 will be described.

FIG. 7A shows the relationship between a horizontal synchronizing signal, an input video signal having a pattern of two pixel periods, and sampling points, and FIG. 7B shows the output of the A / D converter 1. . The output of the A / D converter 1 is shown in FIG.
At the position of the arrow near the video signal waveform of FIG. FIG.
In (a), the frequency division ratio α is set to 21, and the difference from the number of pixels 20 in a period (region a + b + c in FIG. 2) corresponding to one cycle of the horizontal synchronization signal is set to 1.

FIG. 7 (c) shows the output of the A / D converter 1 input to the thinning circuit 2, and the video signal sampled by the A / D converter 1 as shown in FIG. .. Are thinned out in the positions and in the order of the numbers 1, 3, 5, 7,...

FIG. 7D shows that the frequency division ratio α of the PLL circuit 8 is the same, and the numerals 1, 2, 3, 4 indicated by the arrows of the video signal composed of the periodic pattern of two pixels shown in FIG. The output (waveform of FIG. 8B) of the A / D converter 1 when sampling in the order of.
This is the output of the thinning circuit 2 when the thinning is performed in the positions and in the order of the numbers 2, 4, 6, 8,...

Here, the thinning outputs of FIGS. 7C and 7D are input to the maximum / minimum value detection holding circuit 4, and the difference between the maximum value and the minimum value obtained therefrom is calculated as shown in FIG. , (D) are obtained. In this example, the maximum value X is 3.3V.

Next, FIG. 8A shows a case where the sampling phase is shifted by 0.5 pixel as compared with the case of FIG. 7A.

FIG. 8B shows the output of the A / D converter 1. Sampling was performed at the positions indicated by arrows near the video signal waveform in FIG. 8A in the order indicated by the arrows. It is a waveform. In FIG. 8A, the division ratio α = 21,
A period corresponding to one cycle of the horizontal synchronization signal (region a + b in FIG. 2)
The difference between + c) and the number of pixels 20 is 1.

FIG. 8 (c) shows the output of the A / D converter 1 input to the thinning-out circuit 2, and the A / D converter 1 shows the sampled video signal shown in FIG. .. Are thinned out in the positions and the order of the numerals 1, 3, 5, 7,.... FIG. 8D shows a case where the frequency division ratio α of the PLL circuit 8 is the same and is delayed by one sampling interval from the above sampling position, that is, a video signal having a two-pixel periodic pattern shown in FIG. The output (waveform of FIG. 8B) of the A / D converter 1 when sampling is performed in the order of numbers 1, 2, 3, 4,... Are the outputs of the thinning circuit 2 when thinning is performed in the positions and in the order of the numbers 2, 4, 6, 8,...

8 (c) and 8 (d) are input to the maximum / minimum value detection / holding circuit 4, and the difference between the maximum and minimum values obtained therefrom is shown in FIG. 8 (c). Value Y
(Smaller than 3.3 V) and the value X shown in FIG.
(3.3 V) is obtained.

FIGS. 7 (c) and 7 (d), FIGS. 8 (c) and 8 (d)
Is the output of the A / D converter 1 when the number of sampling clocks is smaller than the number of pixels in one horizontal period.
The division ratio α of the L circuit 8 is the same, and the output of the thinning circuit 2 when the sampling position or the thinning position is changed is input to the maximum / minimum value detection holding circuit 4. Here, the maximum value and the minimum value held by the maximum value / minimum value detection holding circuit 4 are different, and the difference between the maximum value and the minimum value has a certain value other than 0.

Next, according to FIGS. 9 and 10, when the difference between the frequency division ratio α of the PLL circuit 8 and the number of pixels 20 in the period corresponding to one cycle of the horizontal synchronizing signal (region a + b + c in FIG. 2) is 0, ie, the number of sampling clocks Is the same as the number of pixels in one horizontal period, the relationship between the sampling phase and the maximum and minimum values detected by the maximum and minimum value detection and holding circuit 4 will be described.

FIG. 9A shows a video signal in the area a + b + c in FIG. 2, and FIG. 9B shows an arrow in the vicinity of the video signal waveform in FIG. 9A in the A / D converter 1 in FIG. At the position
This is a waveform sampled in the order of the numbers indicated by the arrows. FIG. 9C shows the output of the A / D converter 1 as the output of the thinning circuit 2. The sampled video signal shown in FIG.
.. Are thinned out in the position and order of 3, 5,.
FIG. 9D shows the case where the frequency division ratio α of the PLL circuit 8 is the same and is delayed by one pixel from the sampling position, that is, the arrow of the video signal composed of the periodic pattern of two pixels in FIG. The output of the A / D converter 1 when sampling is performed in the order of the numbers 1, 2, 3, 4,.
9 (a) is input to the thinning-out circuit 2, and the output of the thinning-out circuit 2 which has been thinned out at the positions and in the order of the numbers 2, 4, 6,... is there. FIG.
(C), (d) The output of the thinning circuit 2 is input to the maximum / minimum value detection and holding circuit 4, and the difference between the maximum value and the minimum value obtained therefrom is obtained as shown in FIG. 9 (c). X (3.3 V in the embodiment) and the value 0 V shown in FIG. 9D are obtained.

FIG. 10 shows that the frequency division ratio α and the number of pixels are the same as in FIG. 9, but the sampling clock phase is the same as FIG.
In this case, the difference is 0.5 pixels as shown in FIG. FIG. 10B is a diagram showing that sampling is performed in the order indicated by the arrows at the positions of the arrows near the video signal waveform in FIG. 10A.

FIG. 10 (c) shows the A / D converter 1
Are input to the thinning-out circuit 2 and are sampled and held by the A / D converter 1 and are thinned out at intervals of two pixels. The output of the thinning circuit 2 is obtained by thinning the sampled video signals shown in FIG. 10A in the positions and in the order of the numbers 1, 3, 5,... FIG. 10D shows a case where the frequency division ratio α of the PLL circuit 8 is the same and is delayed by one pixel from the above sampling position.
That is, the output of the A / D converter 1 when sampling is performed in the order of the numbers 1, 2, 3, 4,... Indicated by the arrows of the video signal composed of the periodic pattern of two pixels in FIG. (A) is input to the thinning-out circuit 2 and FIG.
This is the output of the thinning circuit 2 when thinning is performed every two pixels in the positions and in the order of the numbers 2, 4, 6,... Indicated by the arrow 0 (a).

Here, in FIGS. 10C and 10D,
The phase of the sampling clock of the A / D converter 1 is
When changed by the delay circuit 45, the waveform output from the thinning circuit 2 in the video display area b during a period corresponding to one cycle of the horizontal synchronizing signal (area a + b + c in FIG. 2) is the waveform at the changed phase. Will continue to be output. For example, when a signal having a two-pixel cycle as shown in FIG. 10A is input, a constant value is taken during one pixel period. Therefore, the phase of the sampling clock changes with respect to a clock that matches the pixel cycle of the video signal. Thinning circuit 2
10 (c) and (d) are waveforms output from
Becomes 10 (c) and 10 (d), the output of the thinning circuit 2 is input to the maximum / minimum value detection / holding circuit 4, and the difference between the maximum value and the minimum value obtained therefrom is calculated as shown in FIGS. ) Is obtained (smaller than 3.3 V).

FIGS. 9C, 9D, 10C,
FIG. 2D shows the frequency division ratio α set in the PLL circuit 8 and the period corresponding to one cycle of the horizontal synchronization signal (region a + b + in FIG. 2).
c) When the number of pixels 20 is equal, the frequency division ratio α of the PLL circuit 8 is the same, and the output of the thinning circuit 2 when the sampling position or the thinning position is changed is input to the maximum / minimum value detection holding circuit 4. It was done. Here, the maximum value and the minimum value held by the maximum value / minimum value detection holding circuit 4 may be equal in a certain phase (FIG. 9D).

That is, when the maximum value and the minimum value become equal, the division ratio α set in the PLL circuit 8 is determined.
And a period corresponding to one cycle of the horizontal synchronizing signal (region a + in FIG. 2).
b + c) when the number of pixels 20 coincides. At this time, the sampling phase is set to a predetermined phase amount, for example,
When the difference between the maximum value and the minimum value is changed at the interval of 1/16 of the sampling clock and becomes the largest (FIG. 9A), the sampling phase becomes optimal.

Therefore, FIGS. 5C, 5D, and 6
The number of pixels in a period (region a + b + c in FIG. 2) corresponding to one cycle of the horizontal synchronization signal of the input video signal in (c) and (d) is 20
And the difference between the frequency dividing ratio α of the PLL circuit 8 and the determination unit 7, and roughly adjusts the frequency dividing ratio α set in the PLL circuit 8 (when the difference is around 2, 2 near the number of pixels for one cycle). 3), and the number of pixels 20 and the division ratio α of the PLL circuit 8 during a period (region a + b + c in FIG. 2) corresponding to one cycle of the horizontal synchronizing signal.
When the difference is small, the relationship between the maximum value, the minimum value, and the phase held by the maximum value / minimum value detection holding circuit 4 is input to the determination unit 7 and the PLL circuit is calculated from the input value. It is determined whether the frequency division ratio α set to 8 matches and whether the phase of the sampling clock is optimal. In the above description, the A / D converter 1 has P
The sampling clock which is the output of the LL circuit 8 is input and the output of the A / D converter 1 is supplied to the thinning circuit 2. However, the sampling clock of the PLL circuit 8 is frequency-divided to reduce the sampling frequency in advance. A configuration in which a clock is supplied to the A / D converter 1 and the thinning-out circuit 2 at the subsequent stage is omitted can be similarly implemented.

As described above, the video signal, which is an adjustment pattern consisting of a periodic pattern in which the number of pixels for one cycle is two, is sampled, and the frequency division ratio of the PLL circuit and one cycle of the horizontal synchronizing signal of the input video signal are obtained. If the number of pixels of the input waveform matches, the state where the difference between the maximum value and the minimum value is the maximum is determined from the relationship between the phase and the maximum value and the minimum value in the pixel cycle of the adjustment pattern of the input waveform. It can be determined that both are optimal in terms of the phase in the cycle, and a normal graphics video signal is sampled using the sampling clock and displayed on a display device (not shown). Even when the number of pixels in one cycle is two or more, the size and phase can be adjusted by performing the same processing.

For example, from VGA mode to XVGA mode, 640 × 480, 800 × 600, 1024 × 768
Using the respective adjustment patterns corresponding to the graphics mode, etc., the number of sampling clocks corresponding to each input video is 640, 800, and 1024, and the optimum sampling clocks of the sampling phases are generated. Mode images can be displayed.

[0049]

As described above, according to the sampling clock control device of the present invention, it is possible to automatically generate an optimal sampling clock with the number of clocks and the clock pulse phase corresponding to various display graphics modes. Can be

[Brief description of the drawings]

FIG. 1 is an overall block configuration diagram of a sampling clock control device according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing an input adjustment pattern signal and a horizontal synchronization signal of the sampling clock control device according to the embodiment of the present invention.

FIG. 3 is a block diagram of a size error detection circuit of the sampling clock control device according to the embodiment of the present invention.

FIG. 4 is a diagram schematically showing a video signal start position and a display device start position of the sampling clock device according to the embodiment of the present invention.

FIG. 5 is a diagram schematically showing the relationship between the maximum value pulse and the minimum value pulse of the size error detection circuit of the sampling clock control device and the sampling clock in the embodiment of the present invention.

FIG. 6 is a diagram schematically illustrating another relationship between the maximum value pulse and the minimum value pulse of the size error detection circuit of the sampling clock control device according to the embodiment of the present invention and the sampling clock;

FIG. 7 is a waveform chart for schematically explaining the operation of the maximum / minimum value detection holding circuit of the sampling clock control device according to the embodiment of the present invention.

FIG. 8 is another waveform diagram for schematically explaining the operation of the maximum / minimum value detection holding circuit of the sampling clock control device according to the embodiment of the present invention.

FIG. 9 is a diagram schematically illustrating the operation of the maximum value / minimum value detection and holding circuit when the difference between the frequency division ratio of the sampling clock control device and the number of pixels of the input adjustment pattern signal is equal in the embodiment of the present invention. Waveform diagram

FIG. 10 is a diagram schematically illustrating an operation of a maximum value / minimum value detection holding circuit when the difference between the frequency division ratio of the sampling clock control device and the number of pixels of the input adjustment pattern signal is equal in the embodiment of the present invention. Other waveform diagrams

FIG. 11 is a block diagram of a sampling clock control device according to a conventional embodiment.

[Explanation of symbols]

 Reference Signs List 1 A / D converter 2 Thinning circuit 3 Size error detection circuit 4 Maximum value minimum value detection holding circuit 5 Position error detection circuit 6 Selector 7 Judgment unit 8 PLL circuit 31 Maximum value detection circuit 32 Minimum value detection circuit 33 Arithmetic unit 34 Counter 81 Delay circuit 82 frequency divider 83 phase comparator 84 LPF 85 VCO

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/06 H04N 5/06 Z

Claims (1)

[Claims] A means for performing A / D conversion with a sampling clock obtained by dividing an input video signal having an adjustment pattern of a two-pixel cycle from a VCO output locked to the horizontal synchronization signal, and a horizontal synchronization of the sampling clock; A delay circuit for changing the phase of the signal, a thinning means for thinning out the video signal of the A / D-converted adjustment pattern section, and counting the number of maximum value pulses and minimum value pulses within a predetermined period of the thinning signal Size error detection means to perform
A maximum value / minimum value detection holding unit for detecting a maximum value and a minimum value of the thinning signal, wherein the VCO is controlled so that the counter value of the number of maximum value pulses and minimum value pulses of the thinning signal becomes a predetermined number. The frequency division ratio of the output is roughly adjusted, and from that state, the frequency division ratio of the VCO is finely adjusted so that the level difference between the maximum value and the minimum value of the decimation signal from the decimation circuit becomes zero. A sampling clock control device wherein a phase of a sampling clock is changed by the delay circuit to maximize a level difference between a maximum value and a minimum value held in the maximum value / minimum value holding circuit.