JPH0566752A - Dot clock reproduction circuit - Google Patents

Abstract

PURPOSE:To automatize the reproduction of a dot clock in an image display device provided with a sampling circuit system such as a matrix display device, etc. CONSTITUTION:A dot cycle is detected from the primary color signal of a personal computer, etc., by an edge detection circuit 1, and the cycle is measured at a cycle measuring circuit 2. Meanwhile, the period of a horizontal synchronizing signal Hsync is also measured by the period measuring circuit 2, and a ratio of dot clock period to period of the horizontal synchronizing signal i.e., the multiplication of a PLL circuit 5 can be found by an arithmetic circuit 4. Thereby, it is possible to automatically reproduce the dot clock (a) fitted in an input signal by setting such value as the frequency division ratio of the frequency division counter of the PLL circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to various personal computers and EWS.
The present invention relates to a multi-scan display capable of displaying information such as, and more particularly, to clock generation of an image display device having a sampling circuit system such as a matrix display device.

[0002]

2. Description of the Related Art A video signal of a personal computer, an EWS, etc., has a fixed period (hereinafter, dot period) shorter than the horizontal synchronizing signal period.
The signal level has changed, and a clock (hereinafter referred to as a dot clock) that coincides with the dot period is required when displaying on a matrix display device or when writing to a memory for signal processing. However, since few personal computers and the like have a dot clock output terminal, the image display device reproduces the dot clock by multiplying the horizontal synchronizing signal.

As an example of dot clock reproduction, Hitachi Color Video Printer V described in TV Technology September '89 issue.
There is Y-200.

This device has a PLL circuit called an auto scan circuit, and the dot clocks of various input video signals are reproduced by this PLL circuit. However,
To reproduce the dot clock, it is necessary to connect a signal source such as a personal computer in advance and display thin vertical lines, and manually adjust the multiple of the PLL circuit so that these thin vertical lines can be seen clearly. It was

[0005]

SUMMARY OF THE INVENTION The present invention automates the adjustment work of a dot clock recovery circuit.

[0006]

To achieve the above object, the present invention detects a dot period from a video signal and a horizontal scanning period from a horizontal synchronizing signal, and obtains a multiple of a PLL circuit from the ratio of the two. The value is set in the frequency division counter of the PLL circuit.

[0007]

By automatically reproducing the dot clock according to the specifications of the input video signal, the user can be relieved from the adjustment work of dot clock reproduction.

[0008]

FIG. 1 shows a first embodiment of the present invention. FIG. 1 includes an edge detection circuit 1, a period measurement circuit 2, a pulse oscillation circuit 3, an arithmetic circuit 4, and a PLL circuit 5. As shown in FIG. 2, the edge detection circuit 1 includes a capacitor 6, a resistor 7, a voltage source 8, a voltage source 9, level comparators 10, 11 and an OR.
It consists of a gate 21. The cycle measuring circuit 2 comprises a counter 12 and a latch 13 as shown in FIG. The PLL circuit 5, as shown in FIG. P. F15,
Frequency division counter 1 having VCO 16 and frequency division ratio setting terminal 18
It is composed of 7.

The operation of FIG. 1 is as follows. The video signal RGB of a personal computer or the like is respectively detected by the edge detection circuit 1-
1, 1-2, and 1-3 are input. The operation waveform of the edge detection circuit is shown in FIG. The video signal input to the edge detection circuit 1 is differentiated by the capacitor 6 and the resistor 7, and the differentiated waveform is input to the level comparators 10 and 11. In order to obtain a differential waveform, a combination of a capacitor and an inductor or a combination of an inductor and a resistor may be used in addition to the capacitor and the resistor. The level comparators 10 and 11 compare the input differential waveform with the voltage source 8 and the voltage source 9. For example, when the differential waveform is larger than 1E, the output of the level comparator 10 is “H”, and when the differential waveform is smaller than 2E, the level is output. The output of the comparator 11 becomes "H". The outputs of the level comparators 10 and 11 are input to the OR gate 21 and the logical sum is output. The output of the OR gate 21 extracts a point at which the video signal level greatly changes, which corresponds to the dot clock cycle Td.

The output of the OR gate 21 is input to the period measuring circuit 2 as a pulse to be measured. In the cycle measuring circuit 2, as shown in FIG. 3, the pulse to be measured becomes the clear pulse of the counter 12 and the clock pulse of the latch 13. on the other hand,
A pulse having a higher frequency than the pulse to be measured is input from the pulse oscillation circuit 3 to the counter 12 as a clock pulse. Therefore, when the pulse to be measured is input, the count value of the counter 12 becomes "0", and the counter 12 counts the pulses of the pulse oscillator 3 until the next pulse to be measured is input. When the next pulse under measurement is input, the count operation is stopped and the count value is set to "0".
At the same time, the latch 13 latches the count value, and is output as the period of the pulse under measurement.

The dot clock cycle is measured by the cycle measuring circuits 2-1, 2-2 and 2-3, and the result is input to the arithmetic circuit 4. Further, the period measuring circuit 2-4 measures the period of the horizontal synchronizing signal, and the result is input to the arithmetic circuit 4. The arithmetic circuit 4 uses, for example, a microcomputer to calculate the ratio between the dot clock cycle and the horizontal synchronizing signal cycle, and outputs the result. The calculation method is, for example, the ratio between the cycle measuring circuits 2-1 and 2-4, and the cycle measuring circuits 2-2 and 2-
4 and the period measuring circuits 2-3 and 2-4 are respectively obtained, and the averages thereof are taken. The output of the arithmetic circuit 4 thus obtained corresponds to the total number of dots in one horizontal scanning period, and the dot clock can be reproduced by setting the multiple of the PLL circuit 5 to the total number of dots. The PLL circuit 5 is shown in FIG.
With such a configuration, the division ratio setting terminal 1 of the division counter 17
By inputting the output of the arithmetic circuit 4, that is, the data of the total number of dots in one horizontal scanning period, to 8, the dot clock reproduced from the VCO 16 can be obtained.

As described above, the dot clock of the input signal can be automatically reproduced by determining the multiple of the PLL circuit 5 from the video signal and the horizontal synchronizing signal.

A second embodiment of the edge detection circuit 1 is shown in FIG.
Shown in. FIG. 6 shows the A / D converter 19, the latch 113, the level comparators 20-1 and 20-2, and the OR gate 12.
1 is an edge detector. FIG. 7 shows operation waveforms. The operation of FIG. 6 will be described below.

The video signal is input to the A / D converter 19 and A / D converted by the clock applied to the terminal 22. The A / D-converted video signal is latched by the latch 113 by the clock applied to the terminal 22 and input to the level comparators 20-1 and 20-2. Further, the video signals before passing through the latch 113 are input to the level comparators 20-1 and 20-2. That is, the level comparators 20-1 and 20-2 compare the levels of signals delayed by one clock. The output of the level comparator 20-1 is set to "H" when the relationship between the inputs A and B is A <B, and the output of the level comparator 20-2 is "H" when B <A. To do so. In this way, the output of the level comparator 20-1 becomes "H" during the period when the video signal is increasing,
The output of the level comparator 20-2 becomes "H" while the amplitude of the video signal is decreasing. By taking the logical sum of the level comparators 20-1 and 20-2 by the OR gate 121, the point where the level of the video signal greatly changes can be extracted and the dot clock cycle Td can be detected.

By using the edge detection circuit of FIG. 6 as the edge detection circuit 1 of FIG. 1, the dot clock of the input video signal can be automatically reproduced as in the first embodiment. In addition, the terminal 22 of the edge detection circuit of FIG.
In order to operate the / D converter 19 and the latch 113, the output of the pulse oscillator 3 may be applied.

A third embodiment of the edge detection circuit 1 is shown in FIG. FIG. 8 shows an edge detection circuit including a sample hold circuit 23, level comparators 110 and 111, and an OR gate 221. FIG. 9 shows the operation waveform. The operation of FIG. 8 will be described below.

The video signal is input to the sample hold circuit 23, sampled and held by the clock pulse applied to the terminal 24, and the level comparators 110 and 1 are connected.
11 is input. In addition, the level comparator 110,
A video signal before being sample-held is input to 111, and the level comparators 110 and 111 compare the video signal levels delayed by one clock, as in the second embodiment. The video signal before being sample-held is input to the-input of the level comparator 110, and +
The video signal after being sampled and held is input to the input so that the output of the level comparator 110 becomes “H” during the period when the video signal level is increasing. On the other hand, the + and-inputs to the level comparator 111 are reversed from those of the level comparator 110, and the level comparator 1 during the period when the video signal level is decreasing.
The output of 11 is set to "H". This level comparator 1
By taking the logical sum of the outputs of 10 and 111 with the OR gate 221, it is possible to extract the point at which the video signal level greatly changes and to detect the dot clock cycle Td.
By providing some hysteresis in the comparison voltage range of the level comparators 110 and 111, malfunction due to noise can be prevented.

By using the circuit of FIG. 8 for the edge detection circuit of FIG. 1, the dot clock can be automatically regenerated as in the first embodiment. The output of the pulse oscillator 3 may be applied to the terminal 24 of FIG. 8 in order to operate the sample hold circuit 23.

A fourth embodiment of the edge detection circuit 1 is shown in FIG.
Shown in. A delay circuit 25 is used instead of the sample hold circuit 23 of the third embodiment. The operation waveform is shown in FIG. Except that the video signal is delayed by the delay circuit 25, it is the same as the third embodiment, and detailed description thereof will be omitted.

FIG. 12 shows an image display system using the present invention.
Shown in. FIG. 12 comprises a dot clock reproducing circuit 26 and an image display device 27. Dot clock recovery circuit 2
6 is composed of a circuit as shown in FIG. 1, for example. The image display device 27 is, for example, a matrix display device such as a liquid crystal display, a CRT display or a video printer. As described in the first embodiment, the dot clock reproducing circuit with auto-preset 26 automatically reproduces the dot clock, and the dot clock is input to the image display device 27 together with the video signal and the synchronizing signals Hsync and Vsync, Display the desired display.

A second embodiment of the present invention is shown in FIG.
FIG. 13 comprises a dot clock recovery circuit 126, an edge detection circuit 101, a correlator 28, a control circuit 30, and a delay circuit 29. The dot clock recovery circuit is composed of, for example, the circuit shown in FIG. Also, the edge detection circuit, for example,
It is composed of the circuit shown in FIG. As shown in FIG. 14, the correlator 28 is composed of an EX-OR gate 31, a resistor 107, and a capacitor 106. As shown in FIG. 15, the delay circuit includes a delay line 32 with a tap, a multiplexer 33, and an output switching terminal 34 of the multiplexer 33. The control circuit 30 includes an A / D converter 119 and a microcomputer 35.

The circuit of FIG. 13 is characterized in that the phase of the reproduced dot clock is brought close to the phase of the dot of the video signal.

The operation of FIG. 13 will be described below. The video signal is input to the edge detection circuit 101, and a pulse having a dot cycle is output based on the operation principle described above, and the output is input to the correlator 28. On the other hand, the video signal is the horizontal synchronization signal H.
It is input to the dot clock recovery circuit together with sync,
This also reproduces the dot clock based on the above-mentioned operation principle, and after receiving a certain delay in the delay circuit 29, the correlator 28
Entered in. Here, the operation of the correlator is shown in FIG.
This will be described with reference to the waveform chart of (b). Edge detection circuit 10
The output of 1 and the output of the delay circuit 29 are input to the EX-OR gate 31 in the correlator 28. 17A shows the case where the delay circuit 29 is, for example, the output 33-a of the tapped delay line 32, and FIG. 17B is the case where it is the output 33-b of the tapped delay line 32. In the case of (a), the output of the edge detection circuit 101 and the output of the delay circuit 29 are different from those of (b), and the period of the output “H” of the EX-OR gate 31 is longer. Therefore, when this output is averaged by the resistor 107 and the capacitor 106, the voltage becomes higher in (a). That is, it means that the dot clock has deviated from the video signal. Further, this average value is A / D converted by the A / D converter 119 of the control circuit 30 and the data is taken into the microcomputer 35 to control the delay amount of the delay circuit. The control method uses, for example, a vertical blanking period, and switches all of the multiplexers 33 during this period to obtain the delay amount that minimizes the output of the correlator,
The multiplexer 33 is set to that value.

As described above, the dots of the video signal have the smallest phase shift. Dot clock can be regenerated.

[0025]

According to the present invention, the dot clock can be automatically reproduced in accordance with the specifications of the input video signal,
The user can be freed from the task of adjusting the dot clock reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention,

FIG. 2 is a circuit diagram of the edge detection circuit of FIG.

FIG. 3 is a configuration diagram of a cycle measuring circuit 2.

FIG. 4 is a block diagram of a PLL circuit,

FIG. 5 is an operation waveform diagram of the edge detection circuit,

FIG. 6 is a block diagram showing a second embodiment of the edge detection circuit,

7 is an operation waveform diagram of FIG.

FIG. 8 is a block diagram showing a third embodiment of the edge detection circuit,

9 is an operation waveform diagram of FIG.

FIG. 10 is a block diagram showing a fourth embodiment of the edge detection circuit,

11 is an operation waveform diagram of FIG.

FIG. 12 is a diagram of an image display system using the present invention,

FIG. 13 is a block diagram showing a second embodiment of the present invention,

FIG. 14 is a circuit diagram of a correlator,

FIG. 15 is an explanatory diagram of a delay circuit,

FIG. 16 is a block diagram of a control circuit,

FIG. 17 is an operation waveform diagram of the correlator.

[Explanation of symbols]

1, 101 ... Edge detection circuit, 2 ... Cycle measurement circuit, 3 ... Pulse oscillation circuit, 4 ... Arithmetic circuit, 5 ... PL
L circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H04N 5/06 Z 9070-5C 5/44 Z 7037-5C

Claims (6)

[Claims] 1. A dot clock reproducing circuit comprising a terminal for applying a horizontal synchronizing signal and a PLL circuit for multiplying the frequency of the horizontal synchronizing signal applied to the terminal by a constant cycle shorter than the cycle of the horizontal synchronizing signal. An edge detection circuit that detects the cycle from at least one primary color signal of red, green, and blue primary color signals whose signal levels change, and a first cycle measurement circuit that measures the cycle from the output of the edge detection circuit. A second period measuring circuit for measuring the period of the horizontal synchronizing signal; a pulse oscillating circuit for supplying clock pulses of the first and second period measuring circuits;
A dot clock recovery circuit comprising a calculation circuit for calculating the measurement result of the second cycle measuring circuit and controlling the PLL circuit. 2. The dot clock recovery circuit according to claim 1, wherein the edge detection circuit includes a delay circuit and a level comparator. 3. The dot clock recovery circuit according to claim 1, wherein the edge detection circuit includes an A / D converter, a latch circuit, and a level comparator. 4. The dot clock recovery circuit according to claim 1, wherein the edge detection circuit includes a sample hold circuit and a level comparator. 5. The image display device according to claim 1, comprising the dot clock reproduction circuit. 6. A dot clock regeneration circuit comprising a terminal for applying a horizontal synchronizing signal and a PLL circuit for multiplying the frequency of the horizontal synchronizing signal applied to the terminal by a signal level at a constant cycle shorter than the horizontal synchronizing signal cycle. An edge detection circuit that detects the cycle from at least one primary color signal of red, green, and blue primary color signals that changes, and a delay circuit that includes a delay amount setting terminal that delays the output signal of the dot clock reproduction circuit. A dot comprising: a correlator that outputs a correlation value between the output of the edge detection circuit and the output of the delay circuit, and a control circuit that controls the delay amount of the delay circuit based on the output of the correlator. Clock recovery circuit.