JPH11184422A - Synchronizing signal processing circuit and method, display device and record medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform. a synchronizing signal processing whose operation is stabilized with respect to horizontal and vertical synchronizing signals and a composite synchronizing signal having various frequencies and polarities. SOLUTION: This circuit is provided with a polarity discriminating means for horizontal synchronizing signal 1 detecting the polarity of a synchronizing signal after a prescribed time is elapsed from the edge of an input horizontal synchronizing signal, a polarity discriminating means for vertical synchronizing signal 2 detecting the polarity of a synchronizing signal at the time a prescribed time is elapsed from the edge of an input vertical synchronizing signal, polarity inverting means making synchronizing signals having fixed polarities so as to be always obtained based the discriminated results and a spurious vertical synchronizing signal generating means 4 generating a spurious vertical synchronizing signal in the case the vertical synchronizing signal is not inputted to a vertical synchronizing signal input terminal and in this circuit, in the case the vertical synchronizing signal is not inputted, the spurious vertical synchronizing signal generated by the means 4 and the horizontal synchronizing signal are made to be synchronized to be outputted as a vertical synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal processing circuit and method, a display device, and a storage medium, and more particularly to a display monitor for inputting various horizontal synchronization signals, vertical synchronization signals or composite synchronization signals, and synchronization of the display monitor. The present invention relates to a signal processing circuit.

[0002]

2. Description of the Related Art Conventionally, as a synchronous signal processing circuit which determines the polarity of a synchronous signal and switches the polarity of the synchronous signal based on the result of the determination, for example, Japanese Patent Laid-Open No.
No. 8 discloses a synchronous signal processing circuit. The synchronization signal processing circuit stores the voltage value of the horizontal or vertical synchronization signal in the storage circuit at the rising or falling timing of the output pulse signal of the horizontal or vertical oscillation circuit, and sets the polarity of the horizontal or vertical synchronization signal to the positive or negative polarity. A corresponding DC signal is obtained.

[0003]

However, Japanese Patent Application Laid-Open No.
As in the case of the synchronization signal processing circuit disclosed in No. 89088, simply changing the polarity of the synchronization signal and outputting the same does not support the composite synchronization signal shown in "HD-1N" in FIG. It was possible.

In order to respond to the composite synchronizing signal,
As a so-called sync separation circuit for separating a vertical sync signal from a composite sync signal, a C-sync as shown in FIGS.
There is a separation circuit using a frequency characteristic by R.

[0005] However, this can correspond to an apparatus using fixed horizontal and vertical frequencies such as NTSC and PAL, but horizontal and vertical synchronizing signals having various frequencies and polarities and composite synchronizing signals are used. It could not correspond to the multi-scan monitor used. because,
In a multi-scan monitor, it is necessary to support various horizontal and vertical frequencies in order to support various different resolution modes. I couldn't expect it to work.

SUMMARY OF THE INVENTION In view of the foregoing, the present invention has been developed to provide various frequency, polarity horizontal,
It is an object of the present invention to be able to perform synchronous signal processing of a stable operation on a vertical synchronous signal or a composite synchronous signal.

[0007]

A synchronization signal processing circuit according to the present invention comprises a horizontal synchronization signal polarity determining means for detecting the polarity of a horizontal synchronization signal input to a horizontal synchronization signal input terminal, and an input signal to a vertical synchronization signal input terminal. Vertical sync signal polarity determining means for detecting the polarity of the detected vertical sync signal, and whether to invert each sync signal based on the polarity determination results of the horizontal sync signal polarity determining means and the vertical sync signal polarity determining means. And a polarity inversion means for always obtaining a synchronization signal of a constant polarity, and determining whether or not a vertical synchronization signal is input to the vertical synchronization signal input terminal, and determining whether or not a vertical synchronization signal is input to the vertical synchronization signal input terminal. If no synchronizing signal is input, it is regarded that a composite synchronizing signal is input to the horizontal synchronizing signal, and the potential of the effective image area within one horizontal scanning period is maintained for one horizontal scanning period. And a pseudo vertical synchronizing signal generating means for generating a pseudo vertical synchronizing signal, and outputting the pseudo vertical synchronizing signal generated by the pseudo vertical synchronizing signal generating means in synchronization with the horizontal synchronizing signal. It is characterized by doing so.

Another feature of the synchronization signal processing circuit of the present invention is that the horizontal synchronization signal polarity determining means includes:
The polarity of the horizontal synchronization signal is determined by detecting a voltage after a first predetermined time from the rising or falling timing of the horizontal synchronization signal, and the vertical synchronization signal polarity determination unit is configured to detect the rising or falling of the vertical synchronization signal. The polarity of the horizontal synchronizing signal is determined by detecting a voltage after a second predetermined time from the falling timing.

Another feature of the synchronization signal processing circuit of the present invention is that the synchronization signal processing circuit further comprises a horizontal synchronization signal generating means for converting an output from the polarity inversion means into a pulse having a predetermined width. .

Another feature of the synchronization signal processing circuit of the present invention is that the horizontal synchronization signal inputted from the horizontal synchronization signal input terminal or the horizontal synchronization signal after a first predetermined time from the rising timing. And a horizontal sync signal polarity determining means for detecting the polarity of the vertical sync signal input from the vertical sync signal input terminal.
A vertical synchronization signal polarity determining means for detecting the voltage of the vertical synchronization signal after a predetermined time to determine the polarity, and detecting the presence or absence of a voltage change at the vertical synchronization signal input terminal to perform complex synchronization with the horizontal synchronization signal input terminal. Composite synchronizing signal determining means for determining whether or not a signal has been input; and maintaining the polarity of the composite synchronizing signal input to the horizontal synchronizing signal input terminal after the first predetermined time for one horizontal scanning period. Pseudo-vertical synchronizing signal generating means for generating a pseudo vertical synchronizing signal, and a horizontal synchronizing signal switching means for selecting either a signal obtained by inverting the polarity of the horizontal synchronizing signal or a signal not inverting the polarity. Vertical synchronizing signal switching for selecting any one of a signal obtained by inverting the polarity of the vertical synchronizing signal or a pseudo vertical synchronizing signal output from the pseudo vertical synchronizing signal generating means. Means, and a vertical synchronizing signal generating means for synchronizing the output from the vertical synchronizing signal switching means with the output from the horizontal synchronizing signal switching means, and based on the result of the judgment by the horizontal synchronizing signal polarity judging means. Generating the output horizontal synchronization signal by aligning the polarity of the horizontal synchronization signal to one of positive and negative, and based on the determination results by the vertical synchronization signal polarity determination means and the composite synchronization signal determination means, The output vertical synchronization signal is generated by adjusting the polarity of the output vertical synchronization signal to one of positive and negative, and the output vertical synchronization signal is output in synchronization with the output horizontal synchronization signal.

Another feature of the synchronization signal processing circuit of the present invention is that the horizontal synchronization signal after a first predetermined time from the rising or falling timing of the horizontal synchronization signal input to the horizontal synchronization signal input terminal. Horizontal sync signal polarity determining means for detecting the voltage of the signal to determine the polarity of the horizontal sync signal; and a second predetermined time after the rising or falling timing of the vertical sync signal input to the vertical sync signal input terminal. Vertical sync signal polarity determining means for detecting the voltage of the vertical sync signal to determine the polarity of the vertical sync signal, and detecting the presence or absence of a voltage change at the vertical sync signal input terminal to detect a composite sync signal Composite synchronizing signal discriminating means for discriminating whether or not the signal has been inputted as a clock signal; and a composite signal inputted to the horizontal synchronizing signal input terminal after the first predetermined time. Pseudo vertical synchronizing signal generating means for generating a pseudo vertical synchronizing signal by maintaining the polarity of the synchronizing signal for one horizontal scanning period; a signal obtained by inverting the polarity of the horizontal synchronizing signal; Horizontal synchronizing signal switching means for selecting any one of the following; a horizontal synchronizing signal generating means for converting an output from the horizontal synchronizing signal switching means into a pulse having a predetermined width; and a signal obtained by inverting the polarity of the vertical synchronizing signal. Or a vertical synchronizing signal switching means for selecting one of the pseudo vertical synchronizing signals output from the pseudo vertical synchronizing signal generating means, and outputting the output from the vertical synchronizing signal switching means to the horizontal synchronizing signal switching means. And a vertical synchronizing signal generating means for synchronizing with the output from the horizontal synchronizing signal polarity judging means based on the result of the judgment by the horizontal synchronizing signal polarity judging means. After adjusting to either positive or negative, the horizontal synchronizing signal generating means converts the pulse into a predetermined pulse to generate an output horizontal synchronizing signal, and the vertical synchronizing signal polarity judging means and the composite synchronizing signal judging means. Based on the determination result, the polarity of the vertical synchronizing signal is adjusted to one of positive and negative to generate an output vertical synchronizing signal, which is output in synchronization with the output horizontal synchronizing signal.

A feature of the display device of the present invention is that the display device includes the horizontal synchronizing signal polarity discriminating means, the vertical synchronizing signal polarity discriminating means, and the composite synchronizing signal discriminating means. Is characterized in that the resolution mode and the like of the input video signal are discriminated based on the determination result.

A feature of the synchronization signal processing method of the present invention is that a horizontal synchronization signal for detecting a polarity of a synchronization signal after a predetermined time has elapsed from an edge of the horizontal synchronization signal input to the horizontal synchronization signal input terminal. Synchronization signal polarity determination processing, vertical synchronization signal polarity determination processing for detecting the polarity of a synchronization signal after a predetermined time has elapsed from the edge of the vertical synchronization signal input to the vertical synchronization signal input terminal, and the horizontal synchronization signal polarity A polarity inversion process for determining whether or not to invert each synchronization signal based on the polarity determination result in the determination process and the vertical synchronization signal polarity determination process, so as to always obtain a synchronization signal having a constant polarity; It is determined whether or not a vertical synchronization signal is input to the synchronization signal input terminal. If the vertical synchronization signal is not input to the vertical synchronization signal input terminal, the horizontal synchronization signal is determined. A pseudo vertical synchronizing signal generating process for generating a pseudo vertical synchronizing signal by maintaining a potential of an effective image area within one horizontal scanning period for one horizontal scanning period assuming that a composite synchronizing signal is input; A pseudo vertical synchronizing signal generated by a pseudo vertical synchronizing signal generation process is synchronized with the horizontal synchronizing signal and output as a vertical synchronizing signal.

Another feature of the synchronization signal processing method of the present invention is that the horizontal synchronization signal polarity discrimination processing includes the following steps.
The polarity of the horizontal synchronization signal is determined by detecting a voltage after a first predetermined time has elapsed from the rising or falling timing of the horizontal synchronization signal. It is characterized in that the polarity of the horizontal synchronizing signal is determined by detecting a voltage after a second predetermined time has elapsed from the rising or falling timing.

Another feature of the synchronization signal processing method of the present invention is that the synchronization signal processing method includes a horizontal synchronization signal generation process for converting an output from the polarity inversion process into a pulse having a predetermined width. .

Another feature of the synchronization signal processing method of the present invention is that the horizontal synchronization signal input from the horizontal synchronization signal input terminal rises or the horizontal synchronization signal after a first predetermined time from the rising timing. And a horizontal synchronization signal polarity determination process for determining the polarity by detecting the voltage of the vertical synchronization signal and a second synchronization timing based on the rising or falling timing of the vertical synchronization signal input from the vertical synchronization signal input terminal.
A vertical synchronization signal polarity determination process of detecting the voltage of the vertical synchronization signal after a predetermined time to determine the polarity, and detecting the presence or absence of a voltage change at the vertical synchronization signal input terminal to perform complex synchronization with the horizontal synchronization signal input terminal. A composite synchronization signal determination process for determining whether or not a signal has been input, and maintaining the polarity of the composite synchronization signal input to the horizontal synchronization signal input terminal after the first predetermined time for one horizontal scanning period. A pseudo-vertical synchronization signal generating process for generating a pseudo-vertical synchronization signal, a horizontal synchronization signal switching process for selecting either a signal whose polarity is inverted or a signal whose polarity is not inverted, and Vertical synchronization signal switching for selecting one of a signal obtained by inverting the polarity of the vertical synchronization signal and a pseudo vertical synchronization signal output from the pseudo vertical synchronization signal generation processing. Processing, and a vertical synchronization signal generation process for synchronizing the output from the vertical synchronization signal switching process with the output from the horizontal synchronization signal switching process, based on the determination result in the horizontal synchronization signal polarity determination process. An output horizontal synchronization signal in which the polarity of the horizontal synchronization signal is adjusted to one of positive and negative, and based on the determination results in the vertical synchronization signal polarity determination processing and the composite synchronization signal determination processing, the vertical synchronization signal The output vertical synchronizing signal is generated by adjusting the polarity of the signal to one of positive and negative, and is output in synchronization with the output horizontal synchronizing signal.

Another feature of the synchronization signal processing method of the present invention is that the horizontal synchronization signal after a first predetermined time from the rising or falling timing of the horizontal synchronization signal input to the horizontal synchronization signal input terminal. A horizontal synchronization signal polarity determination process of detecting the voltage of the signal to determine the polarity of the horizontal synchronization signal, and a second predetermined time after the rising or falling timing of the vertical synchronization signal input to the vertical synchronization signal input terminal A vertical synchronization signal polarity determination process for detecting the voltage of the vertical synchronization signal to determine the polarity of the vertical synchronization signal, and a composite synchronization signal to the horizontal synchronization signal input terminal by detecting the presence or absence of a voltage change at the vertical synchronization signal input terminal. A composite synchronization signal determining process of determining whether or not the signal has been input as a horizontal synchronization signal input terminal after the first predetermined time. A pseudo vertical synchronizing signal generation process for generating a pseudo vertical synchronizing signal by maintaining the polarity of the synchronizing signal for one horizontal scanning period; and a signal obtained by inverting the polarity of the horizontal synchronizing signal or a horizontal synchronizing signal not inverting the polarity. A horizontal synchronization signal switching process for selecting one of the above, a horizontal synchronization signal generation process for converting an output from the horizontal synchronization signal switching process into a pulse having a predetermined width, and a signal obtained by inverting the polarity of the vertical synchronization signal. Or a vertical synchronizing signal switching process for selecting one of the pseudo vertical synchronizing signals output from the pseudo vertical synchronizing signal generating process, and outputting the horizontal synchronizing signal switching process from the vertical synchronizing signal switching process. And a vertical synchronizing signal generating process for synchronizing with the output from the horizontal synchronizing signal. Is adjusted to one of positive and negative, the horizontal synchronizing signal generation processing converts the signal into a predetermined pulse to generate an output horizontal synchronizing signal, the vertical synchronizing signal polarity discriminating processing, and the composite synchronizing signal discriminating processing. Based on the result of the determination in (1), an output vertical synchronization signal is generated by adjusting the polarity of the vertical synchronization signal to one of positive and negative, and is output in synchronization with the horizontal synchronization signal.

A feature of the storage medium of the present invention is that a program for causing a computer to function as each of the means is stored.

Another feature of the storage medium of the present invention is that the steps constituting the synchronous signal processing method are stored so as to be readable from a computer.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit block diagram for explaining a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a horizontal synchronizing signal polarity judging unit, and 10 to 13 denote horizontal synchronizing signal polarity judging units
10 is a monostate multivibrator (hereinafter referred to as mono-multi), 11 is a resistor, 1
2 is a capacitor and 13 is a D type flip-flop (hereinafter DF / F).

Reference numeral 2 denotes a vertical synchronizing signal polarity discriminating means.
Reference numeral 3 denotes a component constituting the vertical synchronization signal polarity discriminating means 2, reference numeral 20 denotes a mono / multi, 21 denotes a resistor, 22 denotes a capacitor, and 23 denotes a DF / F.

Reference numeral 3 denotes a composite synchronizing signal discriminating means, 30 to 32 denote components constituting the composite synchronizing signal discriminating means 3, 30 denotes a mono / multi, 31 denotes a resistor, and 32 denotes a capacitor.

Reference numeral 4 denotes D as pseudo vertical synchronizing signal generating means.
-F / F, 5 are exclusive OR gates (hereinafter referred to as Ex-OR circuits) as horizontal synchronization signal switching means, 6
Is a vertical synchronization signal switching means, 61 and 62 are Ex-OR circuits constituting the vertical synchronization signal switching means 6, and 7 is a DF / F as a vertical synchronization signal generation means.

Reference numeral 8 denotes a horizontal synchronizing signal generating means, 80 to 82 are components constituting the horizontal synchronizing signal generating means 8, 80 is a mono / multi, 81 is a resistor, 82 is a capacitor, 91 is a horizontal synchronizing signal input terminal, 92 Is a vertical synchronizing signal input terminal, 93
Is a horizontal synchronization signal output terminal, 94 is a vertical synchronization signal output terminal, 95 is a horizontal synchronization signal polarity determination result signal line, 96 is a vertical synchronization signal polarity determination result signal line, 97 is a composite synchronization signal determination result signal line, and 98 is a resistor. It is.

Here, the operation of each block of the circuit of this embodiment will be described. First, the horizontal synchronization signal polarity determination means 1 will be described. The horizontal synchronizing signal or the composite synchronizing signal is input from the horizontal synchronizing signal input terminal 91 to the input “A” of the mono / multi 10 and the input “D” of the DF / F 13, and the “PR” of the DF / F 13 is input. ”, A composite synchronization signal determination result output signal“ Comp * ”from the composite synchronization signal determination unit 3 described later is input. Also, “CLR” and “B” of the mono / multi 10 and “CL” of the DF / F 13
R "is connected to" H ".

The mono / multi 10 is triggered by the falling edge of the horizontal synchronizing signal input to "A",
“H” which is “L” during a period from that point to a “first predetermined time” determined by the time constant of the resistor 11 and the capacitor 12
-Trig "is output from" / Q ". This output is supplied to a pseudo vertical synchronizing signal generating means 4 described later,
Used as a trigger for DF / F13.

Here, the "first predetermined time" is longer than the expected maximum value of the pulse width of the horizontal synchronizing signal, and
The resistance of the resistor 11 is set to be shorter than the minimum value of the horizontal scanning period.
If the time constant of the capacitor 12 and the time constant are set, the polarity of the horizontal synchronization signal within the effective video signal period can be held by the DF / F 13, and "H-" Pol ”can be obtained from“ Q ”of the DF / F13.

For example, as shown in FIG. 2A, when a horizontal synchronizing signal of positive polarity is given, the mono-multi 10 is triggered at the trailing edge of the horizontal synchronizing signal, and the trailing edge of the horizontal synchronizing signal is At the passed “first predetermined time”, the DF / F 13 holds the polarity “L” of the horizontal synchronization signal to obtain a horizontal synchronization signal polarity determination result signal.

On the other hand, as shown in FIG. 2B, when a horizontal sync signal of negative polarity is applied, the mono-multi 10 is triggered at the leading edge of the horizontal sync signal, and the trigger is applied within the effective video signal period. The DF / F 13 holds the polarity "H" of the horizontal synchronization signal at the "first predetermined time" to obtain a horizontal synchronization signal polarity determination result signal. In each case, DF /
“Comp *” input to “PR” of F13 is “H”, and the preset function does not work.

On the other hand, when the composite synchronizing signal is given, “Comp” input to “PR” of the DF / F 13
“*” Is “L”, and the DF / F 13 is fixed to always output “H” as the horizontal synchronization signal polarity determination result signal.

The operation of the horizontal synchronizing signal polarity discriminating means 1 is summarized as follows. If the polarity of the input horizontal synchronizing signal is positive, "L" is output, and if negative, "H" is output. Then, even when the composite synchronization signal is input, "H" is output as the horizontal synchronization signal polarity determination result signal.

Next, the vertical synchronizing signal polarity determining means 2 will be described. Mono / Multi 20 input "A" and DF /
The vertical synchronization signal is input from the vertical synchronization signal input terminal 92 to the input “D” of the F23, and “CL” of the DF / F23 is input.
R ”receives a composite synchronization signal determination result signal“ Comp * ”from a composite synchronization signal determination unit 3 described later.
Mono / Multi 20 “CLR”, “B”, DF / F
Thirteen "PR" is connected to "H".

The mono / multi 20 is triggered by the falling edge of the vertical synchronizing signal input to "A",
“V” which is “L” from the time to “second predetermined time” determined by the time constant of the resistor 21 and the capacitor 22
−Trig ”is output from“ / Q ”and used as a trigger of the DF / F23.

Here, the "second predetermined time" is longer than the expected maximum value of the pulse width of the vertical synchronizing signal and is 1
The resistance 21 is set to be shorter than the minimum value of the vertical scanning period.
If the time constant of the capacitor 22 and the time constant of the capacitor 22 are set, the polarity other than the retrace period of the vertical synchronization signal can be held by the DF / F 23, and "V-pol" as the vertical synchronization signal polarity determination result signal is obtained. Can be obtained from “/ Q” of the DF / F23.

The vertical synchronizing signal polarity discriminating means 2 performs substantially the same operation as the horizontal synchronizing signal polarity discriminating means 1, and outputs "H" when a positive vertical synchronizing signal is inputted, and outputs a negative vertical synchronizing signal. Is input, the DF / F 23 holds "L" to obtain a vertical synchronization signal polarity determination result signal.

When the vertical synchronizing signal is not input,
The composite synchronizing signal discriminating means 3 to be described later discriminates this and outputs “L” as the composite synchronizing signal result signal “Comp *”. Since this is supplied to the “CLR” of the DF / F 23, the DF / F 23 outputs “H” to “V-pol”.

As described above, the operation of the vertical synchronizing signal polarity judging means 2 is summarized as follows: if the polarity of the input vertical synchronizing signal is positive, "H" is output, and if negative, "L" is output. Then, even when the composite synchronization signal is input, "H" is output as the vertical synchronization signal polarity determination result signal.

Next, the composite synchronizing signal determining means 3 will be described. The mono / multi 30 is triggered by the falling edge of the vertical synchronizing signal input to “A”, and a period from that time to a “third predetermined time” determined by the time constant of the resistor 31 and the capacitor 32 , “Q” and “/ Q” output “H” and “L” pulses, respectively.

These pulses are supplied to the horizontal synchronization signal polarity determination means 1 and the vertical synchronization signal polarity determination means 2 as the composite synchronization signal determination result signals "Comp *" and "Comp", and the latter are described later. , Respectively.

Here, the time constants of the resistor 31 and the capacitor 32 are set so that the "third predetermined time" is longer than the expected vertical synchronization cycle, and the mono / multi 30 is made a retriggerable circuit. In other words, as long as the vertical synchronization signal continues to be input periodically, the composite synchronization signal determination result signal “Co
“H” and “L” are continuously output from “mp *” and “Comp”, respectively.

When a composite synchronizing signal is input from the horizontal synchronizing signal input terminal 91, nothing is input to the vertical synchronizing signal input terminal 92.
0 indicates that no trigger is applied, and the composite synchronization signal determination result signals “Comp *” and “Comp” are “L”,
“H” is continuously output.

As described above, the operation of the composite synchronizing signal discriminating means 3 is summarized as follows. When nothing is input to the vertical synchronizing signal input terminal 92, it is regarded that the composite synchronizing signal is input to the horizontal synchronizing signal input terminal 91, and " Comp * ”,“ Comp ”
Output "L" and "H", respectively.

If any pulse is input to the vertical synchronizing signal input terminal 92, it is regarded that the input to the horizontal synchronizing signal input terminal 91 is not a composite synchronizing signal,
From “Comp *” and “Comp” to “H”,
"L" is output as a composite synchronization signal determination result signal.

Next, the pseudo vertical synchronizing signal generating means 4 will be described. DF as pseudo vertical synchronization signal generating means 4
/ F4 is DF in the horizontal synchronization signal polarity discriminating means 1.
Similarly to / F13, the horizontal synchronizing signal or the composite synchronizing signal input from the horizontal synchronizing signal input terminal 91 is held at the "first predetermined time" by the "H-Trig" issued from the mono / multi 10.

D- in the horizontal synchronizing signal polarity discriminating means 1
The difference with the F / F 13 is that the “PR” of the DF / F 13 is supplied with the composite synchronization signal determination result signal “Comp *” issued from the composite synchronization signal determination unit 3, The DF / F4 as the pseudo vertical synchronizing signal generating means is fixed at "H" to disable the preset function. Conversely, the "CLR" of the DF / F 13 is fixed at "H" to disable the preset function, whereas the DF / F 4 provides the composite synchronization signal determination result signal "C".
omp "is supplied.

When a positive or negative horizontal synchronizing signal is input to the pseudo vertical synchronizing signal generating means 4 from the horizontal synchronizing signal input terminal 91, the composite synchronizing signal discrimination result signal "Comp" is output to "CLR". Since “L” is input, “H” is always set to the pseudo vertical synchronization signal “Comp-
V ".

On the other hand, when a composite synchronizing signal is input from the horizontal synchronizing signal input terminal 91, as shown in FIG.
"H" is output in the synchronization pulse portion having a wide pulse width corresponding to the vertical retrace period, and "L" is output as the pseudo vertical synchronization signal "Comp-V" in other portions.

The operation of the pseudo vertical synchronizing signal generating means 4 is summarized as follows. When the horizontal synchronizing signal is input to the horizontal synchronizing signal input terminal 91, "H" is always input, and when the composite synchronizing signal is input. Outputs a pseudo vertical synchronization signal as a pseudo vertical synchronization signal “Comp-V”.

Next, the horizontal synchronizing signal switching means 1 will be described. Ex-OR constituting horizontal synchronization signal switching means
The circuit 5 has a horizontal synchronization signal input terminal 91 as one input terminal.
, And a horizontal synchronization signal polarity determination result signal “H-Pol” from the horizontal synchronization signal polarity determination unit 1 is input to the other input terminal.

When the horizontal sync signal polarity determining means 1 determines that a positive horizontal sync signal has been input to the horizontal sync signal input terminal 91, that is, if "H-Pol" is "L", Ex-OR The circuit 5 outputs the horizontal synchronizing signal input to one input terminal as it is with a positive polarity.

Conversely, when the horizontal sync signal polarity determining means 1 determines that a negative horizontal sync signal has been input, and when a composite sync signal has been input, that is, when “H-Pol” is “H”, If there is, the Ex-OR circuit 5 inverts the horizontal synchronizing signal input to one of the input terminals and outputs the same with a positive polarity. As described above, the operation of the horizontal synchronizing signal switching means 5 can be summarized as follows: a positive horizontal synchronizing signal is always output regardless of the polarity of the input horizontal synchronizing signal.

Next, the vertical synchronizing signal switching means 6 will be described. The Ex-OR circuit 61 has one input terminal to which an input signal from the vertical synchronization signal input terminal 92 is input, and the other input terminal to have the vertical synchronization signal polarity determination result signal from the vertical synchronization signal polarity determination means 2 " V-pol "is input.

When the vertical synchronizing signal polarity judging means 2 judges that the horizontal synchronizing signal of the positive polarity has been inputted to the vertical synchronizing signal input terminal 92, that is, if "H-Pol" is "H", Ex-OR The circuit 61 inverts the vertical synchronizing signal input to one input terminal and outputs "NVD" of negative polarity.

Conversely, when the vertical synchronizing signal polarity discriminating means 2 judges that the negative-polarity vertical synchronizing signal has been input, that is, when “H-Pol” is “L”, the Ex-OR circuit 61 inputs the signal. The output vertical synchronizing signal is output as "NVD" of negative polarity as it is.

When the composite synchronizing signal is inputted and nothing is inputted to the vertical synchronizing signal input terminal 92, the vertical synchronizing signal polarity discrimination result signal "V-pol" from the vertical synchronizing signal polarity discriminating means 2 as described above. Is fixed to “H”,
The vertical synchronizing signal input terminal 92, which is the other input of the Ex-OR circuit 61, is fixed at "L" because it is pulled down by the resistor 98. As a result, the output “NVD” of the Ex-OR circuit 61 outputs “H”.

The Ex-OR circuit 62 has one input terminal to which "NVD" is input and the other input terminal having a pseudo vertical synchronizing signal "Com" from the pseudo vertical synchronizing signal generating means 4.
pV "is input.

When the vertical synchronizing signal is inputted and the composite synchronizing signal judging means 3 judges that it is not a composite synchronizing signal, the pseudo vertical synchronizing signal generating means 4 outputs the pseudo vertical synchronizing signal "Comp-V" as described above. H ”is output, so Ex-O
The R circuit 62 outputs “N” input to the other input terminal.
VD "is inverted to obtain a positive polarity output" Unlock-V ".

On the other hand, when the composite synchronizing signal is input and nothing is input to the vertical synchronizing signal input terminal 92, "NVD" is "H", so that the pseudo vertical synchronizing signal "Comp-V"
Is output as “Unlock-V”.

The operation of the vertical synchronizing signal switching means 6 can be summarized as follows. When the vertical synchronizing signal is input, the vertical synchronizing signal of the positive polarity is always input regardless of the polarity of the input vertical synchronizing signal, and the composite synchronizing signal is input. When the pseudo vertical synchronizing signal “Comp-
V is inverted to “Unlock-V”
Output as

Next, the vertical synchronizing signal generating means 7 will be described. DF / F7 as vertical synchronizing signal generating means 7
The “Unlock-V” output from the vertical synchronizing signal switching means 6 input to “D” by using the output horizontal synchronizing signal “HD @ OUT” generated by the horizontal synchronizing signal generating means 8 described later as a trigger By hitting, an output vertical synchronization signal “VD-OUT” synchronized with the output horizontal synchronization signal “HD @ OUT” is obtained.

Finally, the horizontal synchronizing signal generating means 8 will be described. To the input "B" of the horizontal synchronizing signal generating mono-multi 80, a positive synchronizing signal is always input from the horizontal synchronizing signal switching means 5. At the rising edge of this input signal, that is, at the leading edge of the horizontal synchronizing signal, a trigger is applied, and from that point on, a predetermined positive polarity pulse determined by the time constant of the resistor 11 and the capacitor 12 is output from "Q". .

If the signal input to the horizontal synchronizing signal input terminal 91 is a normal horizontal synchronizing signal, its pulse width is constant. However, when a composite synchronizing signal is given, the vertical synchronizing signal portion is shown in FIG. As shown in FIG. By passing through the horizontal synchronizing signal generating means 8, an output horizontal synchronizing signal "HD-OUT" having a constant pulse width is always obtained and output for a synchronizing signal having any pulse width.

As described above, each part of the circuit shown in FIG. 1 includes a case where a positive horizontal synchronizing signal and a vertical synchronizing signal are input, a case where a negative horizontal synchronizing signal and a vertical synchronizing signal are input, and a case where a composite synchronizing signal is input. The waveforms are shown in FIGS. 5, 6, and 7, respectively.

In the examples of FIGS. 5 and 6, both the horizontal synchronizing signal and the vertical synchronizing signal have a positive polarity or a negative polarity, but similar results can be obtained even when the polarities are different from each other.

In the circuit shown in FIG. 1, the mono-multi for polarity discrimination is triggered at the falling edge for both the horizontal synchronizing signal and the vertical synchronizing signal. It goes without saying that this function can be achieved.

Further, when only the rising edge which is the leading edge of the output horizontal synchronizing signal "HD-OUT" is required at the subsequent stage of this circuit, the horizontal synchronizing signal generating means 8 is unnecessary, and this circuit is omitted. Input and output may be directly connected.

(Modifications of the Present Invention) Hereinafter, some functional blocks will be described as modifications of the present invention. First,
FIG. 8 is a block diagram showing a modification of the horizontal synchronizing signal polarity judging means. 8, reference numeral 91 denotes a horizontal synchronizing signal input terminal similar to that of the first embodiment, 101 denotes a PLL oscillation circuit, 102 denotes a frequency divider, 103 denotes a DF / F, 104 denotes an Ex-OR circuit, and 105 denotes a circuit. A counter circuit, 106 is a sample and hold circuit, 107 is a reference voltage source, 108 is a comparator, 109 is an inverter gate (hereinafter referred to as In gate).
v) and 110 are OR gates (hereinafter referred to as OR circuits).

In FIG. 8, a frequency dividing circuit 102 divides the oscillation output of PLL oscillation circuit 101 to a predetermined value. PLL
The oscillation circuit 101 compares the phase of the divided output with the horizontal synchronization signal input from the horizontal synchronization signal input terminal 91, and generates a clock synchronized with the input horizontal synchronization signal.

This clock is supplied to DF / F103 and Ex
-Used for detecting the edge of the input horizontal synchronization signal by the OR circuit 104 and used for the counting operation of the counter circuit 105.

The counter circuit 105 counts the inputted clock, and the count value is counted by the Ex-OR circuit 10.
4 and reset at the time when the count value reaches a predetermined value.
Emits. The set value of the counter value is set to be larger than a value for counting the expected pulse width of the input horizontal synchronizing signal and smaller than the frequency dividing value of the frequency dividing circuit 102.

FIG. 9 shows a signal waveform at each point in these operations. Now, in FIG. 9, the frequency dividing value of the frequency dividing circuit 102 is set to n + 4. The count value “Count” of the counter 105 is first reset at the leading edge of the input horizontal synchronizing signal, and then reset again at the trailing edge.

Thereafter, the period until the next leading edge comes, that is, n, is continued to be counted. And counter 10
"H-Tr" which becomes "H" only when the count value of 5 is 16
ig ".

The sample and hold circuit 106 maintains and outputs the potential of the input horizontal synchronizing signal at the time when “H-Trig” is input from the counter 105, and the comparator 108 compares this voltage with the potential of the reference voltage source 107. And outputs the result. And OR with Inv109
The circuit 110 outputs the composite synchronization signal determination result signal “Comp
When "*" is "L", that is, when the composite synchronizing signal discriminating means judges that the signal is a composite synchronizing signal, the comparison result is fixed at "H". Output as “H-Pol”.

This modification of the horizontal synchronizing signal polarity discriminating means can be directly replaced with that of the first embodiment. Also, a horizontal synchronizing signal input terminal 91
It is also possible to replace only the portion up to the output “H-Trig” of the counter 105 with the corresponding portion of the first embodiment, and conversely, only the portion after “H-Trig”.

FIG. 10 is a block diagram showing a modification of the vertical synchronizing signal polarity discriminating means. In FIG.
Is the same horizontal synchronization signal input terminal as in the other embodiments, 92
Are vertical synchronization signal input terminals similar to those of the first embodiment,
03 is a DF / F, 204 is an Ex-OR circuit, 205 is a counter circuit, 206 is a sample and hold circuit, 20
7 is a reference voltage source, 208 is a comparator, 209 is In
v and 210 are OR circuits.

The modified example of the vertical synchronization signal polarity discriminating means has only a PLL oscillation circuit system for obtaining a clock, and the other blocks are almost the same as the modified example of the horizontal synchronization signal polarity discriminating means described above. Works.

That is, the horizontal synchronizing signal plays the role of the clock in the modification of the horizontal synchronizing signal polarity discriminating means, and the counter 205 is counted by the horizontal synchronizing signal to obtain "V-Tri
g "is obtained and discrimination is performed while maintaining the polarity of the input vertical synchronization signal at that timing to obtain" V-pol "as a vertical synchronization signal polarity determination result signal. “Comp *” is “L”
At this time, the vertical synchronization signal polarity determination result signal "V-Pol" is fixed at "H".

This modified example of the vertical synchronizing signal polarity judging means can be replaced with that of the first embodiment as it is, and only the portion up to “V-Trig” or “V-Trig” can be used. It is also possible to replace only the part after ".

In both the modified example of the horizontal synchronizing signal polarity judging means and the modified example of the vertical synchronizing signal polarity judging means, the voltages sampled and held by the sample and hold circuits 106 and 206 are compared by comparators 108 and 208 at the next stage. However, the same effect can be obtained even if the comparison result is sampled and held after the comparison is first performed by the comparator.

In each of the last stages, a circuit for receiving the composite synchronization signal determination result signal "Comp *" and fixing the output to "H" is provided.
It is conceivable to fix the polarity discrimination result to “H” by a method such as shifting the outputs of the reference voltage sources 06 and 206 to the high voltage side and switching the potentials of the reference pressure sources 107 and 207 to the low voltage side.

Finally, a modified example of the composite synchronizing signal determining means will be described with reference to FIG. FIG. 11 is a block diagram showing a modified example of the composite synchronization signal determining means. FIG.
In the figures, reference numerals 91 and 92 denote a horizontal synchronizing signal input terminal and a vertical synchronizing signal input terminal similar to those of the other embodiments, 303 denotes a DF / F, 304 denotes an Ex-OR circuit, 305 denotes a counter circuit, and 306 denotes Inv. It is.

The point that the counter circuit 305 counts the input horizontal synchronizing signal and is reset at the edge of the input vertical synchronizing signal is the same as the modification of the vertical synchronizing signal polarity discriminating means shown in the previous embodiment. The description is omitted.

The counter circuit 305 of this embodiment
Is "EN" to stop the counting function separately from the previous example
There is a terminal, and the count operation is performed only when the “EN” terminal input is “L”. Until the count value of the counter circuit 305 reaches a predetermined value, “L” which is the output of the composite synchronization signal determination result signal “Comp” is input to the “EN” terminal, and the counting operation is performed as usual.

When the count value reaches a predetermined value, the composite synchronization signal discrimination result signal "Comp" outputs "H". Since this signal is input to the "EN" terminal, the counting operation is stopped. That is, when counting to a certain value, the counting is stopped by itself, and the composite synchronization signal determination result signal “Comp” keeps outputting “H”. To escape from this state, an edge of the vertical synchronization signal is required.

Here, if the predetermined value at which the automatic counting is stopped is set to a value larger than the number of scanning lines in one vertical scanning period, the counting is not stopped as long as the vertical synchronizing signal is input. .

When the vertical synchronizing signal is not input, after the count value reaches a predetermined value, the composite synchronizing signal determination result signal “Comp” enters a state of continuously outputting “H”. This modified example of the composite synchronizing signal determining means can be directly replaced with that of the first embodiment. The DF / F 303 in this embodiment
And the Ex-OR circuit 304 can also be used in the modified example of the vertical synchronization signal polarity determination means.

Further, in the above-described first embodiment,
Ex-OR circuits have been used for the horizontal synchronizing signal switching means 5 and the vertical synchronizing signal switching means 6, but these can be replaced with switching circuits such as analog switches.

(Other Embodiments of the Present Invention) The present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), and can be applied to an apparatus composed of one device. May be applied.

Further, the functions of the above-described embodiment are implemented in an apparatus connected to the various devices or a computer in a system so that various devices are operated so as to realize the functions of the above-described embodiment. Supplies the software program code for performing the
The invention implemented by operating the various devices according to the program stored in U) is also included in the scope of the present invention.

In this case, the program code of the software implements the functions of the above-described embodiment, and the program code itself and means for supplying the program code to the computer, for example, the program The storage medium storing the code constitutes the present invention. As a storage medium for storing such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-RO
M, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the supplied program code, not only the functions of the above-described embodiment are realized, but also the OS (operating system) or other operating system in which the program code runs on the computer. It goes without saying that such program codes are also included in the embodiment of the present invention when the functions of the above-described embodiment are realized in cooperation with the application software or the like.

Further, after the supplied program code is stored in a memory provided in a function expansion board of a computer or a function expansion unit connected to the computer, the function expansion board or the function expansion unit is specified based on the instruction of the program code. It is needless to say that the present invention also includes a case where a CPU or the like provided for performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0093]

As described above, according to the present invention, the polarity of the horizontal synchronizing signal and the vertical synchronizing signal are determined, and whether or not to invert the polarity of the synchronizing signal is determined based on the result of the determination. , A synchronization signal having a fixed polarity can always be obtained. If the vertical synchronization signal is not input, it is assumed that a composite synchronization signal has been input instead of the horizontal synchronization signal, and a pseudo vertical synchronization signal is generated. Since the signal is output as a synchronization signal, it is possible to satisfactorily cope with a case where a composite synchronization signal is input instead of the horizontal and vertical synchronization signals. As a result, even when horizontal and vertical synchronization signals or composite synchronization signals of various frequencies and polarities in different resolution modes are input, the synchronization signal processing can be stably performed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a first embodiment of a synchronization signal processing circuit.

FIG. 2 is a timing chart for explaining the operation of a horizontal synchronization signal polarity determination unit.

FIG. 3 is a timing chart for explaining the operation of a pseudo vertical synchronization signal generating means.

FIG. 4 is a timing chart for explaining the operation of a horizontal synchronizing signal generator.

FIG. 5 is a timing chart for explaining the operation of each unit when a horizontal / vertical synchronization signal of positive polarity is input.

FIG. 6 is a timing chart for explaining the operation of each unit when a horizontal / vertical synchronization signal of negative polarity is input.

FIG. 7 is a timing chart illustrating the operation of each unit when a composite synchronization signal is input.

FIG. 8 is a circuit block diagram showing a modification of the horizontal synchronization signal polarity discriminating means.

FIG. 9 is a timing chart for explaining an operation of a modification of the horizontal synchronization signal polarity determination means.

FIG. 10 is a circuit block diagram showing a modification of the vertical synchronization signal polarity discriminating means.

FIG. 11 is a circuit block diagram showing a modified example of the composite synchronization signal determining means.

FIG. 12 is a diagram showing an example of a vertical synchronization signal separation circuit as a conventional example.

FIG. 13 is a diagram showing waveforms of respective parts of a vertical synchronization signal separation circuit as a conventional example.

[Explanation of symbols]

 1 horizontal sync signal polarity discriminating means 2 vertical sync signal polarity discriminating means 3 composite sync signal discriminating means 4 pseudo vertical sync signal generating means 5 horizontal sync signal switching means 6 vertical sync signal switching means 7 vertical sync signal generating means 8 horizontal sync signal generation Means 91 Horizontal synchronization signal input terminal 92 Vertical synchronization signal input terminal 93 Horizontal synchronization signal output terminal 94 Vertical synchronization signal output terminal 95 Horizontal synchronization signal polarity determination result signal line 96 Vertical synchronization signal polarity determination result signal line 97 Composite synchronization signal determination result signal line

Claims (14)

[Claims] 1. A horizontal synchronization signal polarity determining means for detecting the polarity of a horizontal synchronization signal input to a horizontal synchronization signal input terminal, and a vertical synchronization signal for detecting the polarity of a vertical synchronization signal input to a vertical synchronization signal input terminal. A polarity discriminating unit, and determining whether or not to invert each of the synchronizing signals based on the polarity discriminating results of the horizontal synchronizing signal polarity discriminating unit and the vertical synchronizing signal polarity discriminating unit, and always obtaining a sync signal of a constant polarity Polarity inverting means to determine whether or not a vertical synchronization signal is input to the vertical synchronization signal input terminal, and when the vertical synchronization signal is not input to the vertical synchronization signal input terminal, the horizontal synchronization signal Pseudo synchronizing signal which generates a pseudo vertical synchronizing signal while maintaining the potential of the effective image area within one horizontal scanning period for one horizontal scanning A synchronizing signal processing circuit, comprising: a signal generating means for synchronizing the pseudo vertical synchronizing signal generated by the pseudo vertical synchronizing signal generating means with the horizontal synchronizing signal. 2. The horizontal synchronization signal polarity determination means detects a voltage after a first predetermined time from a rising or falling timing of the horizontal synchronization signal, determines the polarity of the horizontal synchronization signal, and determines the vertical synchronization signal. The signal polarity determining means is
2. The synchronization signal processing circuit according to claim 1, wherein the polarity of the horizontal synchronization signal is determined by detecting a voltage after a second predetermined time from the rising or falling timing of the vertical synchronization signal. 3. The synchronization signal processing circuit according to claim 1, further comprising a horizontal synchronization signal generation unit that converts an output from the polarity inversion unit into a pulse having a predetermined width. 4. The apparatus according to claim 1, further comprising: a horizontal synchronization signal polarity determination unit, a vertical synchronization signal polarity determination unit, and a composite synchronization signal determination unit, wherein the input is performed based on a determination result of these determination units. A display device for discriminating each mode including a resolution mode of a video signal. 5. A horizontal synchronizing signal polarity judging means for detecting a voltage of a horizontal synchronizing signal inputted from a horizontal synchronizing signal input terminal or a voltage of the horizontal synchronizing signal after a first predetermined time from a rising timing, and judging the polarity. Vertical synchronization signal polarity determination means for detecting the voltage of the vertical synchronization signal after a second predetermined time from the rising or falling timing of the vertical synchronization signal input from the vertical synchronization signal input terminal and determining the polarity, Composite synchronizing signal determining means for detecting the presence or absence of a voltage change at the vertical synchronizing signal input terminal to determine whether or not a composite synchronizing signal has been input to the horizontal synchronizing signal input terminal; and the first predetermined time A pseudo vertical synchronizing signal that generates a pseudo vertical synchronizing signal by maintaining the polarity of the composite synchronizing signal input to the subsequent horizontal synchronizing signal input terminal for one horizontal scanning period. Direct synchronizing signal generating means, horizontal synchronizing signal switching means for selecting either a signal obtained by inverting the polarity of the horizontal synchronizing signal or a signal not inverting the polarity, and a signal obtained by inverting the polarity of the vertical synchronizing signal Or a vertical synchronizing signal switching means for selecting any one of the pseudo vertical synchronizing signals output from the pseudo vertical synchronizing signal generating means, and outputting the output from the vertical synchronizing signal switching means to the horizontal synchronizing signal switching means. Vertical synchronizing signal generating means for synchronizing with the output of the horizontal synchronizing signal switching means for switching the horizontal synchronizing signal switching means on the basis of the result of the judgment by the horizontal synchronizing signal polarity judging means. An output horizontal synchronizing signal is generated in line with one of the two directions. Based on the above, the vertical synchronizing signal switching means is switched to generate an output vertical synchronizing signal by adjusting the polarity of the vertical synchronizing signal to either positive or negative, and synchronizing the output vertical synchronizing signal with the output horizontal synchronizing signal. A synchronizing signal processing circuit characterized by outputting. 6. A horizontal circuit for detecting a polarity of the horizontal synchronization signal by detecting a voltage of the horizontal synchronization signal after a first predetermined time from a rising or falling timing of the horizontal synchronization signal input to the horizontal synchronization signal input terminal. Synchronization signal polarity determining means, detecting the voltage of the vertical synchronization signal after a second predetermined time from the rising or falling timing of the vertical synchronization signal input to the vertical synchronization signal input terminal, and detecting the polarity of the vertical synchronization signal. A vertical synchronizing signal polarity judging unit for judging, and a composite synchronizing signal judging unit for detecting the presence or absence of a voltage change at the vertical synchronizing signal input terminal and judging whether or not the horizontal synchronizing signal input terminal is inputted as a composite synchronizing signal Means for maintaining the polarity of the composite synchronizing signal input to the horizontal synchronizing signal input terminal after the first predetermined time for one horizontal scanning period, Pseudo-vertical synchronization signal generating means for generating a vertical synchronization signal; horizontal synchronization signal switching means for selecting one of a signal obtained by inverting the polarity of the horizontal synchronization signal and a horizontal synchronization signal not inverting the polarity; Horizontal synchronizing signal generating means for converting the output from the synchronizing signal switching means into a pulse of a predetermined width; and a signal obtained by inverting the polarity of the vertical synchronizing signal, or a pseudo signal output from the pseudo vertical synchronizing signal generating means. A vertical synchronization signal switching unit for selecting any one of the vertical synchronization signals; and a vertical synchronization signal generation unit for synchronizing an output from the vertical synchronization signal switching unit with an output from the horizontal synchronization signal switching unit. The horizontal synchronization signal switching means is switched based on the result of determination by the horizontal synchronization signal polarity determination means to change the polarity of the horizontal synchronization signal to either positive or negative. After the alignment, the horizontal synchronizing signal generating means converts the pulse into a predetermined pulse to generate an output horizontal synchronizing signal, and based on the result of judgment by the vertical synchronizing signal polarity judging means and the composite synchronizing signal judging means. And then
The vertical synchronizing signal switching means is switched to generate an output vertical synchronizing signal by adjusting the polarity of the vertical synchronizing signal to one of positive and negative, and to output in synchronization with the output horizontal synchronizing signal. Signal processing circuit. 7. A horizontal synchronizing signal polarity discriminating means according to claim 5 or 6, a vertical synchronizing signal polarity discriminating means, and a composite synchronizing signal discriminating means, based on a discrimination result of these discriminating means. A display device for discriminating each mode including a resolution mode of an input video signal. 8. A horizontal synchronization signal polarity determination process for detecting the polarity of a synchronization signal after a predetermined time has elapsed from an edge of the horizontal synchronization signal input to the horizontal synchronization signal input terminal, and an input to the vertical synchronization signal input terminal. The vertical synchronization signal polarity determination processing for detecting the polarity of the synchronization signal after a predetermined time has elapsed from the edge of the vertical synchronization signal, and the polarity determination results in the horizontal synchronization signal polarity determination processing and the vertical synchronization signal polarity determination processing. A polarity inversion process for determining whether or not to invert each of the synchronization signals, so as to always obtain a synchronization signal having a constant polarity, and whether or not a vertical synchronization signal is input to the vertical synchronization signal input terminal. If no vertical synchronization signal is input to the vertical synchronization signal input terminal, it is considered that a composite synchronization signal is input to the horizontal synchronization signal and one horizontal scan is performed. A pseudo vertical synchronizing signal generating process for generating a pseudo vertical synchronizing signal by maintaining a potential of an effective image area within a scanning period for one horizontal scanning period. A synchronization signal processing method, wherein a pseudo vertical synchronization signal generated by processing and the horizontal synchronization signal are synchronized and output as a vertical synchronization signal. 9. The horizontal synchronization signal polarity determination processing includes detecting a voltage after a first predetermined time has elapsed from a rising or falling timing of the horizontal synchronization signal, and determining a polarity of the horizontal synchronization signal. The vertical synchronizing signal polarity judging process judges a polarity of the horizontal synchronizing signal by detecting a voltage after a second predetermined time has elapsed from a rising or falling timing of the vertical synchronizing signal. Item 9. The synchronization signal processing method according to item 8. 10. The synchronization signal processing method according to claim 8, further comprising performing a horizontal synchronization signal generation process of converting an output from the polarity inversion process into a pulse having a predetermined width. 11. A horizontal synchronization signal polarity determination process for detecting the polarity of a horizontal synchronization signal input from a horizontal synchronization signal input terminal or detecting the voltage of the horizontal synchronization signal after a first predetermined time from the rising timing of the horizontal synchronization signal. Vertical synchronization signal polarity determination processing for detecting the voltage of the vertical synchronization signal after a second predetermined time from the rising or falling timing of the vertical synchronization signal input from the vertical synchronization signal input terminal and determining the polarity; A composite synchronization signal determining process of detecting whether or not a voltage change has occurred at the vertical synchronization signal input terminal to determine whether a composite synchronization signal has been input to the horizontal synchronization signal input terminal; and the first predetermined time A pseudo vertical synchronizing signal is generated by maintaining the polarity of the composite synchronizing signal input to the subsequent horizontal synchronizing signal input terminal for one horizontal scanning period. A vertical synchronization signal generating process; a horizontal synchronization signal switching process of selecting one of a signal whose polarity is inverted or a signal whose polarity is not inverted; and a signal whose polarity of the vertical synchronization signal is inverted. Or a vertical synchronization signal switching process for selecting any one of the pseudo vertical synchronization signals output from the pseudo vertical synchronization signal generation process, and an output from the vertical synchronization signal switching process based on the horizontal synchronization signal switching process. A vertical synchronization signal generating process for synchronizing with the output of (a), wherein the polarity of the horizontal synchronization signal is set to one of positive or negative based on the result of the determination in the horizontal synchronization signal polarity determination process. A horizontal synchronizing signal is generated, and the vertical synchronizing signal is determined based on the results of the vertical synchronizing signal polarity determining process and the composite synchronizing signal determining process. Align the polarity of one positive or negative to produce an output vertical synchronizing signal,
A synchronization signal processing method, wherein the synchronization signal is output in synchronization with the output horizontal synchronization signal. 12. A horizontal circuit for detecting the polarity of a horizontal synchronization signal by detecting a voltage of the horizontal synchronization signal after a first predetermined time from the rising or falling timing of the horizontal synchronization signal input to the horizontal synchronization signal input terminal. Synchronization signal polarity determination processing, detecting the voltage of the vertical synchronization signal after a second predetermined time from the rising or falling timing of the vertical synchronization signal input to the vertical synchronization signal input terminal, and detecting the polarity of the vertical synchronization signal. A vertical synchronization signal polarity determination process for determining, and a composite synchronization signal determination for detecting whether or not a voltage change has occurred at the vertical synchronization signal input terminal and determining whether or not the horizontal synchronization signal input terminal is input as a composite synchronization signal. Processing, and maintaining the polarity of the composite synchronizing signal input to the horizontal synchronizing signal input terminal after the first predetermined time for one horizontal scanning period. A pseudo-vertical synchronization signal generating process for generating a vertical synchronization signal; a horizontal synchronization signal switching process for selecting one of a signal obtained by inverting the polarity of the horizontal synchronization signal and a horizontal synchronization signal not inverting the polarity; A horizontal synchronizing signal generating process for converting an output from the horizontal synchronizing signal switching process into a pulse having a predetermined width; and a signal obtained by inverting the polarity of the vertical synchronizing signal, or a pseudo signal output from the pseudo vertical synchronizing signal generating process. A vertical synchronization signal switching process for selecting any one of the vertical synchronization signals; a vertical synchronization signal generation process for synchronizing an output from the vertical synchronization signal switching process with an output from the horizontal synchronization signal switching process. A synchronization signal processing method, wherein the polarity of the horizontal synchronization signal is either positive or negative based on the determination result in the horizontal synchronization signal polarity determination processing After being turned, the horizontal synchronization signal is converted into a predetermined pulse in the horizontal synchronization signal generation process to generate an output horizontal synchronization signal, and based on the determination results in the vertical synchronization signal polarity determination process and the composite synchronization signal determination process. Generating an output vertical synchronization signal by aligning the polarity of the vertical synchronization signal to either positive or negative;
A synchronization signal processing method, wherein the synchronization signal is output in synchronization with the horizontal synchronization signal. 13. A storage medium storing a program for causing a computer to function as each means according to claim 1. Description: 14. A storage medium, wherein the steps constituting the synchronization signal processing method according to claim 8 are stored so as to be readable from a computer.