JP2988042B2 - Dot clock regeneration circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to various personal computers and EWS
More particularly, the present invention relates to clock generation for an image display device having a sampling circuit system such as a matrix display device.

[0002]

2. Description of the Related Art A video signal from a personal computer, an EWS, or the like has a fixed period shorter than the horizontal synchronizing signal period (hereinafter, dot period)
Therefore, a clock (hereinafter, referred to as a dot clock) that matches the dot cycle is required when displaying on a matrix display device or when performing signal processing by writing to a memory. However, since few PCs have a dot clock output terminal, the image display device reproduces the dot clock by multiplying the horizontal synchronization signal.

As an example of dot clock reproduction, a Hitachi color video printer V described in TV technology September 1989 is described.
There is Y-200.

This device has a PLL circuit called an O-scan circuit, and reproduces dot clocks of various input video signals by the PLL circuit. However,
To reproduce the dot clock, it is necessary to connect a signal source such as a personal computer in advance to display thin vertical lines, and manually adjust the multiple of the PLL circuit so that these thin vertical lines can be clearly seen. Was.

[0005]

The present invention has various specifications.
Corresponding to the input video signal of
Suitable dot clock can be automatically reproduced
It is an object of the present invention to provide a dot clock reproducing circuit .

[0006]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
The dot clock reproduction circuit according to the present invention
The horizontal synchronization signal input with the
A PLL circuit configured to reproduce the
A dot clock reproducing circuit having the video signal
Is used to calculate the period corresponding to the dot period of the video signal.
An edge detection circuit that generates and outputs a pulse signal having
The period of the pulse signal output from the edge detection circuit is measured.
A first period measuring circuit to determine the period of the horizontal synchronization signal
A second period measuring circuit for measuring the first and second
The measurement result of the period measurement circuit is calculated to control the PLL circuit.
And an arithmetic circuit for controlling the
You.

[0007]

By automatically reproducing the dot clock in accordance with the specification of the input video signal, the user can be freed from the task of adjusting the dot clock reproduction.

[0008]

FIG. 1 shows a first embodiment of the present invention. FIG. 1 includes an edge detection circuit 1, a period measurement circuit 2, a pulse oscillation circuit 3, an arithmetic circuit 4, and a PLL circuit 5. As shown in FIG. 2, the edge detecting circuit 1 includes a capacitor 6, a resistor 7, a voltage source 8, a voltage source 9, level comparators 10, 11, OR
It comprises a gate 21. The cycle measuring circuit 2 comprises a counter 12 and a latch 13 as shown in FIG. PLL circuit 5, as shown in FIG. 4, the phase comparator 14, L. P. F15, V
Frequency dividing counter 17 having CO 16 and frequency dividing ratio setting terminal 18
It is composed of

The operation of FIG. 1 is as follows. A video signal RGB from a personal computer or the like is supplied to an edge detection circuit 1-
1, 1-2 and 1-3. FIG. 5 shows operation waveforms of the edge detection circuit. The video signal input to the edge detection circuit 1 is differentiated by the capacitor 6 and the resistor 7, and the differentiated waveform is input to the level comparators 10 and 11. In order to obtain a differential waveform, a combination of a capacitor and an inductor or a combination of an inductor and a resistor may be used in addition to a capacitor and a resistor. The level comparators 10 and 11 compare the input differential waveform with the voltage sources 8 and 9, for example, when the differential waveform is larger than 1E, the output of the level comparator 10 is "H", and when the differential waveform is smaller than 2E, the level is The output of the comparator 11 becomes "H". The outputs of the level comparators 10 and 11 are input to an OR gate 21 to output a logical sum. The output of the OR gate 21 extracts a point where the video signal level largely changes, which corresponds to the dot clock cycle Td.

The output of the OR gate 21 is input to the period measuring circuit 2 as a pulse to be measured. In the cycle measuring circuit 2, the pulse to be measured is a clear pulse of the counter 12 and a clock pulse of the latch 13 as shown in FIG. on the other hand,
A pulse having a higher frequency than the pulse to be measured is input from the pulse oscillation circuit 3 to the counter 12 as a clock pulse. Therefore, when the pulse to be measured is input, the count value of the counter 12 becomes “0”, and the counter 12 counts the pulses of the pulse oscillator 3 until the next pulse to be measured is input. When the next pulse to be measured is input, the counting operation is stopped and the count value is set to “0”.
At the same time, the count value is latched by the latch 13 and is output as the period of the pulse to be measured.

The dot clock cycle is measured by the cycle measuring circuits 2-1, 2-2, 2-3, and the result is input to the arithmetic circuit 4. The period of the horizontal synchronizing signal is measured by the period measuring circuit 2-4, and the result is input to the arithmetic circuit 4. The arithmetic circuit 4 calculates the ratio of the period of the dot clock to the period of the horizontal synchronization signal using a microcomputer, for example, and outputs the result. The calculation method is, for example, the ratio of the period measurement circuits 2-1 and 2-4, the period measurement circuits 2-2 and 2-
4 and the ratio of the period measuring circuits 2-3 and 2-4 are respectively obtained, and the average of them is obtained. The output of the arithmetic circuit 4 obtained in this way corresponds to the total number of dots in one horizontal scanning period, and the dot clock can be reproduced by setting the multiple of the PLL circuit 5 to the total number of dots. The PLL circuit 5 is shown in FIG.
The division ratio setting terminal 1 of the division counter 17
The dot clock reproduced from the VCO 16 can be obtained by inputting the output of the arithmetic circuit 4, that is, the data of the total number of dots during one horizontal scanning period into 8.

As described above, the multiple of the PLL circuit 5 can be determined from the video signal and the horizontal synchronizing signal, and the dot clock of the input signal can be automatically reproduced.

A second embodiment of the edge detection circuit 1 is shown in FIG.
Shown in FIG. 6 shows an A / D converter 19, a latch 113, level comparators 20-1 and 20-2, and an OR gate 12.
1 is an edge detector. FIG. 7 shows operation waveforms. Hereinafter, the operation of FIG. 6 will be described.

The video signal is input to an A / D converter 19 and A / D converted by a clock applied to a terminal 22. The A / D-converted video signal is latched by the latch 113 by the clock applied to the terminal 22, and is input to the level comparators 20-1 and 20-2. The video signals before passing through the latch 113 are input to the level comparators 20-1 and 20-2. That is, the level comparators 20-1 and 20-2 compare the levels of signals delayed by one clock. For example, the output of the level comparator 20-1 is set to “H” when the relationship between the inputs A and B is A <B, and the output of the level comparator 20-2 is set to “H” when B <A. To do. In this way, the output of the level comparator 20-1 becomes “H” during the period when the video signal is increasing,
While the amplitude of the video signal is decreasing, the output of the level comparator 20-2 becomes "H". By taking the logical sum of the level comparators 20-1 and 20-2 by the OR gate 121, a point at which the level of the video signal greatly changes can be extracted, and the dot clock cycle Td can be detected.

By using the edge detection circuit of FIG. 6 as the edge detection circuit 1 of FIG. 1, the dot clock of the input video signal can be automatically reproduced in the same manner as in the first embodiment. The terminal 22 of the edge detection circuit shown in FIG.
In order to operate the / D converter 19 and the latch 113, the output of the pulse oscillator 3 may be applied.

FIG. 8 shows a third embodiment of the edge detection circuit 1. FIG. 8 shows an edge detection circuit including a sample hold circuit 23, level comparators 110 and 111, and an OR gate 221. FIG. 9 shows the operation waveform. Hereinafter, the operation of FIG. 8 will be described.

The video signal is input to a sample and hold circuit 23 and sampled and held by a clock pulse applied to a terminal 24.
11 is input. Also, the level comparator 110,
The video signal before being sampled and held is input to 111, and the level comparators 110 and 111 compare the video signal levels delayed by one clock as in the second embodiment. The video signal before being sampled and held is input to the-input of the level comparator 110,
The video signal after the sample and hold is input to the input so that, for example, the output of the level comparator 110 becomes “H” while the video signal level is increasing. On the other hand, the + input and the − input to the level comparator 111 are opposite to those of the level comparator 110, and the level comparator 1
11 is set to "H". This level comparator 1
By taking the logical sum of the outputs of 10 and 111 by the OR gate 221, it is possible to extract a point where the video signal level largely changes and detect the dot clock cycle Td.
By providing a slight hysteresis in the comparison voltage range of the level comparators 110 and 111, malfunction due to noise can be prevented.

By using the circuit of FIG. 8 for the edge detection circuit of FIG. 1, the dot clock can be automatically reproduced, as in the first embodiment. The output of the pulse oscillator 3 may be applied to the terminal 24 in FIG. 8 in order to operate the sample and hold circuit 23.

FIG. 10 shows a fourth embodiment of the edge detection circuit 1.
Shown in A delay circuit 25 is used in place of the sample and hold circuit 23 of the third embodiment. FIG. 11 shows operation waveforms. Except that the video signal is delayed by the delay circuit 25, the third embodiment is the same as the third embodiment, and thus a detailed description is omitted.

FIG. 12 shows an image display system using the present invention.
Shown in FIG. 12 includes a dot clock reproducing circuit 26 and an image display device 27. Dot clock regeneration circuit 2
6 is composed of, for example, a circuit as shown in FIG. The image display device 27 is, for example, a matrix display device such as a liquid crystal display, a CRT display, a video printer, or the like. First, as described in the embodiment, the dot clock is automatically reproduced by the dot clock reproducing circuit with auto preset 26, and the dot clock is input to the image display device 27 together with the video signal and the synchronization signals Hsync and Vsync. Perform the desired display.

FIG. 13 shows a second embodiment of the present invention.
FIG. 13 includes a dot clock reproduction circuit 126, an edge detection circuit 101, a correlator 28, a control circuit 30, and a delay circuit 29. The dot clock reproducing circuit is constituted by, for example, the circuit shown in FIG. Also, for example, the edge detection circuit
It is composed of the circuit shown in FIG. The correlator 28 includes an EX-OR gate 31, a resistor 107, and a capacitor 106 as shown in FIG. As shown in FIG. 15, the delay circuit includes a delay line 32 with a tap, a multiplexer 33, and an output switching terminal 34 of the multiplexer 33. The control circuit 30 includes an A / D converter 119 and a microcomputer 35.

A feature of the circuit shown in FIG. 13 is that the phase of the reproduced dot clock is made closer to the phase of the dot of the video signal.

The operation of FIG. 13 will be described below. The video signal is input to the edge detection circuit 101, and outputs a dot cycle pulse based on the above-described operation principle. The output is input to the correlator 28. On the other hand, the video signal is a horizontal synchronizing signal H
input to the dot clock recovery circuit together with sync,
This also reproduces the dot clock based on the above-described operation principle, and after receiving a certain delay in the delay circuit 29,
Is input to Here, the operation of the correlator is shown in FIG.
This will be described with reference to the waveform diagram of FIG. Edge detection circuit 10
The output of 1 and the output of the delay circuit 29 are input to the EX-OR gate 31 in the correlator 28. FIG. 17A shows the case where the delay circuit 29 is, for example, the output 33-a of the tapped delay line 32, and FIG. 17B shows the case where the output is the output 33-b of the tapped delay line 32. In the case of (a), the output of the edge detection circuit 101 and the output of the delay circuit 29 are different from those of (b), and the period of the output “H” of the EX-OR gate 31 is longer. Therefore, when this output is averaged by the resistor 107 and the capacitor 106, the voltage becomes higher in (a). That is, it means that the dot clock has shifted from the video signal. Further, the average value is A / D converted by the A / D converter 119 of the control circuit 30 and the data is taken into the microcomputer 35 to control the delay amount of the delay circuit. The control method uses, for example, a vertical retrace period, switches all of the multiplexers 33 during this period, and obtains the delay amount at which the output of the correlator becomes the smallest,
The multiplexer 33 is set to the value.

[0024] As described above, it is possible to reproduce the most phase shift is small wells Ttokurokku the dot of the video signal.

[0025]

According to the present invention, input images of various specifications are provided.
Signals that are suitable for displaying the input video signal.
The clock can be automatically reproduced. Yo
The user's burden of adjusting the dot clock.
Wear.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;

FIG. 2 is an edge detection circuit diagram of FIG. 1;

FIG. 3 is a configuration diagram of a cycle measuring circuit 2.

FIG. 4 is a block diagram of a PLL circuit;

FIG. 5 is an operation waveform diagram of the edge detection circuit;

FIG. 6 is a block diagram showing a second embodiment of the edge detection circuit;

7 is an operation waveform diagram of FIG.

FIG. 8 is a block diagram showing a third embodiment of the edge detection circuit;

FIG. 9 is an operation waveform diagram of FIG.

FIG. 10 is a block diagram showing a fourth embodiment of the edge detection circuit;

11 is an operation waveform diagram of FIG.

FIG. 12 is an image display system diagram using the present invention;

FIG. 13 is a block diagram showing a second embodiment of the present invention;

FIG. 14 is a circuit diagram of a correlator,

FIG. 15 is an explanatory diagram of a delay circuit;

FIG. 16 is a block diagram of a control circuit;

FIG. 17 is an operation waveform diagram of the correlator.

[Description of Signs] 1, 101: Edge detection circuit, 2: Period measurement circuit, 3: Pulse oscillation circuit, 4: Operation circuit, 5: PL
L circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G09G 5/00 H04N 3/27 H04N 5/06 H04N 5/44

Claims (9)

(57) [Claims] 1. A method of reproducing a dot clock by multiplying a frequency of a horizontal synchronizing signal inputted together with a video signal.
In the dot clock reproduction circuit having the PLL circuit thus formed , the video signal is used to match the dot cycle of the video signal.
An edge detection circuit for generating and outputting a pulse signal having an equivalent periodic pulse signal output from the edge detection circuit
A first cycle measuring circuit for measuring the cycle of the signal, a second cycle measuring circuit for measuring the cycle of the horizontal synchronizing signal, and calculating the P and the measurement results of the first and second cycle measuring circuits.
A dot clock reproducing circuit, comprising: an arithmetic circuit for controlling the LL circuit. 2. The dot clock reproducing circuit according to claim 1,
The Oite, the edge detection circuit includes a differentiating circuit for differentiating <br/> the video signal, the output signal and the reference voltage of the fine fraction circuit
Dot clock reproducing circuit, characterized by comprising a comparator for generating said pulse signal compared to. 3. The dot clock reproduction circuit according to claim 1,
Oite to said edge detector circuit, digital the video signal
An A / D converter for converting the barrel signal, the A / D con
Latch circuit for latching the output of the inverter , and the latch circuit
And the output signal from the latch circuit
This having a comparator for generating the pulse signal
And a dot clock reproducing circuit. 4. The dot clock reproduction circuit according to claim 1,
Oite to said edge detector circuit is San the video signal
A sample-and-hold circuit that pulls and holds the sample;
The input signal of the hold circuit and the output of the sample hold circuit
And a comparator for comparing the input signal with the input signal to generate the pulse signal . 5. The dot clock reproduction circuit according to claim 1, wherein said edge detection circuit delays said video signal.
A delay circuit, an input signal of the delay circuit,
A comparator for comparing the output signal with the output signal to generate the pulse signal;
And a dot clock generator, comprising:
Raw circuit. 6. The dot clock reproduction circuit according to claim 1,
In the arithmetic circuit, the first cycle measuring circuit
The ratio between the measurement result and the measurement result of the second period measurement circuit is
Determining a multiple of the PLL circuit.
Dot clock regeneration circuit. 7. A dot clock reproducing circuit according to claim 1.
Wherein the edge detection circuit is included in the video signal.
The pulse signals corresponding to each of the three primary color signals
The first period.
The measurement circuit outputs the three packets output from the edge detection circuit.
Measuring the period of each of the pulse signals;
The arithmetic circuit calculates the value of 3 measured by the first period measurement circuit.
The second period measurement for each of the periods of the two pulse signals.
Calculate the ratio to the period of the horizontal sync signal measured by the constant circuit.
Set the multiple of the PLL circuit from the average of the ratio
A dot clock reproducing circuit. Claim 8. A dot clock reproducing circuit according to claim 1.
An image display device comprising: 9. Horizontal sync signal input with video signal
To reproduce the dot clock by multiplying
Dot clock recovery circuit with PLL circuit
And Using the video signal, the dot period of the video signal is
Edge that generates and outputs a pulse signal with the corresponding period
A detection circuit, and a pulse signal output from the edge detection circuit.
A first period measuring circuit for measuring the period of the signal;
A second period measuring circuit for measuring the period of the period signal,
The measurement results of the first and second period measurement circuits Calculate the P
An arithmetic circuit for controlling the LL circuit;
A delay circuit for delaying the input dot clock;
Pulse signal output from the edge detection circuit and the delay circuit
Phase shift with the dot clock delayed by
A control circuit for controlling a delay amount of the delay circuit.
And a dot clock reproducing circuit.