JP2001215915A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of enhancing the detecting accuracy of completion positions of a horizontal video signal. SOLUTION: This display device is provided with a means detecting the completion position of a horizontal video for detecting completion positions of the horizontal video signal of video data based on second threshold and a threshold control means for controlling the second thresholds in accordance with levels of the video data to be outputted for A/D converters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device irrespective of the total number of horizontal dots of an input video signal.
The present invention relates to a liquid crystal display device that can appropriately display an image.

[0002]

2. Description of the Related Art In a liquid crystal display device, an image is displayed by synchronizing one dot of dot data included in an input video signal with one pixel of a liquid crystal panel in one horizontal scanning period. Also, line data of one horizontal scanning line in an arbitrary number of line data included in one vertical scanning period of the input video signal is displayed corresponding to one vertical line on the liquid crystal panel. This line data is an aggregate of dot data.

In recent years, computers of various specifications have been manufactured. Even if it is an XGA video signal output from various computers, for example, FIG.
And the video signal shown in FIG. 6B,
The total number of horizontal dots is different. However, in the XGA video signal, the number of dots (the number of horizontal effective dots) in the horizontal video effective period is common. That is, the number of horizontal effective dots of the XGA video signal is 1024.

[0004] A sampling clock for sampling 1024 dots in the horizontal image valid period of the input XGA video signal is generated based on the horizontal synchronizing signal of the input XGA video signal. Therefore, it is necessary to change the method of generating the sampling clock in accordance with the total number of horizontal dots of the input XGA video signal. For this reason,
In order to generate a sampling clock, it is necessary to recognize the total number of horizontal dots of the input XGA video signal.

Conventionally, a table in which the total number of horizontal dots is stored for each type of XGA video signal is prepared.
By determining the type of the GA video signal and selecting the total number of horizontal dots for the determined type from the table, the total number of horizontal dots of the input XGA video signal is recognized. However, this method cannot cope with an XGA video signal generated by a computer of a new specification.

Accordingly, the present applicant has developed a method of generating an appropriate sampling clock for a plurality of types of video signals of which the number of horizontal effective dots is known and the total number of horizontal dots is different, and has filed a patent application (Japanese Patent Application Laid-open No. No. 11-311967).

That is, a horizontal video start position HS (see FIG. 6) and a horizontal video end position HE (see FIG. 6) are detected for each horizontal line, and based on the detected horizontal video start position and horizontal video end position. Then, the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is calculated.

If the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is smaller than the known number 1024 of effective horizontal dots, sampling is performed in a direction to increase the frequency of the sampling clock. If the frequency of the clock is controlled and the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is greater than the value 1025 which is one larger than the known number of horizontal effective dots,
The frequency of the sampling clock is controlled so as to lower the frequency of the sampling clock.

When the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is equal to 1024 or 1025, the phase of the clock is shifted by at least one clock in several nano units. Delay.

[0010]

The horizontal video start position and the horizontal video start / end position of the input video signal are as follows:
It is detected by comparing input video data after AD conversion by the A / D converter with a predetermined threshold value.
However, these position detection precisions are greatly affected by the dullness of the analog input video signal input to the A / D converter.

Also, the threshold value used for detecting the horizontal video start position and the horizontal video start / end position of the input video signal is conventionally fixed, and the threshold value for the input video signal having a lower luminance is used for the input video signal. Since it has to be determined to be suitable, the rounding of the analog input video signal input to the A / D converter has a great effect on the position detection accuracy.

At the falling edge of the analog input video signal, dullness appears remarkably, and in the related art, there is a problem that the detection accuracy of the horizontal video end position is particularly low.

It is an object of the present invention to provide a display device capable of improving the accuracy of detecting the end position of a horizontal image.

[0014]

A display device according to the present invention generates a sampling clock based on a horizontal synchronization signal of an input video signal, and controls the frequency of the sampling clock based on a given frequency control value. A clock generation circuit, an A / D converter that samples an input video signal based on a sampling clock generated from the clock generation circuit, and a horizontal video start position of video data output from the A / D converter as a first threshold value. Horizontal video start position detecting means for detecting the horizontal video end position of the video data output from the A / D converter based on the second threshold value; Calculating means for calculating the number of sampling clocks corresponding to the distance to the horizontal video end position, a calculation result by the calculating means, Determining means for determining whether or not a given reference value matches; if it is determined that the calculation result by the calculating means does not match the reference value, the calculation result by the calculating means, the reference value, and a clock generation circuit A frequency control value adjusting means for calculating a new frequency control value based on the currently set frequency control value and providing the same to the clock generation circuit, and a second threshold value output from the A / D converter. It is characterized by including a threshold control means for controlling according to the level of the video data.

As the clock generating circuit, for example, a VCO for outputting a sampling clock, a frequency dividing circuit for dividing the sampling clock output from the VCO, an output of the frequency dividing circuit and a horizontal synchronizing signal of the input video signal are inputted. ,
A device having phase detection means for outputting a detection signal corresponding to the phase difference between the two input signals, and filter means for integrating the detection signal output from the phase detection means and outputting the integrated signal to the VCO is used. In this case, the frequency division value of the frequency division circuit is used as the frequency control value.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows the overall configuration of a liquid crystal display device.

The XGA video signals R, G, B sent from a computer (hereinafter referred to as PC) 10 are converted into A / D converters 2 at the subsequent stage by level adjusters 1R, 1G, 1B.
The level is adjusted to meet the input conditions of R, 2G, and 2B. The video signals R, G, and B whose levels have been adjusted are A /
After being converted into digital video data R, G and B by the D converters 2R, 2G and 2B, the scan conversion circuits 3R and 3R
G, 3B.

In the scan conversion circuits 3R, 3G and 3B, the video data R, G and B are scan-converted so as to be compatible with the liquid crystal panels 7R, 7G and 7B. Scan conversion circuits 3R, 3
The outputs of G and 3B are converted into analog video signals R, G and B by D / A converters 4R, 4G and 4B.

The video signals R, G, B output from the D / A converters 4R, 4G, 4B are sent to the liquid crystal panels 7R, 7G, 7B via the color signal driver 5 and the sample hold circuits 6R, 6G, 6B. Sent.

A timing signal is sent from the timing controller 30 to the scan conversion circuits 3R, 3G, 3B, the color signal driver 5, the sample hold circuits 6R, 6G, 6B and the liquid crystal panels 7R, 7G, 7B. A / D converters 2R, 2G, 2B and D / A converters 4R, 4G, 4
The sampling clock sent to B is generated by the sampling clock adjustment circuit 40. Timing controller 30 and sampling clock adjustment circuit 4
0 is controlled by the CPU 20.

FIG. 2 shows a sampling clock adjustment circuit 4.
0 is shown.

The sampling clock adjusting circuit 40 outputs a sampling clock based on a horizontal synchronizing signal (H signal) of an input video signal input from the computer 10, and a frequency of the sampling clock output from the PLL circuit 50. And a phase control circuit 70 for controlling the phase of the sampling clock output from the PLL circuit 50.

The phase control circuit 70 includes a fixed oscillator 71, a clock frequency conversion unit 72 for detecting the frequency of the sampling clock, and a delay for determining a unit delay amount based on the frequency of the sampling clock detected by the clock frequency conversion unit 72. A delay circuit 74 for delaying the phase of the horizontal synchronization signal based on the unit delay amount determined by the data creation unit 73 and the delay data creation unit 73 is provided.

As is well known, the PLL circuit 50 includes a phase detector 51, an LPF 52, a VCO 53 and a frequency divider 54. The phase detector 51 outputs a detection signal corresponding to the phase difference between the horizontal synchronization signal sent via the delay circuit 74 and the output signal of the frequency divider 54. The LPF 52 integrates the detection signal from the phase detection unit 51. The VCO 53 outputs a sampling clock having a frequency corresponding to the detection signal integrated by the LPF 52. The frequency dividing circuit 54 divides the frequency of the sampling clock output from the VCO 53 based on frequency division value data (horizontal total dot number detection data) from the horizontal total dot number detection circuit 60.

The horizontal total dot number detection circuit 60 includes a horizontal video start / end detection circuit 61, an H counter 62, a maximum hold section 63, a subtractor 64, a comparator 65, and a CPU 6
6 and a threshold control unit 67.

When a command to start adjusting the frequency of the sampling clock is input to the CPU 66, the CPU 66
66 outputs a horizontal total dot number detection start command. The command to start detection of the total number of horizontal dots is sent to the comparator 65. The comparator 65 becomes active when receiving the horizontal total dot number detection start command.

The sampling clocks for the A / D converters 2R, 2G, 2B are generated by a PLL circuit 50. The PLL circuit 50 receives a horizontal synchronization signal for the input video signal via a delay circuit 74 in the phase control circuit 70. The PLL circuit 50 includes a delay circuit 7
A sampling clock is generated based on the horizontal synchronizing signal output from the counter 4. The frequency of the sampling clock is adjusted by frequency division value data from the CPU 66 in the horizontal total dot number detection circuit 60. The phase of the sampling clock is adjusted by changing the delay amount of the delay circuit 74.

The digital R, G, B data obtained by the A / D converters 2R, 2G, 2B are sent to a horizontal video start / end detection circuit 61. The horizontal video start / end detection circuit 61 is provided for detecting a horizontal video start position and a horizontal video end position for each horizontal line based on output data of the A / D converters 2R, 2G, 2B. It is.

That is, the horizontal video start / end detection circuit 61
Is a pulse signal for one sampling clock when the input R, G, B data changes from a level lower than a predetermined threshold for start position determination to a level higher than the threshold for start position determination. Is output. However, after the horizontal image start signal is output by changing the input data from a level lower than the start position determination threshold to a level higher than the start position determination threshold, the input data is changed to the start position determination. When a level higher than the threshold value is maintained, the horizontal video start signal is not output. After the horizontal video start signal is output, if the input data becomes lower than the start position determination threshold and then exceeds the start position determination threshold again, the horizontal video start signal is output again. You.

The horizontal video start / end detection circuit 61
When the input R, G, B data changes from a level higher than the predetermined end position determination threshold to a level lower than the end position determination threshold, the sampling clock 1
It outputs a horizontal video end signal composed of pulse signals for the individual pieces. The horizontal video start signal and the horizontal video end signal output from the horizontal video start / end detection circuit 61 are
Sent to 2.

If a large value is set as the threshold value for discriminating the start position or the end position, data with low luminance cannot be read. If a small value is set as the threshold value, noise may be read as data. As the threshold value, a low value that does not pick up noise is set. In this embodiment, the start position determination threshold value used for detecting the horizontal image start position is fixed, but the end position determination threshold value used for detecting the horizontal image end position is used. The value is changed by the threshold control unit 67 according to the input video signal level. Details of the operation of threshold control section 67 will be described later.

The H counter 62 is reset each time a horizontal synchronizing signal is input from the delay circuit 74. The H counter 62 counts the number of sampling clocks input to the H counter 62. When a horizontal video start signal is sent from the horizontal video start / end detection circuit 61, the H counter 62 counts the count value (delay circuit 74).
(The number of sampling clocks from the point in time when the horizontal synchronization signal is input to the point in time when the horizontal video start signal is input)
Is sent to the maximum hold unit 63 as the horizontal video start count value (11 bits).

When the horizontal video end signal is sent from the horizontal video start / end detection circuit 61, the H counter 62 counts the count value (from the time when the horizontal synchronization signal is input from the delay circuit 74) to the horizontal counter. The horizontal video end count value (11 bits) is sent to the maximum hold section 63 as the horizontal video end count value (11 bits).

The maximum hold unit 63 includes the maximum hold unit 6
3 holds the smallest one of the horizontal video start count values input. This operation is referred to as a minimum value hold operation. The horizontal video start count value held in the maximum hold unit 63 is initialized to an initial value (for example, “2047”) when a vertical synchronization signal (V signal) is input.

The maximum hold section 63 holds the maximum horizontal video end count value. This operation is referred to as a maximum value hold operation. The horizontal video end count value held in the maximum hold unit 63 is initialized to an initial value (for example, “0”) when a vertical synchronization signal (V signal) is input.

The maximum hold section 63 sends the held horizontal video start count value and horizontal video end count value to the subtractor 64. The subtractor 64 calculates the difference between the horizontal video start count value and the horizontal video end count value sent from the maximum hold unit 63 (horizontal video end count value−horizontal video start count value), and calculates the calculation result. It is sent to the comparator 65.

Each time the vertical synchronizing signal (V signal) is input, the comparator 65 determines whether the subtraction result sent from the subtractor 64 matches the reference value or not. More specifically, it is determined whether or not the subtraction result sent from the subtractor 64 matches the number of horizontal effective dots of the input video signal or a value larger by 1 than that. In the following description, the type of the input video signal is XGA
Assume that it is a video signal. In this case, the comparator 6
5 indicates that the subtraction result sent from the subtractor 64 is an XGA
It is determined whether or not the number matches the number of horizontal effective dots of the video signal "1024" or a value "1025" which is larger by 1 than that.

If the subtraction result is "1024" or "102"
5 ", the match / mismatch determination signal is set to L level, and the subtraction results are" 1024 "and" 102 ".
If any one of 5 ″ matches, the match / mismatch determination signal is set to H level.

The result of the subtraction by the subtractor 64 is sent to the CPU 66 via the comparator 65. A match / mismatch determination signal from the comparator 65 is also sent to the CPU 66. The match / mismatch determination signal from the comparator 65 is also sent to the delay data creation unit 73.

The CPU 66 calculates the horizontal total dot value based on the following equation (1).

[0042]

(Equation 1)

The horizontal total dot value calculated by the CPU 66 is input to the frequency dividing circuit 54 as frequency dividing value data. The default value of the horizontal total dot value is set at the time of initial setting. As the default value, a value close to the general total number of horizontal dots of the XGA video signal, for example, “1225” is set.

When the above operation is performed and the subtraction result matches "1024" or "1025", the match / mismatch determination signal changes to H level.

When the coincidence / non-coincidence determination signal goes high, the delay data creation section 73 performs horizontal adjustment in units of several nanometers every time a vertical synchronization signal (V signal) is input in order to perform fine adjustment as described later. The delay circuit 74 is controlled so as to delay the synchronization signal. Also in this case, the maximum hold unit 63, the subtractor 64, the comparator 65, and the like perform the same operations as described above. At the time of this fine adjustment, when the coincidence / mismatch discrimination signal becomes L level, that is, when the subtraction result changes, the CPU 66 calculates the total number of horizontal dots based on the above equation 1 and calculates Update the circumference data.

When the total delay value reaches a predetermined value equal to or more than one sampling clock, the delay data creation unit 73 stops the delay control and
A horizontal total dot number detection end instruction is sent to the CPU 66. CP
U66, upon receiving the horizontal total dot number detection end command,
The frequency division value data is stored so that the frequency division value data does not change, and an instruction to end the detection of the total number of horizontal dots is sent to the comparator 65. The comparator 65 becomes inactive when receiving the horizontal total dot number detection end command.

As described above, the subtraction result of the subtractor 64 is "
The reason why delay control (fine adjustment) is performed after the value matches 1024 "or" 1025 "is as follows: An analog signal before sampling (A / D conversion) the video signal has a rounded waveform or the like. Therefore, the difference between the horizontal video start count value and the horizontal video end count value tends to be slightly larger than the actual 1024 dots.

Then, even if the frequency of the sampling clock is correct, the difference between the horizontal video start count value and the horizontal video end count value is "1024" depending on the phase of the sampling clock with reference to the horizontal synchronization signal. And "1025".

Therefore, the difference between the horizontal video start count value and the horizontal video end count value is "1024" or "102".
It is considered that the frequency of the sampling clock is appropriate when the value is 5 ". However, when it is determined that the difference between the horizontal video start count value and the horizontal video end count value is" 1025 ", the sampling clock frequency is determined. When the phase is changed, the difference between the horizontal video start count value and the horizontal video end count value may be “1026”.

Therefore, the difference between the horizontal video start count value and the horizontal video end count value is "1024" or "102".
After it is determined to be 5 ", the phase of the sampling clock is changed within a certain range, and the difference between the horizontal video start count value and the horizontal video end count value is temporarily set to" 102 ".
Even if it becomes 6 ", fine adjustment is performed so that the frequency of the sampling clock becomes small.

The clock frequency conversion unit 72 divides the frequency of the clock generated from the fixed oscillator 71 by
Create a reference clock signal with a fixed cycle width. Also, reset at the rising edge of the reference clock signal,
In addition, a counter for counting the sampling clock output from the VCO 53 is generated, and a counter value from when the counter is reset until the next reset is obtained.

The count value and the frequency of the sampling clock are in a proportional relationship, and it can be said that the higher the count value, the higher the frequency of the sampling clock. Since the cycle of the reference clock signal is known, the frequency of the sampling clock is obtained from the count value and the reference clock signal. The longer the period of the reference clock signal is, the higher the accuracy is. However, since the purpose is to find the unit delay amount and not to find the exact sampling clock frequency, the period of the reference clock signal is 30 μs.
About c is sufficient.

When the frequency of the sampling clock is obtained by the clock frequency conversion unit 72, the delay data creation unit 73 obtains the period T of the sampling clock.
A unit delay amount is determined based on a preset number of delays N. That is, the unit delay amount Δd is obtained based on the following Expression 2.

[0054]

(Equation 2)

Here, it is assumed that the number of delays N is set to eight. The frequency of the sampling clock calculated by the clock frequency conversion unit 72 is, for example, 2
In the case of 0 MHZ (the cycle is 50 [ns]), the unit delay amount is 6.25 [ns]. Each time a vertical signal is input, the delay data generating unit 73
4 has a phase of 6.25 [n
s], so that the delay amount of the delay circuit 74 is controlled so as to shift each time.

The frequency of the sampling clock calculated by the clock frequency conversion unit 72 is, for example, 125
In the case of MHZ (the cycle is 8 [ns]), the unit delay amount is 1 [ns]. The delay data creation unit 73
The delay amount of the delay circuit 74 is controlled such that the phase of the horizontal synchronization signal output from the delay circuit 74 is shifted by 1 [ns] every time a vertical signal is input.

The feature of this sampling clock adjusting circuit is that the threshold value for judging the end position used in the horizontal video start / end detection circuit 61 is changed according to the input video signal level so that the detection time can be maintained without lowering the accuracy. Is to shorten the time. Hereinafter, this feature will be described.

FIG. 3 shows a horizontal video effective period (the number of horizontal effective dots) detected by the sampling clock adjustment circuit according to the above embodiment.

FIG. 4 shows a horizontal video effective period (the number of horizontal effective dots) detected by the conventional sampling clock adjustment circuit.

In FIGS. 3 and 4, the signal (a) is
This shows an ideal analog input video signal without dullness. Further, the signal (b) or the signal (c) indicates a dull actual analog input video signal. As shown in signals (b) and (c), the rounding appears more prominently at the falling edge. In addition, THs indicates a start determination threshold value, and THe indicates an end position determination threshold value.

In the conventional sampling clock adjusting circuit, as shown in FIG.
And the end position determination threshold value THe are the same value,
Since these thresholds are set to small values in accordance with the case where the input video signal is a signal having a low luminance, the actually detected horizontal video effective periods L1 and L2 are the theoretical values of the horizontal video effective period. It is much longer than the value L. That is,
The detection accuracy of the number of horizontal effective dots decreases. in this way,
Even if the detection accuracy of the number of horizontal effective dots is low, in order to generate a sampling clock with the most appropriate frequency for the input video signal, it is necessary to finely adjust the phase fine adjustment unit. Takes longer.

On the other hand, in the sampling clock adjusting circuit according to the above-described embodiment, as shown in FIG. 3, the end position determination threshold value THe used for detecting the end position of the horizontal image is changed to the input image signal. It changes according to the level. For this reason, the end position determination threshold value THe does not need to be set in accordance with the case where the input video signal is a signal with low luminance, and can be set to a large value. As a result, the actually detected horizontal video effective period L
1, L2 is the theoretical value L of the horizontal image effective period as compared with the related art.
It is a value close to.

This means that the necessity of the phase fine adjustment is reduced and the unit of adjustment at the time of the phase fine adjustment can be reduced, so that the adjustment accuracy can be improved and the adjustment time can be shortened. .

The operation of threshold value control section 67 for controlling end position determination threshold value THe will be described in detail.

The threshold control unit 67 includes a horizontal synchronizing signal (H signal) and a vertical synchronizing signal (V signal) of the input video signal, output signals of the A / D converters 2R, 2G, 2B, and start and end of the horizontal video. The horizontal video end signal from the detection circuit 61, H
The horizontal video end count value from the counter 62 and the horizontal video end count value from the maximum hold unit 63 are input.

The threshold control unit 67 sets the threshold
In the vertical period, the end position determination threshold value T used in the horizontal image start / end detection circuit 61 based on the input image signal level when the image end count value is the maximum.
Update He. The operation of the threshold value control section 67 is started before the horizontal total dot detection operation is started.

A method of detecting the end position determination threshold value THe will be described with reference to FIG.

The threshold value calculated based on the horizontal video end position detected by the horizontal video start / end detection circuit 61 within one vertical period is referred to as an intermediate threshold value. The end position determination threshold value THe is updated every one vertical period based on the intermediate threshold value calculated in the preceding one vertical period. The initial values of the intermediate threshold value and the end position determination threshold value THe are “40” in hexadecimal.
h ". The intermediate threshold value is initialized to an initial value each time a vertical synchronization signal (V signal) is output.

In principle, the video data (outputs of the A / D converters 2R, 2G, 2B) when the horizontal video end position is detected by the horizontal video start / end detection circuit 61 is taken in every horizontal period. , Is stored as video end position data, and the intermediate threshold value is updated based on the video end position data.
The intermediate threshold value is set to a half value of the video data, with the minimum value being 40h. The initial value of the video end position data is “00h”, and the video end position data is initialized so as to become the initial value every time the vertical synchronization signal is output.

However, there are the following exceptions. As shown in FIG. 5, when the video end count value for the horizontal video end position detected by the horizontal video start / end detection circuit 61 is smaller than the video end count value held by the maximum hold unit 63, the detection is performed. Since the horizontal video end position is not a true horizontal video end position, the captured video data is not stored as video end position data. That is, in this case, the intermediate threshold is not updated.

When the vertical synchronizing signal is output, the intermediate threshold value held at that time is output to the horizontal image start / end detection circuit 61 as the end position determination threshold value THe, and the intermediate threshold value is also output. The value and the video end position data are returned to the initial values.

By repeating the above operation,
Each time the vertical synchronization signal (V signal) is output, the end position determination threshold value THe is updated.

[0073]

According to the present invention, the detection accuracy of the horizontal video end position can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device.

FIG. 2 is a block diagram illustrating a configuration of a sampling clock control circuit.

FIG. 3 is a schematic diagram showing an end position determination threshold set according to the embodiment;

FIG. 4 is a schematic diagram showing a conventional end position determination threshold value.

FIG. 5 is a timing chart for explaining an operation of threshold control section 67;

FIG. 6 is a timing chart showing XGA video signals having mutually different total numbers of horizontal dots.

[Explanation of symbols]

 2R, 2G, 2B A / D converter 10 Computer 40 Sampling clock adjustment circuit 50 PLL circuit 60 Horizontal total dot number detection circuit 67 Threshold control unit 70 Phase adjustment circuit

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yasuo Onishi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. 2H093 NA06 NC21 NC23 NC24 NC49 NC50 ND36 ND60 5C006 AF54 AF72 BB11 BC16 BF11 BF14 BF28 FA08 FA16 5C080 AA10 BB05 DD09 JJ02 JJ04

Claims (2)

[Claims] A clock generation circuit for generating a sampling clock based on a horizontal synchronization signal of an input video signal and controlling the frequency of the sampling clock based on a given frequency control value, An A / D converter that samples based on a sampling clock generated from the A / D converter; a horizontal image start position detecting unit that detects a horizontal image start position of image data output from the A / D converter based on a first threshold value; Horizontal video end position detection means for detecting a horizontal video end position of video data output from the A / D converter based on a second threshold value, sampling corresponding to a distance from the horizontal video start position to the horizontal video end position Calculating means for calculating the number of clocks, determining whether or not a calculation result obtained by the calculating means matches a given reference value When it is determined that the calculation result by the calculation means does not match the reference value, based on the calculation result by the calculation means, the reference value, and the frequency control value currently set in the clock generation circuit, Frequency control value adjusting means for calculating a new frequency control value and applying it to the clock generation circuit, and threshold value control means for controlling the second threshold value according to the level of video data output from the A / D converter A display device, comprising: 2. A clock generating circuit, comprising: a VCO for outputting a sampling clock; a frequency dividing circuit for dividing a sampling clock output from the VCO; an output of the frequency dividing circuit and a horizontal synchronization signal of an input video signal; A phase detection means for outputting a detection signal corresponding to the phase difference between the two input signals; and a filter means for integrating the detection signal output from the phase detection means and outputting the integrated signal to the VCO. The display device according to claim 1, wherein is used as a frequency control value.