JP3515441B2 - Display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a liquid crystal display device capable of appropriately displaying an image regardless of the total number of horizontal dots of an input image signal.

[0002]

2. Description of the Related Art In a liquid crystal display device, an image is displayed by synchronizing one dot of dot data included in an input video signal with one pixel of a liquid crystal panel in one horizontal scanning period. Further, the line data of one horizontal scanning line in the arbitrary number of line data that the input video signal has within one vertical scanning period is displayed corresponding to one line in the vertical direction in the liquid crystal panel. This line data is a set of dot data.

In recent years, computers having various specifications have been manufactured. Even if the XGA video signal is output from various computers, for example, as shown in FIG.
The video signal shown in FIG. 10A and the video signal shown in FIG. 10B have different numbers of dots in the horizontal period (horizontal total number of dots). However, in the XGA video signal, the number of dots within the horizontal video valid period (the number of horizontal valid dots) is common.
That is, the number of horizontal effective dots of the XGA video signal is 102
It is 4 dots.

A sampling clock for sampling 1024 dots in the horizontal video effective period of the input XGA video signal is generated based on the horizontal synchronizing signal of the input XGA video signal. Therefore, it is necessary to change the sampling clock generation method according to the total number of horizontal dots of the input XGA video signal. For this reason,
In order to generate the sampling clock, it is necessary to recognize the total number of horizontal dots of the input XGA video signal.

Conventionally, a table in which the total number of horizontal dots is stored is prepared for each type of XGA video signal, and X is determined from the characteristics of the XGA video signal input from the computer.
The type of the GA video signal is discriminated, and the total horizontal dot number for the discriminated type is selected from the table, whereby the horizontal total dot number of the input XGA video signal is recognized. However, this method cannot deal with the XGA video signal generated by the computer of the new specification.

[0006]

Therefore, the applicant of the present invention is
A method for generating an appropriate sampling clock for a plurality of types of video signals in which the number of horizontal effective dots is known and the total number of horizontal dots is different was developed and applied for a patent (Patent application 10
-119641).

That is, the horizontal video start position and the horizontal video end position are detected for each horizontal line. Of the horizontal video start positions detected in one field, the horizontal video start position closest to the horizontal period start position specified by the horizontal sync signal and the horizontal video end position detected in one field are horizontally synchronized. The number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is calculated for each field based on the horizontal video end position farthest from the horizontal period start position specified by the signal. .

The number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is compared with a preset value (known horizontal effective dot number, for example, 1024), The frequency of the sampling clock is controlled based on the comparison result. Specifically, if the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is larger than 1024, the frequency of the sampling clock is controlled so that the frequency becomes smaller. Conversely, if the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal is smaller than 1024, the frequency of the sampling clock is controlled so as to increase.

However, in this method, if there is valid data at the front end of the horizontal image valid period in any of the horizontal lines and no valid data at the rear end of the horizontal image valid period in any of the horizontal lines. , The horizontal video start position and the horizontal video end position of the input video signal cannot be accurately detected.

If there is no valid data at the front end of the horizontal video valid period in any horizontal line, or if there is no valid data at the rear end of the horizontal video valid period in any horizontal line, the detected horizontal Since the number of sampling clocks corresponding to the distance from the video start position to the detected horizontal video end position becomes smaller than the actual value, it becomes impossible to obtain a sampling clock having a frequency suitable for the input video signal.

According to the present invention, when the sampling clock is adjusted for a plurality of types of video signals having a known horizontal effective dot number and different horizontal total dot numbers, an appropriate sampling clock can be generated regardless of the input image.
As a result, it is an object of the present invention to provide a display device capable of displaying an appropriate video image for a plurality of types of video signals having a known horizontal effective dot number and different horizontal total dot numbers.

[0012]

A display device according to the present invention generates a sampling clock based on a horizontal synchronizing signal of an input video signal sent from a computer ,
And clock generator frequency of the sampling clock is controlled based on a given frequency control value, the competent
A / D converter for sampling the input video signal sent from the computer based on the sampling clock generated from the clock generation circuit, and a first cursor control command to the computer at the time of adjusting the sampling clock.
By giving a first cursor control for stopping a predetermined period by moving the cursor image included in the input video to a predetermined stop position of the left side of the input image screen, the competent
By giving the computer a second cursor control command,
An image output from the A / D converter that repeatedly performs a second cursor control that moves a cursor image included in the input image to a predetermined stop position on the right end side of the input image screen and stops for a predetermined period. Detection means for detecting the horizontal video start position and the horizontal video end position of the video data by comparing the data with a predetermined threshold value,
Each time one cycle of cursor control consisting of one cycle of first cursor control and one cycle of second cursor control is performed,
Of the horizontal image start positions detected when the cursor image is stopped at the predetermined position on the left side of the screen, the horizontal image start position closest to the horizontal period start position specified by the horizontal sync signal and the cursor image are Based on the horizontal video end position farthest from the horizontal period start position specified by the horizontal sync signal among the horizontal video end positions detected in the state of being stopped at the predetermined position on the right end side of the screen, the input video signal Calculation means for calculating the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of each, and the calculation result by the calculation means and the given reference value every time the cursor control for one cycle is performed. When it is determined that the calculation result by the calculation means and the reference value do not match, the calculation means determines whether the value and the reference value match. Based on the calculation result, the reference value, and the frequency control value currently set in the clock generation circuit, the new frequency control value is calculated and given to the clock generation circuit by the frequency control value adjusting means and the calculating means. When it is determined that the calculation result and the reference value match,
It is characterized in that it is provided with means for determining the frequency control value currently set in the clock generation circuit as an appropriate frequency control value.

As the clock generation circuit, for example, a VCO which outputs a sampling clock, a frequency dividing circuit which divides the sampling clock output from the VCO, an output of the frequency dividing circuit and a horizontal synchronizing signal of the input video signal are input. ,
What is provided with a phase detection means for outputting a detection signal according to the phase difference between both input signals and a filter means for integrating the detection signal output from the phase detection means and outputting it to the VCO is used.

When such a clock generation circuit is used, the frequency division value of the frequency division circuit is used as the frequency control value. Further, as the frequency control value adjusting means,
A value that calculates a new frequency division value by calculating (reference value × frequency division value currently set / calculation result by the calculation means) is used.

The stop position on the left end side of the cursor image is set, for example, so that the white pixel of the cursor image is located at the second pixel in the horizontal direction from the upper left end of the input image screen.
The stop position on the right end side of the cursor image is set so that the white pixel of the cursor image is located at the right end pixel of the input image screen.

That is, in a state where the cursor image is stopped at a predetermined position on the left end side of the input image screen, after the horizontal image start position is detected based on the white pixel of the cursor image, it is specified by the horizontal synchronizing signal. If a horizontal video start position closer to the horizontal period start position is detected,
The reference value is set to the number of horizontal effective dots of the input video signal. When the cursor image is stopped at a predetermined position on the left end side of the input image screen, after the horizontal image start position is detected based on the white pixels of the cursor image, the horizontal period start position specified by the horizontal synchronization signal When the near horizontal image start position is not detected, the reference value is set to a value smaller by 1 than the number of horizontal effective dots of the input image signal.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention applied to a liquid crystal display device will be described below with reference to the drawings.

FIG. 1 shows the overall structure of a liquid crystal display device.

The XGA video signals R, G, B sent from a computer (hereinafter referred to as a PC) 10 are processed by the level adjusting units 1R, 1G, 1B and the A / D converter 2 in the subsequent stage.
The level is adjusted to meet the input conditions of R, 2G, and 2B. The video signals R, G, and B whose levels have been adjusted are A /
After being converted into digital video data R, G, B by the D converters 2R, 2G, 2B, scan conversion circuits 3R, 3
Sent to G, 3B.

In the scan conversion circuits 3R, 3G, 3B, the video data R, G, B are scan converted so as to be suitable for the liquid crystal panels 7R, 7G, 7B. Scan conversion circuits 3R, 3
The outputs of G and 3B are converted into analog video signals R, G and B by D / A converters 4R, 4G and 4B.

The video signals R, G, B output from the D / A converters 4R, 4G, 4B are transmitted to the liquid crystal panels 7R, 7G, 7B via the color signal driver 5 and the sample hold circuits 6R, 6G, 6B. Sent.

Timing signals are sent from the timing controller 30 to the scan conversion circuits 3R, 3G, 3B, the color signal driver 5, the sample hold circuits 6R, 6G, 6B and the liquid crystal panels 7R, 7G, 7B. A / D converters 2R, 2G, 2B and D / A converters 4R, 4G, 4
The sampling clock sent to B is generated by the sampling clock adjustment circuit 40. Timing controller 30 and sampling clock adjustment circuit 4
0 is controlled by the CPU 20.

FIG. 2 shows a sampling clock adjusting circuit 4
0 configuration is shown.

The sampling clock adjusting circuit 40 outputs the sampling clock based on the horizontal synchronizing signal (H signal) of the input video signal input from the computer 10, and the frequency of the sampling clock output from the PLL circuit 50. And a phase control circuit 70 for controlling the phase of the sampling clock output from the PLL circuit 50 and the horizontal total dot number detection circuit 60.

The phase control circuit 70 includes a delay circuit 71 to which the horizontal synchronizing signal of the input video signal is input and a delay data creating section 72 for controlling the delay circuit 71.

As is well known, the PLL circuit 50 includes a phase detector 51, an LPF 52, a VCO 53 and a frequency divider 54. The phase detector 51 receives the horizontal synchronizing signal sent via the delay circuit 71 and the output of the frequency divider 54. The output of the phase detector 51 is input to the LPF 52. LPF5 for VCO53
The output of 2 is input. A sampling clock output from the VCO 53 and frequency division value data (horizontal total dot number detection data) from the horizontal total dot number detection circuit 60 are input to the frequency dividing circuit 54.

The horizontal total dot number detection circuit 60 includes a horizontal video start / end detection circuit 61, an H counter 62, a maximum hold section 63, a subtractor 64, a comparator 65 and a CPU 6.
6, a reference value determination unit 67, a cursor control unit 68, and a timing conversion unit 69.

The feature of the horizontal total dot number detection circuit 60 is that the horizontal image start position and the horizontal image end position are accurately detected by using the cursor displayed on the liquid crystal panel. Therefore, first, the operations of the cursor control unit 68 and the timing conversion unit 69 will be described. In the following description, the total dot means the total number of horizontal dots.

When a command for starting the adjustment of the sampling clock frequency is input to the CPU 66, the CPU
66 outputs a total dot detection start command. The total dot detection start command is sent to the comparator 65. Upon receiving the total dot start command, the comparator 65 activates the total dot detection signal (L level) at the timing synchronized with the vertical synchronizing signal (V signal) of the input video signal. The total dot detection signal is sent to the cursor control unit 68 and the timing conversion unit 69.
Sent to. When the total dot detection signal becomes active, the cursor control unit 68 sends a cursor movement command for moving the cursor to the upper left position to the PC 10, as shown in FIGS. 3 and 4.

Here, it is assumed that an XGA compatible display is used as the liquid crystal display. Therefore, the cursor is moved to the left by the maximum number of images 1024 in the X direction to the Y direction.
A cursor movement command for moving the maximum number of images in the direction 768 upward is sent to the PC 10.

Then, regardless of the position of the cursor on the screen, when a predetermined time longer than the time required to move the cursor to the upper left position has passed, the cursor control unit 68 causes one vertical scanning synchronized with the input video signal. A cursor stop signal for stopping the cursor at the upper left position for the time corresponding to the period is output to the timing conversion unit 69. Timing conversion unit 6
When the cursor stop signal is first received after the total dot detection signal becomes active, 9 outputs the cursor upper left stop signal for one vertical period synchronized with the vertical sync signal of the input video signal.

The cursor control unit 68 issues a cursor movement command for moving the cursor to the lower right position when a predetermined time elapses after the cursor stop signal is output to the PC 10.
Send to. In other words, move the cursor to the maximum number of images in the X direction 10
A cursor movement command is sent to the PC 10 to move 24 directions to the right and downward by the maximum number 768 of images in the Y direction.

When a predetermined time longer than the time required to move the cursor from the upper left position to the lower right position elapses, the cursor is moved by 2 pixels to the left and 5 pixels upward. Send a command to the PC 10.
The reason why after moving the cursor to the lower right position, the cursor is further moved by 2 pixels in the left direction and 5 pixels in the upward direction will be described.

When the cursor is moved from the upper left position to the lower right position, only the black pixel at the apex of the cursor is displayed as shown in FIG. Therefore, move the cursor to the left by 2
By moving the pixel, 5 pixels upwards,
As shown in FIGS. 6 and 7, white data (valid data) exists at the right end. After that, FIG.
The cursor position in FIG. 7 will be referred to as the lower right position of the cursor.

After that, a cursor stop signal for stopping the cursor at the lower right position for a period corresponding to one vertical scanning period synchronized with the input video signal is output to the timing converter 69. When receiving the cursor stop signal, the timing conversion unit 69 outputs the cursor lower right stop signal for one vertical period in synchronization with the vertical synchronizing signal of the input video signal.

After the cursor stop signal is output, the cursor control unit 68 issues a cursor movement command to move the cursor to the upper left position when a predetermined time elapses.
And repeat the same processing as above. And
Total dot detection signal is inactive (H level)
When, the cursor control ends.

The horizontal total dot number detection circuit 60 detects the horizontal image start position when the cursor is stopped at the upper left position, and detects the horizontal image end position when the cursor is stopped at the lower right position. It

When the cursor is stopped at the upper left position, since the left end of the cursor is a black pixel, effective data starts from the second pixel on the screen. Therefore, the horizontal video start position is detected when the cursor is stopped at the upper left position,
When the horizontal video end position is detected when the cursor is stopped at the lower right position, the subtraction result of the subtracter 64 is smaller than the normal horizontal effective dot number 1024 by 1 if the frequency of the sampling clock is appropriate. Value "1023"
Becomes

However, when the video signal such that the left edge of the screen becomes valid data is input when the cursor is stopped at the upper left position, if the frequency of the sampling clock is appropriate, the subtractor The subtraction result of 64 is the regular horizontal effective dot number 1024. Therefore, the horizontal total dot number detection circuit 60 receives a video signal such that the left end of the screen is valid data and a case where a video signal such that the left end of the screen is valid data is not input. A reference value determination unit 67 is provided to determine whether or not. The operation of the reference value determination unit 67 will be described later.

The sampling clock for the A / D converters 2R, 2G, 2B is generated by the PLL circuit 50. The horizontal synchronizing signal for the input video signal is sent to the PLL circuit 50 via the delay circuit 71 in the phase control circuit 70. The PLL circuit 50 includes the delay circuit 7
A sampling clock is generated on the basis of the horizontal synchronizing signal output from 1. The frequency of the sampling clock is adjusted by frequency division value data from the CPU 66 in the horizontal total dot number detection circuit 60. The phase of the sampling clock is adjusted by changing the delay amount of the delay circuit 71.

The digital R, G, B data obtained by the A / D converters 2R, 2G, 2B are sent to the horizontal video start / end detection circuit 61. The horizontal video start / end detection circuit 61 is provided to detect the horizontal video start position and the horizontal video end position for each horizontal line based on the output data of the A / D converters 2R, 2G, 2B. Is.

That is, the horizontal image start / end detection circuit 61.
Is the sampling clock 1 when the input R, G, B data changes from a level lower than a predetermined threshold value (video slice level) to a level higher than the threshold value.
A horizontal image start signal composed of individual pulse signals is output. However, after the horizontal image start signal is output by changing the input data from the level lower than the threshold to the level higher than the threshold, the input data maintains the level higher than the threshold. In this case, the horizontal video start signal is not output. After the horizontal image start signal is output, if the input data becomes lower than the threshold value and then exceeds the threshold value again, the horizontal image start signal is output again.

Further, the horizontal video start / end detection circuit 61 is
When the input R, G, B data changes from a level higher than a predetermined threshold value to a level lower than the threshold value,
A horizontal image end signal composed of a pulse signal for one sampling clock is output. Horizontal video start / end detection circuit 6
The horizontal video start signal and the horizontal video end signal output from 1 are sent to the H counter 62.

When a large value is set as the threshold value, low-luminance data cannot be read. When a small value is set as the threshold value, noise may be read as data. Is set to a low value.

The H counter 62 is reset every time the horizontal synchronizing signal is input from the delay circuit 71. The H counter 62 counts the number of sampling clocks input to the H counter 62. When the horizontal video start signal is sent from the horizontal video start / end detection circuit 61, the H counter 62 counts at that time (delay circuit 71
(The number of sampling clocks from the time when the horizontal sync signal from is input to the time when the horizontal video start signal is input)
Is sent to the maximum hold unit 63 as the horizontal image start count value (11 bits).

When the horizontal video start signal is sent from the horizontal video start / end detection circuit 61, the H counter 62 receives the count value at that time (the horizontal value from the time when the horizontal sync signal from the delay circuit 71 is input). The sampling clock number up to the time when the video end signal is input is sent to the maximum hold unit 63 as the horizontal video end count value (11 bits).

The maximum hold unit 63 is input to the maximum hold unit 63 while the cursor upper left stop signal is output from the timing conversion unit 69 (while the cursor upper left stop signal is active (H level)). The smallest horizontal image start count value is held.
This operation is called a minimum value holding operation. The horizontal image start count value held in the maximum hold unit 63 is initialized to an initial value (for example, “2047”) when the cursor upper left stop signal becomes active.

Further, the maximum hold unit 63 ends the horizontal image while the cursor lower right stop signal is being output from the timing conversion unit 69 (while the cursor lower right stop signal is active (H level)). Hold the largest of the count values. This operation is called maximum value holding operation. The horizontal image end count value held in the maximum hold unit 63 is set to an initial value (for example, "" when the cursor lower right stop signal becomes active.
0 ") is initialized.

Further, the maximum hold unit 63 uses the minimum value hold signal as the reference value determination unit 6 when the horizontal image start count value is updated (including the case where it is updated from the initial value).
Send to 7. The reference value determination unit 67 receives the minimum value hold signal twice or more while the cursor upper left stop signal is active (H level) (when the horizontal video start count value is updated twice or more). , It is determined that a video signal such that the left end of the screen is valid data is input, and the reference value determination signal output to the comparator 65 is set to H level. Then, the H level is maintained until the next cursor lower left stop signal becomes active (H level).

The reference value judging section 67 is provided while the cursor upper left stop signal is active (H level).
When the minimum value hold signal is received only once (when the horizontal image start count value is updated only once), it is determined that no image signal is input so that the left edge of the screen becomes valid data. Then, the reference value determination signal output to the comparator is set to L level. Then, until the next cursor lower left stop signal becomes active (H level), L
Maintain the level.

The maximum hold unit 63 sends the held horizontal video start count value and horizontal video end count value to the subtractor 64. The subtractor 64 includes a timing conversion unit 69.
Stop signal from the bottom right of the cursor is at H level (active)
Difference from the horizontal video start count value and the horizontal video end count value sent from the maximum hold unit 63 at the time of changing from the L level to the L level (inactive) (horizontal video end count value-horizontal video start count value) Is calculated and the calculation result α is sent to the comparator 65.

The comparator 65 determines whether the subtraction result α sent from the subtractor 65 matches the reference value β, is smaller than the reference value β, or is larger than the reference value β. The reference value β is determined based on the reference value determination signal from the reference value determination unit 67. That is, the reference value determination signal is H
When the level is the level, the reference value β is determined by the horizontal effective dot number 1024 of the XGA video signal, and when the reference value determination signal is the L level, the reference value β is determined by 1023.

When the subtraction result α does not match the reference value β, the comparator 65 outputs the match / mismatch determination signal to L.
When the subtraction result matches the reference value β, the comparator 65 sets the match / mismatch determination signal to the H level.

The subtraction result α by the subtractor 64 is sent to the CPU 66 via the comparator 65. A match / mismatch determination signal from the comparator 65 is also sent to the CPU 66.

The CPU 66 calculates the horizontal total dot value based on the following formula 1.

[0056]

[Equation 1]

The horizontal total dot value calculated by the CPU 66 is input to the frequency dividing circuit 54 as frequency dividing value data. The default value of the horizontal total dot value is set at the time of initial setting. As this default value, a value close to the general horizontal total number of dots of the XGA video signal, for example, "1225" is set.

FIG. 8 shows signals of the respective parts of FIG. 2 when a video signal such that the left end of the screen becomes valid data is not input.

In this example, the number of horizontal effective dots of the input video signal is "1024", and the total number of horizontal dots is "140".
The case of 0 "will be described. However, the number of horizontal effective dots is known, but the total number of horizontal dots is unknown.

When a command for starting the adjustment of the sampling clock frequency is input to the CPU 66, the CPU 66
A total dot detection start command is output from 66, and the frequency division value data is initialized by the CPU 66. In this example, the initial value is "1225". Also,
“2047” is set as the initial value of the horizontal video start count value of the maximum hold unit 63, and “0” is set as the initial value of the horizontal video end count value.

Based on the total dot detection start command,
When the total dot detection signal output from the comparator 65 becomes active (L level), the cursor control unit 68 starts moving the cursor toward the upper left end. However, the minimum value holding operation and the maximum value holding operation by the maximum holding unit 63 and the comparator 6
The coincidence determination operation by 5 is prohibited, and the frequency division value data is also held as it is.

When the cursor is stopped at the upper left position and the cursor upper left stop signal from the timing conversion unit 69 becomes active (H level), the maximum hold unit 63 holds the minimum value of the horizontal video start count value. Hold operation is performed. The horizontal image start count value is set to the initial value "2" by the minimum value hold operation by the maximum hold unit 63.
It is assumed that the value changes from 047 "to" 176 ", for example.

When the cursor upper left stop period ends, the cursor starts moving toward the lower right position. Also in this case, the minimum value holding operation and the maximum value holding operation by the maximum holding unit 63 and the coincidence determination operation by the comparator 65 are prohibited, and the frequency division value data is also held as it is.

When the cursor is stopped at the lower right position and the cursor lower right stop signal from the timing conversion unit 69 becomes active (H level), the maximum hold unit 63 holds the maximum horizontal image end count value. Performs maximum value hold operation. The maximum value hold operation by the maximum hold unit 63 causes the horizontal video end count value to be the initial value "
It is assumed that the value changes from 0 ”to, for example,“ 1071 ”.

When the lower right cursor stop signal becomes L level, the subtracter 64 causes the horizontal video end count value "1".
071 "is subtracted from the horizontal image start count value" 176 ", and the calculation result α = 895 is sent to the comparator 65. The comparator 65 calculates the calculation result"
895 "is compared with the reference value β. In this case, since the reference value determination signal is at the L level," 1023 "is used as the reference value β.

The calculation result "895" is the reference value "1023".
Therefore, the match / mismatch determination signal remains at the L level. Also, the calculation result “895” is the reference value ”
Since it does not match 1023 ", the operation result is" 895 ".
Is sent to the CPU 66, and the horizontal total dot value is calculated based on the above mathematical expression 1. In this case, the horizontal total dot value is 1023 × (1225-895) = 1400.19.
5, the rounded value "1400" is sent to the frequency dividing circuit 54 as frequency dividing value data. As a result, the frequency division value data is updated from "1225" to "1400".

After that, the cursor starts moving toward the upper left end again. Also in this case, the minimum value holding operation and the maximum value holding operation by the maximum holding unit 63 and the coincidence determination operation by the comparator 65 are prohibited, and the frequency division value data is also held as it is.

When the cursor is stopped at the upper left position and the cursor upper left stop signal from the timing conversion unit 69 becomes active (H level), the horizontal image start count value held in the maximum hold unit 63 is the initial value "2047". After the initialization, the maximum hold unit 63 starts the minimum value hold operation. By the minimum value hold operation by the maximum hold section 63, the horizontal image start count value is "
Suppose that it has changed from 2047 "to" 201 ".

When the cursor upper left stop period ends, the cursor starts moving toward the lower right position. Also in this case, the minimum value holding operation and the maximum value holding operation by the maximum holding unit 63 and the coincidence determination operation by the comparator 65 are prohibited, and the frequency division value data is also held as it is.

When the cursor is stopped at the lower right position and the cursor lower right stop signal from the timing conversion unit 69 becomes active (H level), the horizontal video end count value held in the maximum hold unit 63 is the initial value " After being initialized to 0 ″, the maximum holding unit 63 starts the maximum value holding operation. It is assumed that the horizontal image end count value is changed from "0" to "1224" by the maximum value hold operation by the maximum hold unit 63.

When the lower right cursor stop signal becomes L level, the subtracter 64 causes the horizontal video end count value "1".
A calculation for subtracting the horizontal image start count value “201” from 224 ″ is performed, and the calculation result α = 1023 is sent to the comparator 65. The comparator 65 compares the calculation result “1023” with the reference value “1023”. To do.

The calculation result "1023" is the reference value "102".
Since it matches 3 ", the match / mismatch determination signal changes to H level.

When the coincidence / non-coincidence determination signal changes to the H level, the delay data creating section 72 moves one cycle interval from the cursor movement to the upper left to the coincidence determination for fine adjustment as described later. Each time, the delay circuit 71 is controlled so as to delay the horizontal synchronization signal in units of several nanometers. Also in this case, the same operations are repeated for the cursor control unit 68, the maximum hold unit 63, the subtractor 64, the comparator 65, and the like.

At the time of this fine adjustment, the comparator 6
5 determines whether or not the calculation result of the subtracter 64 matches the reference value β or a value (β + 1) larger by 1 than the reference value β. When the calculation result of the subtractor 64 matches either the reference value β or a value (β + 1) larger by 1 than the reference value, the frequency division value data is held as it is. If the calculation result of the subtracter 64 does not match either the reference value β or a value (β + 1) larger by 1 than the reference value, C
The PU 66 calculates the horizontal total dot value based on Equation 1 above, and updates the frequency division value data.

When the total delay value reaches a predetermined value of one sampling clock or more, the delay data creating section 72 stops the delay control and sends a horizontal total dot detection end command to the CPU 66. When the CPU 66 receives the horizontal total dot detection end command, the CPU 66 saves the frequency division value data so as not to change, and sends the horizontal total dot detection end command to the comparator 65.
Send to PU66. Upon receiving the horizontal total dot detection end command, the comparator 65 deactivates the horizontal total dot detection signal (H level). As a result, the cursor control is stopped and the sampling clock adjustment is completed.

FIG. 9 shows signals of the respective parts of FIG. 2 when a video signal such that the left end of the screen becomes valid data is input.

When a video signal such that the left end of the screen becomes valid data is input, the timing conversion section 69
Stop cursor top left signal from is active (H level)
If it is, the horizontal video start count value is updated twice. That is, the horizontal video start count value is updated based on the cursor image at the upper left end and then updated again based on the valid data existing at the left end of the screen in the input video signal. Therefore, since the reference value determination signal is at the H level, 1024 is used as the reference value β.

The reason why the fine adjustment is performed after the subtraction result of the subtracter 64 matches the reference value β will be described below. Since the analog signal before sampling (A / D conversion) of the video signal has a rounded waveform, if the difference between the horizontal video start count value and the horizontal video end count value is valid data at the left end of the image, The number tends to be slightly larger than 1024 dots, and tends to be slightly larger than 1023 dots when there is no valid data at the left end of the image.

Then, even if the frequency of the sampling clock is correct, depending on the phase of the sampling clock based on the horizontal synchronizing signal, if there is valid data at the left end of the image, the horizontal video start count value and the horizontal video end count value can be obtained. It is considered that the difference from the value may be 1024 or 1025 when there is valid data at the left end of the image. Similarly, when there is no valid data at the left end of the image, it is considered that the difference between the horizontal video start count value and the horizontal video end count value may be 1023 or 1024.

Therefore, at the time of fine adjustment, when there is valid data at the left end of the image, the difference between the horizontal image start count value and the horizontal image end count value is 1024 or 102.
When it is 5, it is considered that the frequency of the sampling clock is appropriate. Similarly, when there is no valid data at the left end of the image, the difference between the horizontal video start count value and the horizontal video end count value is 1023 or 1 during fine adjustment.
When it is 024, it is considered that the frequency of the sampling clock is appropriate.

However, when there is valid data at the left end of the image, the phase of the sampling clock is changed when it is determined that the difference between the horizontal video start count value and the horizontal video end count value is 1025. ,
The difference between the horizontal image start count value and the horizontal image end count value may be 1026. Similarly, when there is valid data at the left end of the image, when it is determined that the difference between the horizontal video start count value and the horizontal video end count value is 1024, the phase of the sampling clock is changed. The difference between the 2 video start count value and the 2 video end count value may be 1025.

Therefore, when there is valid data at the left end of the image, after it is determined that the difference between the horizontal video start count value and the horizontal video end count value is 1024,
Change the phase of the sampling clock within a certain range,
Even if the difference between the horizontal image start count value and the horizontal image end count value is 1026, fine adjustment is performed so that the frequency of the sampling clock becomes small.

Similarly, when there is no valid data at the left end of the image, after it is determined that the difference between the horizontal video start count value and the horizontal video end count value is 1023,
Change the phase of the sampling clock within a certain range,
Even if the difference between the horizontal image start count value and the horizontal image end count value is 1025, fine adjustment is performed so that the frequency of the sampling clock becomes small.

[0084]

According to the present invention, when the sampling clock is adjusted for a plurality of types of video signals having a known number of horizontal effective dots and a different total number of horizontal dots, an appropriate sampling clock is obtained regardless of the input image. As a result, it becomes possible to display an appropriate video image for a plurality of types of video signals having a known horizontal effective dot number and different horizontal total dot numbers.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device.

FIG. 2 is a block diagram showing a configuration of a sampling clock adjustment circuit of FIG.

FIG. 3 is a schematic diagram showing a state in which a cursor is stopped at an upper left stop position.

FIG. 4 is an enlarged view of FIG.

FIG. 5 is a schematic diagram showing a state where the cursor is moved to the lower right corner.

FIG. 6 is a schematic diagram showing a state where the cursor is stopped at the lower right stop position.

FIG. 7 is an enlarged view of FIG.

FIG. 8 is a time chart showing signals of respective parts of FIG. 2 when a video signal such that the left end of the screen becomes valid data is not input.

FIG. 9 is a time chart showing signals of respective parts of FIG. 2 when a video signal such that the left end of the screen becomes valid data is input.

FIG. 10 is a timing chart showing two types of XGA video signals having different horizontal total dots.

[Explanation of symbols]

2R, 2G, 2B A / D converter 10 computers 40 Sampling clock adjustment circuit 50 PLL circuit 51 Phase detector 52 LPF 53 VCO 54 frequency divider 60 Horizontal total dot number detection circuit 61 Horizontal video start / end detection circuit 62 H counter 63 Maximum hold part 64 subtractor 65 comparator 66 CPU 67 Reference value determination unit 68 Cursor control section 69 Timing converter 70 Phase control circuit

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-10-63234 (JP, A) JP-A-10-11023 (JP, A) JP-A-11-202839 (JP, A) JP-A-10- 91127 (JP, A) JP 10-39838 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-5/42 H04N 5/66-5/74

Claims (4)

(57) [Claims] 1. A clock generation circuit for generating a sampling clock based on a horizontal synchronizing signal of an input video signal sent from a computer , and controlling the frequency of the sampling clock based on a given frequency control value. An A / D converter that samples an input video signal sent from a computer based on a sampling clock generated by a clock generation circuit, and the above computer when adjusting the sampling clock.
A first cursor control command is given to the cursor to move the cursor image included in the input image to a predetermined stop position on the left end side of the input image screen and stop for a predetermined period.
Cursor control and a second cursor control on the computer
Second cursor control for moving the cursor image included in the input image to a predetermined stop position on the right end side of the input image screen and stopping for a predetermined period by giving a command. Means for detecting horizontal image start position and horizontal image end position of the image data by comparing the image data output from the A / D converter with a predetermined threshold value; Every time the cursor control for one cycle consisting of and the second cursor control for one time is performed, among the horizontal image start positions detected in the state where the cursor image is stopped at the predetermined position on the left end side of the screen,
The horizontal sync signal of the horizontal video start position closest to the horizontal period start position specified by the horizontal sync signal and the horizontal video end position detected when the cursor video is stopped at the predetermined position on the right edge of the screen. Calculation means for calculating the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input video signal, based on the horizontal video end position farthest from the horizontal period start position specified by Every time one cycle of cursor control is performed, a determination unit that determines whether or not the calculation result by the calculation unit matches a given reference value, and the calculation result by the calculation unit does not match the reference value. When determined, a new value is calculated based on the calculation result of the calculation means, the reference value, and the frequency control value currently set in the clock generation circuit. When it is determined that the frequency control value adjusting means for calculating the wave number control value and giving it to the clock generating circuit and the calculation result by the calculating means and the reference value match, the frequency control value currently set in the clock generating circuit is appropriate. A display device having means for determining a proper frequency control value. 2. The clock generating circuit receives a VCO for outputting a sampling clock, a frequency dividing circuit for dividing the sampling clock output from the VCO, an output of the frequency dividing circuit and a horizontal synchronizing signal of the input video signal, The frequency division means of the frequency division circuit is provided with a phase detection means for outputting a detection signal according to the phase difference between the two input signals and a filter means for integrating the detection signal output from the phase detection means and outputting the integrated signal to the VCO. The display device according to claim 1, wherein is used as a frequency control value. 3. The frequency control value adjustment means calculates a new frequency division value by calculating {reference value × frequency division value currently set / calculation result by the calculation means}. Display device according to. Left side of the stop position of wherein cursor image is input
And from the upper left end of the force image screen is set to white pixels of the cursor image on the second pixel in the horizontal direction is positioned, the right end side of the stop position of the cursor image, the cursor image to the right end of the pixel of the input image screen After the horizontal image start position is detected based on the white pixels of the cursor image in the state where the white pixel of is set to the position and the cursor image is stopped at the predetermined position on the left end side of the input image screen. , When the horizontal video start position closer to the horizontal period start position specified by the horizontal sync signal is detected, the reference value is set to the number of effective horizontal dots of the input video signal, and the cursor video is on the left edge side of the input video screen. The horizontal period specified by the horizontal sync signal after the horizontal image start position is detected based on the white pixels of the cursor image when stopped at the predetermined position If the horizontal video start position is not detected closer to the start position, the reference value A display device according to claim 3 which is set to one less than the horizontal effective dots of the input video signal.