JP4017335B2 - Video signal valid period detection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an effective period detection circuit for a video signal used in a display device of a personal computer.
[0002]
[Prior art]
There are various signal formats such as the number of scanning lines, the number of pixels, and the frame frequency in the video signal of a personal computer, but the position of the effective period of the video signal (period to be displayed on the display device in the video signal) is also There are various. Therefore, when displaying an image, it is necessary to adjust the position of the display screen for each signal format of the input signal. Thus, conventionally, a device has been devised that automatically detects the effective period of the video signal and displays the video signal within the effective period at an appropriate position on the display device.
[0003]
FIG. 11 is a block diagram showing a display device using a conventional video signal valid period detection circuit. In FIG. 11, 1 is an AD conversion unit that converts a video signal into a digital signal, 2 is a PLL unit that generates a dot clock and a horizontal reference signal used in internal processing from the horizontal synchronization signal H1, and 4 is a horizontal reference signal and vertical synchronization. An address generating unit 5 for generating a horizontal address signal H2 and a vertical address signal V2 based on the signal V1 is an effective period detecting unit for detecting an effective period of the video signal. Here, the address generation unit 4 and the valid period detection unit 5 constitute a valid period detection circuit 6 for the video signal. Reference numeral 7 denotes a display unit. The display unit unit 7 displays the video signal on the display device based on the horizontal address signal H2, the vertical address signal V2, and the output signal of the valid period detection unit 5. In order to make the description easy to understand, in the following description, the display device of the display unit unit 7 is a matrix type having a total of 32 (= 8 × 4) pixels of 8 rows in the horizontal direction and 4 columns in the vertical direction. The case where it is a device will be described. Here, as a display device of the display unit section 7, there are a liquid crystal panel, PDP, DMD (digital micromirror device) and the like.
[0004]
Hereinafter, the operation of the display device of FIG. 11 will be described with reference to the timing chart of FIG. Here, FIGS. 12A and 12G are the input video signal S1, FIG. 12B is the input vertical synchronization signal V1, and FIGS. 12C and 12H are the input horizontal synchronization signal. H1 is shown. 12 (d) and 12 (i) are vertical address signals V2 output from the address generator 4, and FIGS. 12 (f) and 12 (l) are effective period detection flag signals used in the internal processing of the effective period detector 5. F1, FIG. 12 (j) shows the horizontal address signal H2. FIGS. 12 (g) to 12 (l) are partial enlargements of FIGS. 12 (a) to 12 (f) over time. In the following description, the horizontal synchronizing signal H1 and the vertical synchronizing signal V1 that are input have negative polarity as shown in FIGS. 12B and 12C, the falling edge is the leading edge, and the rising edge is the trailing edge. Will be described.
[0005]
A video signal S1 shown in FIGS. 12A and 12G is input to the AD converter 1. The AD conversion unit 1 converts the input video signal S1 into a digital signal and outputs the digital signal to the valid period detection unit 5 and the display unit unit 7.
[0006]
The PLL unit 2 generates a dot clock. The PLL unit 2 generates a horizontal reference signal by dividing the dot clock, and the falling edge of the horizontal reference signal and the falling edge of the horizontal synchronizing signal H1 shown in FIGS. The frequency of the dot clock is controlled so that. In general, the horizontal synchronization signal H1 and the horizontal reference signal have almost the same falling position, but the horizontal reference signal that is completely synchronized with the dot clock is used in the internal processing.
[0007]
As shown in FIG. 12D, the address generation unit 4 is reset at the falling edge of the vertical synchronization signal V1, and falls on the falling edge of the horizontal reference signal (matches the falling edge of the horizontal synchronization signal H1). The vertical address signal V2 is generated by a counter whose count value increases by 1. At the same time, as shown in FIG. 12 (j), the address generator 4 is reset at the falling edge of the horizontal reference signal, and generates a horizontal address signal H2 by a counter whose count value is incremented by 1 by the dot clock. To do. The horizontal address signal H2 and the vertical address signal V2 are used in the valid period detection unit 5 and the display unit unit 7 as address information representing the horizontal position and the vertical position on the screen.
[0008]
The effective period detection unit 5 compares the video signal S1 indicated by a solid line in FIGS. 12A and 12G with a predetermined threshold TH indicated by a broken line, and becomes high when the video signal S1 is equal to or greater than the threshold TH. Otherwise, the valid period detection flag signal F1 (FIGS. 12 (f) and (l)) that is low is generated. The predetermined threshold TH is set to about 1/8 of the maximum amplitude of the video signal S1. Further, the effective period detection unit 5 sets the value of the minimum horizontal address signal H2 (“5” in FIG. 12J) with the effective period detection flag signal F1 being high to the left end coordinate and the maximum value (FIG. “12”) in j) is output to the display unit 7 as the right end coordinate. Also, the minimum vertical address signal V2 value (“4” in FIG. 12D) when the valid period detection flag signal F1 is high and the maximum vertical address signal V2 value (in FIG. 12D). "7") is output to the display unit section 7 as the upper end coordinates and the lower end coordinates, respectively.
[0009]
The display unit unit 7 is based on the left end, right end, upper end, and lower end coordinates input from the valid period detection unit 5 and the horizontal address signal H2 and the vertical address signal V2 input from the address generation unit 4, and the video signal S1. Is displayed at an appropriate position on the display device. In the following description, for the sake of convenience, the value H of the horizontal address signal H2 and the value V of the vertical address signal V2 are expressed in the form (H, V). Here, H and V are positive integers.
[0010]
For example, when the left end coordinate is “5”, the right end coordinate is “12”, the upper end coordinate is “4”, and the lower end coordinate is “7”, the horizontal address signal H2 and the vertical address signal V2 are at timings (5, 4). The input video signal is displayed on the upper left pixel. A video signal in which the horizontal address signal H2 and the vertical address signal V2 are input at the timing (6, 4) is displayed as a video signal in which the horizontal address signal H2 and the vertical address signal V2 are input at the timing (5, 4). It is displayed on the pixel right next to the selected pixel. FIG. 13 shows the relationship between the position on the display device and the values of the horizontal address signal H2 and the vertical address signal V2.
[0011]
In the operation of the above-mentioned video signal effective period detection circuit, it is assumed that there are always video signals exceeding the threshold value at the upper, lower, left and right ends of the effective period. When an operating system having an interface is used, there are many cases where the video signal exists until the end of the effective period of the video signal, and there is no problem in practical use.
[0012]
[Problems to be solved by the invention]
Since the above-described conventional video signal valid period detection circuit is configured as described above, the valid period may not be detected correctly due to the influence of crosstalk noise mixed on the cable transmitting the video signal. There was a problem.
[0013]
The operation of the conventional video signal effective period detection circuit when the crosstalk noise CN of the horizontal synchronization signal H1 is mixed in the video signal will be described with reference to FIG.
[0014]
FIG. 14A shows the state of the video signal S1 when the crosstalk noise CN of the horizontal synchronization signal H1 is mixed, and ringing noise is mixed in the portion where the horizontal synchronization signal H1 has changed. . When such a video signal S1 is input to the effective period detection unit 5, the crosstalk noise CN equal to or higher than the threshold TH indicated by the broken line is detected as an effective period, and the effective period detection flag signal F1 is shown in FIG. 14 (e). Accordingly, the minimum horizontal address signal H2 with the valid period detection flag signal F1 being high is “1” as shown in FIG. 14D, which is shifted by 4 pixels from the correct value “5”. The left end coordinate. Since the display unit unit 7 controls to display the pixel at the left end coordinate at the left end, the display unit 7 displays as shown in FIG. In FIG. 15, the pixels in the left four columns indicated by the dotted lines are inactive period images.
[0015]
As described above, in the above-described conventional video signal effective period detection circuit, there is a crosstalk noise CN on the cable transmitting the video signal S1 and the like in which the change of the synchronization signal is superimposed on the video signal. However, there is a problem that the valid period cannot be detected correctly and the position of the screen display is shifted.
[0016]
Therefore, the present invention has been made to solve the above-described problems of the prior art, and the object of the present invention is to superimpose the change of the synchronization signal on the video signal on a cable for transmitting the video signal. It is an object of the present invention to provide a video signal valid period detection circuit capable of accurately detecting a valid period even when crosstalk noise is generated.
[0017]
[Means for Solving the Problems]
The valid period detection circuit for a video signal according to claim 1 is a first level in a first period and a first level for the first period, and a second level in the other period, and a second level A period to be displayed on the display device in the video signal based on the horizontal synchronization signal and the video signal which are the fourth level in the period and the third level only in the second period. In the valid period detection circuit of the video signal for detecting the first detection non-permission period and the horizontal synchronization signal of a predetermined length set so as to include a time point when the vertical synchronization signal changes its level, the level changes The detection is at the fifth level in the period belonging to at least one of the second detection non-permission periods having a predetermined length set to include the time point to be detected, and at the sixth level in the other periods Generate region window signal A detection window signal generation unit, and an effective period detection unit that outputs a period in which the level of the video signal is equal to or higher than a predetermined threshold and the detection area window signal is at the sixth level as an effective period. It is characterized by.
[0018]
According to a second aspect of the present invention, there is provided a video signal valid period detection circuit that is at a first level for the first period in the first period, and is at a second level for the other periods. The second level is the third level for the second period and the other periods are displayed on the display device in the video signal based on the horizontal synchronization signal and the video signal which are the fourth level. In the valid period detection circuit of the video signal for detecting the power period, the first detection non-permission period and the horizontal synchronization signal having a predetermined length set so as to include a time point at which the vertical synchronization signal changes its level In the period belonging to at least one of the second detection non-permission periods of a predetermined length set so as to include the time point at which the change is made, it is the fifth level, and in the other periods it is the sixth level Certain detection window signal A detection window signal generation unit to generate, and when the detection area window signal is at a sixth level, the video signal is passed, and when the detection area window signal is at a fifth level, the level of the video signal is set to zero level And a valid period detector that outputs as a valid period a period in which the level of the output signal of the gate section is equal to or higher than a predetermined threshold value.
[0019]
In the video signal valid period detection circuit according to the third aspect, the first detection non-permission period starts when the vertical synchronization signal changes from the second level to the first level, and immediately thereafter This is a period that ends when a predetermined time elapses from the time when the synchronization signal returns from the first level to the second level. The second detection non-permission period is a period when the horizontal synchronization signal is changed from the fourth level to the third level. The period starts at the time when the level changes, and ends immediately after a predetermined time has elapsed from the time when the horizontal synchronization signal returns from the third level to the fourth level.
[0020]
The video signal effective period detection circuit according to claim 4 measures the first period in which the vertical synchronization signal is at the first level and the second period in which the horizontal synchronization signal is at the third level. The first detection non-permission period starts at a time when the vertical synchronization signal changes from the second level to the first level, and then, for a predetermined time in the first period. The second detection non-permission period starts when the horizontal synchronization signal changes from the fourth level to the third level, and then the second detection non-permission period. This is a period that ends when a time obtained by adding a predetermined time to this period elapses.
[0021]
In the video signal valid period detection circuit according to claim 5, the first detection non-permission period starts at a first time point when the vertical synchronization signal changes from the second level to the first level. A period that ends when a predetermined time elapses from the first time point, and a second time point when the vertical synchronization signal changes from the first level to the second level, and a predetermined time period elapses from this second time point The second detection non-permission period starts at the third time point when the horizontal synchronization signal changes from the fourth level to the third level, and a predetermined time elapses from the third time point. And a period that ends when the horizontal synchronization signal changes from the third level to the fourth level and ends when a predetermined time has elapsed from the fourth time point. It is characterized by.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
FIG. 1 is a block diagram showing a configuration of a display device using a video signal valid period detection circuit according to Embodiment 1 of the present invention. In FIG. 1, 1 is an AD conversion unit that converts a video signal S1 into a digital signal, 2 is a PLL unit that generates a dot clock and a horizontal reference signal used in internal processing from the horizontal synchronization signal H1, and 3 is an effective video signal S1. When detecting the period, a detection area window signal generator 4 for generating a detection area window signal D1, which is a control signal for prohibiting detection at a predetermined timing, 4 is a horizontal address signal based on the horizontal reference signal and the vertical synchronization signal V1. An address generation unit 5 that generates H2 and the vertical address signal V2 is an effective period detection unit that detects an effective period of the video signal S1. Here, the detection area window signal generation unit 3, the address generation unit 4, and the effective period detection unit 5 constitute a video signal effective period detection circuit 6. Reference numeral 7 denotes a display unit portion including a display device such as a liquid crystal panel or a PDP. The display unit unit 7 displays the video signal S1 on the display device based on the horizontal address signal H2, the vertical address signal V2, and the output signal of the effective period detection unit. In order to make the description easy to understand, in the following description, the display device of the display unit unit 7 is a matrix type device having a total of 32 (= 8 × 4) pixels of 8 rows in the horizontal direction and 4 columns in the vertical direction. The case where it is is demonstrated.
[0023]
Hereinafter, the operation of the display device of FIG. 1 will be described with reference to the timing chart of FIG. FIG. 2 shows the timing of each part of the display device using the video signal valid period detection circuit according to the first embodiment. 2A and 2G show the input video signal S1, FIG. 2B shows the input vertical synchronization signal V1, and FIGS. 2C and 2H show the input horizontal synchronization signal. H1. 2 (d) and 2 (i) show the vertical address signal V2 output from the address generator 4, and FIGS. 2 (e) and 2 (k) show the detection area window signal D1, and FIGS. 2 (f) and (l). ) Is a valid period detection flag signal F1 used in the internal processing of the valid period detection unit 5, and FIG. 2 (j) is a horizontal address signal H2. 2 (g) to (l) are parts of FIGS. 2 (a) to (f) enlarged in time. In the following description, the input horizontal synchronization signal H1 and vertical synchronization signal V1 have negative polarity, and the falling edge means the leading edge and the rising edge means the trailing edge.
[0024]
A video signal S1 shown in FIGS. 2A and 2G is input to the AD converter 1. The AD conversion unit 1 converts the video signal S1 into a digital signal and outputs the digital signal to the valid period detection unit 5 and the display unit unit 7.
[0025]
The PLL unit 2 generates a dot clock, and divides the dot clock to generate a horizontal reference signal. The falling edge of the horizontal reference signal and the falling edge of the input horizontal synchronization signal H1 The dot clock frequency is controlled so that the edges coincide.
[0026]
As shown in FIG. 2D, the address generation unit 4 is reset at the falling edge of the vertical synchronization signal V1, and at the falling edge of the horizontal reference signal (matches the falling edge of the horizontal synchronization signal H1). A vertical address signal V2 is generated by a counter whose count value increases by one. At the same time, as shown in FIG. 2 (j), the horizontal address signal H2 is generated by a counter which is reset at the falling edge of the horizontal reference signal and whose count value is incremented by 1 by the dot clock. The horizontal address signal H2 and the vertical address signal V2 are used in the valid period detection unit 5 and the display unit unit 7 as address information representing the horizontal position and the vertical position on the screen.
[0027]
As shown in FIGS. 3A to 3C, the detection area window signal generator 3 goes low at the falling edge of the horizontal reference signal and goes high at a position delayed by a predetermined time tp from the rising edge. A signal A is generated. The predetermined time tp is set to a time when the superimposed noise attenuates and becomes negligible when noise is superimposed on the video signal due to crosstalk at the rising edge of the horizontal synchronization signal H1. The predetermined time tp depends on the level of the crosstalk noise CN, and is determined in advance assuming the worst state in consideration of the circuit configuration of the display device. The predetermined time tp can also be determined based on experiments.
[0028]
Further, as shown in FIG. 4, the detection area window signal generation unit 3 generates a signal B that goes low at the falling edge of the vertical synchronization signal V1 and goes high at a position delayed by a predetermined time tp from the rising edge. The detection area window signal D1 is generated by the logical product of the signals A and B.
[0029]
The effective period detection unit 5 compares the video signal S1 indicated by the solid line in FIG. 2A or 2G with a predetermined threshold TH indicated by the broken line. The effective period detection unit 5 becomes high when the video signal S1 is equal to or higher than the threshold value TH and the detection area window signal D1 is high, and becomes low otherwise, as shown in FIG. ) And (l)). The predetermined threshold TH is set to about 1/8 of the maximum amplitude of the video signal S1. Thus, by using the video region window signal for detection of the effective period, it is possible to exclude the influence of the crosstalk noise CN mixed in the video signal S1 from the horizontal synchronizing signal H1 or the vertical synchronizing signal V1. Further, the valid period detection unit 5 displays a signal having the minimum horizontal address signal H2 with the valid period detection flag signal F1 being high as the value at the left end coordinate and the maximum value as the value at the right end coordinate. 7 is output. Further, the display unit unit 7 is supplied with a signal having the minimum vertical address signal V2 in the high state of the valid period detection flag signal F1 as the value at the upper end coordinate and the maximum vertical address signal V2 as the value at the lower end coordinate. Output.
[0030]
The display unit unit 7 outputs a video signal based on the left end, right end, upper end, and lower end coordinates input from the valid period detection unit 5 and the horizontal address signal H2 and the vertical address signal V2 input from the address generation unit 4. Display at the appropriate position on the display device. For example, when the left end coordinate is “5”, the right end coordinate is “12”, the upper end coordinate is “4”, and the lower end coordinate is “7”, the horizontal and vertical addresses are input at the timing of (5, 4). The video signal is displayed in the upper left pixel, and the video signal input at the timing of the horizontal and vertical addresses (6, 4) is displayed in the right adjacent pixel. FIG. 5 shows the relationship between the position on the display device and the horizontal and vertical addresses.
[0031]
As described above, when the video signal effective period detection circuit according to the first embodiment is used, the video signal S1 is not affected by the noise component mixed by the crosstalk from the horizontal synchronization signal H1 or the vertical synchronization signal V1. The valid period of the video signal can be accurately detected.
[0032]
In the video signal valid period detection circuit according to the first embodiment, the detection area window signal D1 is generated with reference to both the leading edge (falling edge) and the trailing edge (rising edge) of the horizontal and vertical synchronizing signal V1. However, the present invention is not limited to this, and the time width of the active period (from the leading edge to the trailing edge) of the synchronization signal is measured, and the measured time width is measured from the leading edge of the synchronization signal. The detection area window signal D1 may be generated so as to be low until + tp.
[0033]
Embodiment 2
FIG. 6 is a block diagram showing a display device using a video signal valid period detection circuit according to Embodiment 2 of the present invention. In FIG. 6, 1 is an AD conversion unit, 2 is a PLL unit, 3 is a detection area window signal generation unit, 8 is a synchronization signal period measurement unit that measures active periods of the horizontal synchronization signal H1 and the vertical synchronization signal V1, and 4 is An address generation unit 5 is a valid period detection unit. Here, the detection area window signal generation unit 3, the synchronization signal period measurement unit 8, the address generation unit 4, and the effective period detection unit 5 constitute a video signal effective period detection circuit 6. Reference numeral 7 denotes a display unit portion including a display device such as a liquid crystal panel or a PDP.
[0034]
Hereinafter, the operation of the display device of FIG. 6 will be described with reference to the timing chart of FIG. FIG. 7 shows the timing of each part of the display device using the effective period detection circuit for video signals according to the second embodiment. 7A shows the input video signal S1, FIG. 7B shows the input horizontal synchronization signal H1, FIG. 7C shows the vertical address signal V2 output from the address generator 4, and FIG. (D) is a horizontal address signal H2, FIG. 7 (e) is a detection area window signal D1, and FIG. 7 (f) is an effective period detection flag signal F1 used in the internal processing of the effective period detection unit 5.
[0035]
The synchronization signal period measurement unit 8 includes a horizontal synchronization period measurement circuit and a vertical synchronization period measurement circuit. The time from the leading edge to the trailing edge of the horizontal synchronization signal H1, and the leading edge to the trailing edge of the vertical synchronization signal V1, respectively. The time to the edge is measured and output to the detection area window signal generation unit 3 as information on the width of the period in which the horizontal synchronizing signal H1 is low and the width of the period in which the vertical synchronizing signal V1 is low.
[0036]
The detection area window signal generation unit 3 goes low at the falling edge of the horizontal reference signal (corresponding to the falling edge of the horizontal synchronization signal H1), and adds the time tp to the width of the period during which the horizontal synchronization signal H1 is low. A signal that goes high after the lapse of time, and a signal that goes low at the falling edge of the vertical synchronization signal V1 and goes high after the lapse of time tp the width of the period in which the vertical synchronization signal V1 is low. A detection area window signal D1 (FIG. 7E) is generated by logical product.
[0037]
Thereafter, as in the first embodiment, using the detection area window signal D1, the valid period detector 5 detects the valid period of the video signal S1 excluding the crosstalk noise CN, and the display unit section. 7 displays the video of the effective period at an appropriate position of the display device based on the detection result of the effective period detection unit 5.
[0038]
As described above, by using the video signal valid period detection circuit according to the second embodiment, the video signal S1 is not affected by the noise component mixed by the crosstalk from the horizontal synchronization signal H1 and the vertical synchronization signal V1. It is possible to accurately detect the effective period of the video signal.
[0039]
In the first and second embodiments, the detection of the valid period from the falling position of the synchronization signal to the vicinity of the rising position is prohibited. However, the present invention is not limited to this, and only the changed vicinity is prohibited. You may make it do.
[0040]
Embodiment 3
Since the block diagram of the display device using the video signal valid period detection circuit according to the third embodiment is the same as that of the first embodiment, FIG. 1 is also referred to in the description of the third embodiment. The video signal valid period detection circuit according to the third embodiment is different from that of the first embodiment only in the operation of the detection area window signal generation unit 3.
[0041]
FIG. 8 is a timing chart of each part of the display device using the video signal valid period detection circuit according to the third embodiment. FIG. 8A shows an input video signal S1, and FIG. 8B shows an input horizontal synchronization signal H1. 8C shows the vertical address signal V2 output from the address generator 4, FIG. 8D shows the horizontal address signal H2, FIG. 8E shows the detection area window signal D1, and FIG. ) Is an effective period detection flag signal F1 used in the internal processing of the effective period detection unit 5. The signals other than the detection area window signal D1 shown in FIG. 8E are the same as those in the first embodiment shown in FIG.
[0042]
The detection area window signal generation unit 3 becomes low when the horizontal synchronizing signal H1 or the vertical synchronizing signal V1 falls, and becomes high when delayed by time tp from the falling. Further, a detection region window signal D1 (FIG. 8 (e)) that becomes low again at the rising edge of the horizontal synchronizing signal H1 or the vertical synchronizing signal V1 and becomes high when delayed by time tp from the rising edge is generated.
[0043]
This detection area window signal D1 is used for detection of the effective period in the effective period detection unit 5 as in the first embodiment. Thereafter, the process is the same as in the first embodiment until the video signal S1 is displayed on the display unit unit 7.
[0044]
As described above, when the effective period detection circuit for video signals according to the third embodiment is used, even if the detection of the effective period is prohibited only at the position where the synchronization signal is changed, the influence of the crosstalk noise CN is affected. The effective period of the video signal can be accurately detected.
[0045]
In the first, second, and third embodiments, the detection area is designated by the detection area window signal D1 for the comparison result between the video signal S1 and the threshold value TH. However, the present invention is not limited to this method. Alternatively, the video signal S1 may be gated with the detection area window signal D1 and then compared with the threshold value TH.
[0046]
Embodiment 4
FIG. 9 is a block diagram showing a display device using a video signal valid period detection circuit according to Embodiment 4 of the present invention. In FIG. 9, 1 is an AD conversion unit, 2 is a PLL unit, 3 is a detection area window signal generation unit, 4 is an address generation unit, and 9 is a gate that passes and does not pass a video signal using the detection area window signal D1 as a control signal. Reference numerals 5 and 5 denote effective period detection units. Here, the detection area window signal generation unit 3, the address generation unit 4, the gate unit 9, and the effective period detection unit 5 constitute a video signal effective period detection circuit 6. Reference numeral 7 denotes a display unit.
[0047]
Hereinafter, the operation of the display device of FIG. 9 will be described with reference to the timing chart of FIG. FIG. 10 shows input / output signals of the gate unit 9. 10A shows a video signal S1 that is an input signal from the AD conversion unit 1, and FIG. 10B shows a detection region window signal D1 that is an input signal from the detection region window signal generation unit 3. FIG. 10C shows an output signal from the gate unit 9.
[0048]
As in the first embodiment, the detection area window signal generation unit 3 generates a detection area window signal D1. As shown in FIG. 10, the gate unit 9 outputs the input video signal S1 as it is when the detection area window signal D1 is high, and outputs zero when it is low. Here, “zero” means black of the video signal. Thereby, the noise superimposed by the crosstalk of the horizontal synchronizing signal H1 and the vertical synchronizing signal V1 is removed.
[0049]
The output signal of the gate unit 9 is input to the valid period detection unit 5. The valid period detection unit 5 compares the video signal processed by the gate unit 9 with a predetermined threshold TH, and generates a valid period detection flag signal F1 that is high when the video signal is equal to or higher than the threshold TH and low otherwise. To do. Furthermore, a signal having the minimum horizontal address signal H2 with the valid period detection flag signal F1 being high as the value at the left end coordinate and the maximum value at the right end coordinate is output to the display unit section 7. Further, the display unit unit 7 is supplied with a signal having the minimum vertical address signal V2 in the high state of the valid period detection flag signal F1 as the value at the upper end coordinate and the maximum vertical address signal V2 as the value at the lower end coordinate. Output.
[0050]
Thereafter, as in the first embodiment, the display unit 7 displays video signals from the left end, right end, upper end, and lower end coordinates, and the horizontal address signal H2 and the vertical address signal V2 input from the address generator 4. Controlled to display at the appropriate location on the device.
[0051]
As described above, by using the video signal valid period detection circuit according to the fourth embodiment, the influence of the crosstalk noise CN can be eliminated, and the valid period of the video signal can be accurately detected. .
[0052]
In the first to fourth embodiments, the detection result of the valid period detection circuit is used to control the position of the screen. However, the present invention is not limited to this, and sampling of one line is performed. It may be used as data for obtaining a number. For example, when an XGA signal having an effective period of 1024 pixels in the horizontal direction and 768 lines in the vertical direction is input, the division of the PLL unit is determined so that the sampling number of one line is determined so that the width of the detected effective period is 1024. The frequency may be determined.
[0053]
The effective period detection circuit according to the present invention is not limited to a matrix type display device such as a liquid crystal panel, PDP, DLP (Digital Light Processing), FED, EL, etc., but can be applied to any display device that requires screen position adjustment. .
[0054]
【The invention's effect】
As described above, according to the effective period detection circuit of the video signal according to claims 1 to 5, the effective period is not detected in the vicinity of the change in the horizontal synchronizing signal and the vertical synchronizing signal. It is possible to eliminate the influence of crosstalk noise caused by mixing the synchronization signal into the video signal, and as a result, it is possible to accurately detect the effective period.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a display device using a video signal valid period detection circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of each part of the video signal valid period detection circuit according to the first embodiment;
3 is a timing chart for explaining the operation of the detection area window signal generation unit of FIG. 1; FIG.
4 is a timing chart for explaining the operation of the detection area window signal generation unit of FIG. 1; FIG.
5 is a diagram showing a screen display state of the display device of FIG. 1; FIG.
FIG. 6 is a block diagram showing a configuration of a display device using an effective period detection circuit according to a second embodiment of the present invention.
FIG. 7 is a timing chart for explaining the operation of each part of the video signal valid period detection circuit according to the second embodiment;
FIG. 8 is a timing chart for explaining the operation of each part of the display device using the effective period detection circuit according to the third embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a display device using an effective period detection circuit according to a fourth embodiment of the present invention.
10 is a timing chart for explaining the operation of the gate unit of FIG. 9;
FIG. 11 is a block diagram illustrating a configuration of a display device using a conventional video signal valid period detection circuit.
FIG. 12 is a timing chart for explaining the operation of each part of a conventional video signal valid period detection circuit;
13 is a diagram showing a screen display state of the display device of FIG.
FIG. 14 is a timing chart for explaining the operation of each part of a conventional video signal valid period detection circuit;
15 is a diagram showing a screen display state of the display device of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 AD conversion part, 2 PLL part, 3 Detection area window signal generation part, 4 Address generation part, 5 Effective period detection part, 6 Effective period detection circuit, 7 Display unit part, 8 Synchronization signal period measurement part, 9 Gate part

Claims (5)

The first level is the first level only for the first period in the first period, and the other period is the third level for the second period and the vertical synchronization signal that is the second level in the second period, In the video signal effective period detection circuit for detecting the period to be displayed on the display device in the video signal based on the horizontal synchronization signal which is the fourth level and the video signal during the other period,
A first detection disapproval period of a predetermined length set to include a time point at which the vertical synchronization signal changes its level and a predetermined length set to include a time point at which the horizontal synchronization signal changes its level A detection window signal generation unit that generates a detection area window signal that is a fifth level in a period belonging to at least one of the second detection non-permission periods and a sixth level in other periods; ,
An effective period detector that outputs a period in which the level of the video signal is equal to or higher than a predetermined threshold and the detection area window signal is at a sixth level as an effective period. Period detection circuit. The first level is the first level only for the first period in the first period, and the other period is the third level for the second period and the vertical synchronization signal that is the second level in the second period, In the video signal effective period detection circuit for detecting the period to be displayed on the display device in the video signal based on the horizontal synchronization signal which is the fourth level and the video signal during the other period,
A first detection disapproval period of a predetermined length set to include a time point at which the vertical synchronization signal changes its level and a predetermined length set to include a time point at which the horizontal synchronization signal changes its level A detection window signal generation unit that generates a detection area window signal that is a fifth level in a period belonging to at least one of the second detection non-permission periods and a sixth level in other periods; ,
A gate section that passes the video signal when the detection area window signal is at the sixth level and outputs the video signal at a zero level when the detection area window signal is at the fifth level;
A valid period detecting circuit for a video signal, comprising: a valid period detecting section that outputs a period in which a level of an output signal of the gate section is equal to or greater than a predetermined threshold as a valid period. The first detection non-permission period starts when the vertical synchronization signal changes from the second level to the first level, and immediately after that when the vertical synchronization signal returns from the first level to the second level. It is a period that ends when a predetermined time has elapsed,
The second detection non-permission period starts when the horizontal synchronization signal changes from the fourth level to the third level, and immediately after the horizontal synchronization signal returns from the third level to the fourth level. 3. The video signal valid period detection circuit according to claim 1, wherein the period ends when a predetermined time elapses. A synchronization signal period measuring unit that measures the first period in which the vertical synchronization signal is at the first level and the second period in which the horizontal synchronization signal is at the third level;
The first detection disapproval period starts when the vertical synchronization signal changes from the second level to the first level, and then ends when a time obtained by adding a predetermined time to the first period elapses. Is a period to
The second detection disapproval period starts when the horizontal synchronization signal changes from the fourth level to the third level, and then ends when a time obtained by adding a predetermined time to the second period elapses. 3. The video signal valid period detection circuit according to claim 1, wherein the period is a period during which the video signal is valid. The first detection non-permission period starts at a first time point when the vertical synchronization signal changes from the second level to the first level, and ends when a predetermined time has elapsed from the first time point, and A period starting from a second time point when the vertical synchronization signal changes from the first level to the second level and ending when a predetermined time elapses from the second time point,
The second detection non-permission period begins at a third time point when the horizontal synchronization signal changes from the fourth level to the third level, and ends when a predetermined time has elapsed from the third time point, and 2. The method according to claim 1, further comprising a period starting at a fourth time point when the horizontal synchronizing signal changes from the third level to the fourth level and ending when a predetermined time elapses from the fourth time point. 3. An effective period detection circuit for a video signal according to any one of 2 above.

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