JP4239475B2 - Scanning line converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a scanning line conversion apparatus in an electronic apparatus centering on a liquid crystal display.
[0002]
[Prior art]
Conventionally, a scanning line conversion apparatus described in Japanese Patent Laid-Open No. 9-247574 has been known. FIG. 4 shows the structure of a conventional scanning line conversion apparatus.
[0003]
A synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from an input signal; a first PLL circuit that generates a first clock in synchronization with a horizontal synchronization signal that is an output of the synchronization separation circuit; and the horizontal synchronization A second PLL circuit that generates a second clock in synchronization with the signal, a scanning line conversion circuit for converting the scanning line of the input signal, and horizontal and vertical interpolation in the scanning line conversion circuit For generating interpolation timing and interpolation coefficients for generating a horizontal synchronizing signal having a plurality of horizontal frequencies after conversion of the scanning line, and a memory for converting the frame frequency of the output of the scanning line conversion circuit The clock and the synchronization signal are selected so that the frame before conversion and the frame after conversion have an integer ratio.
[0004]
[Problems to be solved by the invention]
As described above, when scanning line conversion is performed, horizontal synchronization signals having a plurality of horizontal frequencies after scanning line conversion are generated, so that the number of counters is required and the circuit scale becomes large. It was.
[0005]
Also, when there are a plurality of horizontal sync signal frequencies after scanning line conversion, depending on the liquid crystal panel, even if one of the multiple horizontal sync signals becomes shorter than the spec of the horizontal sync signal of the liquid crystal panel, it cannot be displayed. There was a problem.
[0006]
[Means for Solving the Problems]
In order to solve this problem, the present invention provides an A / D converter that converts an input signal into a digital video signal, a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the input signal, and the synchronization separation circuit. A first PLL circuit that generates a first clock in synchronization with a horizontal synchronizing signal that is output from the first, and a first frequency divider that controls the oscillation frequency of the first clock that is the output of the first PLL circuit A counter, a second PLL circuit that generates a second clock in synchronization with the horizontal synchronizing signal, and a second frequency dividing counter that controls the oscillation frequency of the second clock that is the output of the second PLL circuit A horizontal processing timing generation circuit for generating an interpolation coefficient and interpolation timing used for interpolation calculation when converting the number of dots in the horizontal direction of the input signal, and an output from the horizontal processing timing generation circuit. A horizontal processing circuit that performs an interpolation calculation based on the interpolation coefficient and the interpolation timing, a memory that writes the data after the interpolation calculation, which is an output of the horizontal processing circuit, with a first clock, and a scanning line conversion A vertical processing timing generation circuit for generating an interpolation coefficient and interpolation timing used for vertical interpolation calculation from the subsequent horizontal synchronization signal, and an interpolation calculation in the vertical direction from the interpolation coefficient and interpolation timing output from the vertical processing timing generation circuit. A frequency dividing counter that operates with a second clock that is an output of the second PLL circuit and resets with a vertical synchronization signal that is an output of the synchronization separation circuit. Thus, a horizontal counter 1 is provided which generates a horizontal synchronizing signal after scanning line conversion shorter by the last 1H in one frame. It is intended.
[0007]
In view of the above problems, the present invention provides a scanning line conversion device that converts the number of scanning lines of an input signal in accordance with a display device, and performs scanning line conversion with only one horizontal counter of a horizontal synchronizing signal generation circuit after scanning line conversion. A scanning line conversion device having a small circuit scale is provided so as to be possible.
[0008]
It is another object of the present invention to provide a scanning line conversion device capable of displaying without problems on a liquid crystal panel in which all horizontal period signals in one frame after the scanning line conversion must always be 1H period or more according to the specifications of the liquid crystal panel. .
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is a scanning line conversion device that converts the number of scanning lines of an input signal according to a display device, and forcibly resets a horizontal timing generation circuit after the scanning line conversion by a vertical synchronization signal, so that the last 1 of one frame is converted. A scanning line conversion apparatus characterized in that the number of dots in a line is shorter than that of other lines, so that the scanning line conversion can be performed with only one horizontal counter of the horizontal synchronizing signal generation circuit after the scanning line conversion. Thus, the scanning line conversion is possible with a small circuit scale.
[0010]
The present invention also provides an A / D converter that converts an input signal into a digital video signal, a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the input signal, and a horizontal output that is an output from the synchronization separation circuit. A first PLL circuit that generates a first clock in synchronization with a synchronization signal; a first frequency division counter that controls an oscillation frequency of a first clock that is an output of the first PLL circuit; and the horizontal synchronization A second PLL circuit that generates a second clock in synchronization with the signal, a second frequency dividing counter that controls the oscillation frequency of the second clock that is an output of the second PLL circuit, and A horizontal processing timing generation circuit that generates an interpolation coefficient and interpolation timing used for interpolation when converting the number of dots in the horizontal direction, and an interpolation coefficient that is an output from the horizontal processing timing generation circuit is complemented. A horizontal processing circuit that performs interpolation calculation from timing, a memory that writes data after interpolation calculation, which is an output of the horizontal processing circuit, with a first clock, and that is read with a second clock, and a vertical synchronization signal after scanning line conversion. A vertical processing timing generation circuit for generating an interpolation coefficient and interpolation timing for use in a direction interpolation calculation, and a vertical processing for performing an interpolation calculation in the vertical direction from the interpolation coefficient and interpolation timing output from the vertical processing timing generation circuit. A scanning line conversion device that operates with a second clock that is an output of the second PLL circuit and resets with a vertical synchronization signal that is an output of the synchronization separation circuit; A scanning line converter characterized by comprising a horizontal counter 1 for generating a horizontal synchronizing signal of 1 mm shorter by the last 1H in one frame. It is those, such an action may scanning line conversion with a small circuit scale.
[0011]
The present invention is also a scanning line conversion device for converting the number of scanning lines of an input signal in accordance with a display device, and by making the number of dots of one final line of one frame longer than other lines, The scanning line conversion device is characterized in that it corresponds to a liquid crystal panel in which all the horizontal periods must always be 1H period or more according to the specifications of the liquid crystal panel, and all the horizontal period signals in one frame are It has the effect that it can be displayed without any problem on the liquid crystal panel which must always be 1H cycle or more on the specifications of the liquid crystal panel.
[0012]
The present invention also provides an A / D converter that converts an input signal into a digital video signal, a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the input signal, and a horizontal output that is an output from the synchronization separation circuit. A first PLL circuit that generates a first clock in synchronization with a synchronization signal; a first frequency division counter that controls an oscillation frequency of a first clock that is an output of the first PLL circuit; and the horizontal synchronization A second PLL circuit that generates a second clock in synchronization with the signal, a second frequency dividing counter that controls the oscillation frequency of the second clock that is an output of the second PLL circuit, and A horizontal processing timing generation circuit that generates an interpolation coefficient and interpolation timing used for interpolation when converting the number of dots in the horizontal direction, and an interpolation coefficient that is an output from the horizontal processing timing generation circuit is complemented. A horizontal processing circuit that performs interpolation calculation from timing, a memory that writes data after interpolation calculation, which is an output of the horizontal processing circuit, with a first clock, and that is read with a second clock, and a vertical synchronization signal after scanning line conversion. A vertical processing timing generation circuit for generating an interpolation coefficient and interpolation timing for use in a direction interpolation calculation, and a vertical processing for performing an interpolation calculation in the vertical direction from the interpolation coefficient and interpolation timing output from the vertical processing timing generation circuit. A scanning line converter, which operates with a second clock that is an output of the second PLL circuit, and a frequency dividing counter that resets only an initial value with a vertical synchronization signal that is an output of the synchronization separation circuit, A scanning line change characterized by comprising a horizontal counter 2 for generating a horizontal synchronizing signal after the scanning line conversion by a length of 1H last in one frame. It is obtained by a device, an effect that can be displayed without any problem on the liquid crystal panel every horizontal period signal in one frame must necessarily 1H period or more.
[0013]
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
[0014]
(Embodiment 1)
FIG. 1 shows an example of a scanning line conversion apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an A / D converter that converts an analog signal into a digital signal, and 2 denotes a vertical sync signal from an input signal to a horizontal synchronizing signal. A synchronization separation circuit that separates the synchronization signals, 3 is a PLL circuit 1 that generates a first clock in synchronization with a horizontal synchronization signal that is an output of the synchronization separation circuit, and 4 is an amount that controls the oscillation frequency of the PLL circuit 1. Numeral counters 1 and 5 are horizontal processing circuits that perform interpolation processing when converting the number of horizontal dots, and 6 is a horizontal processing timing generation circuit that generates interpolation coefficients and interpolation timings used for the horizontal interpolation processing.
[0015]
Reference numeral 7 denotes a memory for writing with the first clock and conversion with respect to the horizontal synchronization signal by reading with the second clock. Reference numeral 8 denotes a PLL circuit for generating the second clock in synchronization with the horizontal synchronization signal which is the output of the synchronization separation circuit. 2 and 9 are frequency dividing counters 2 and 10 for controlling the oscillation frequency of the PLL circuit 2, 10 is a vertical processing circuit for performing interpolation in the vertical direction with respect to the data after scanning line conversion which is an output from the memory, and 11 is the vertical processing circuit. A vertical processing timing generation circuit 12 for generating an interpolation coefficient and interpolation timing used in the processing circuit is constituted by a horizontal counter circuit which operates with a second clock and generates a horizontal synchronizing signal after scanning line conversion.
[0016]
FIG. 2 is an internal configuration diagram showing an example 1 inside the horizontal counter circuit. In FIG. 2, 13 is an adder that increments by one, 14 is a selector with two inputs and one output, 15 is a D-FF that operates with a second clock, and 16 is the carry-out of the adder to one clock width of the second clock. The one-shot circuit 17 is an inverter that inverts and outputs an input signal, and 18 is a two-input one-output OR circuit.
[0017]
Next, an operation example of the scanning line conversion apparatus of the present invention will be described. The input signal is input to the sync separation circuit 2, and the horizontal sync signal (Hsync) and the vertical sync signal (Vsync) are separated and output. The PLL circuit 1 regenerates the first clock based on Hsync. In the PLL circuit 1, the frequency of the first clock is determined by setting a frequency division ratio in the frequency division counter 1. For example, if the frequency division ratio is 800 in the case of the VGA standard, the dot clock on the signal sending side can be reproduced. Similarly, the PLL circuit 2 generates a second clock set by the frequency dividing counter 2. For example, when the output liquid crystal panel is XGA standard, the frequency division ratio of the frequency division counter 2 is set to 1280 which is the same as the XGA standard.
[0018]
The horizontal processing timing generation circuit 6 and the vertical processing timing generation circuit 10 generate interpolation coefficients and timings for conversion from the VGA standard to the XGA standard, and accordingly, the horizontal processing circuit 5, the memory 7, and the vertical processing circuit 11 perform scanning. Perform line number conversion. At this time, in the case of having a plurality of horizontal frequencies of the horizontal synchronizing signal after the scanning line conversion, it is necessary to have counters corresponding to the number of horizontal frequencies. Therefore, the horizontal counter 12 that generates a horizontal synchronizing signal after scanning line conversion is basically composed of one counter composed of an adder, a selector, and a D-FF.
[0019]
This counter starts incrementing from an initial value (frequency division ratio), and when it overflows, starts incrementing from the initial value again. The timing at which this counter overflows is the horizontal synchronization signal after scanning line conversion. Here, the setting of the initial value of the counter and the timing of the horizontal sync signal after the scan line conversion are also performed by Vsync which is the output of the sync separator circuit 2, thereby converting the number of scan lines as shown in FIG. Done.
[0020]
According to such a configuration, generation of a horizontal synchronizing signal after scanning line conversion can be realized by one horizontal counter.
[0021]
(Embodiment 2)
Next, another embodiment of the present invention will be described with reference to FIG. FIG. 3 is an internal configuration diagram showing an example 2 inside the horizontal counter circuit. In addition, about the same structure as embodiment mentioned above, the same code | symbol is used and description is abbreviate | omitted.
[0022]
An operation example of the scanning line conversion apparatus of the present invention will be described. When the horizontal synchronization signal after scanning line conversion has a plurality of horizontal frequencies with one horizontal counter, there is a liquid crystal panel that cannot be displayed if there is a horizontal synchronization signal shorter than the specification of the horizontal synchronization signal of the liquid crystal panel. Therefore, the timing for setting the initial value of the horizontal counter 12 for generating the horizontal synchronizing signal after the scanning line conversion is performed at the time of overflow and the timing of Vsync which is the output of the synchronization separation circuit 2, and the horizontal synchronizing signal to be output is set as the overflow timing. By doing so, the number of scanning lines is converted as shown in FIG.
[0023]
According to this configuration, all the horizontal synchronization signals after the scanning line conversion can be displayed on the liquid crystal panel which must be longer than the specification of the horizontal synchronization signal of the liquid crystal panel.
[0024]
【The invention's effect】
As described above, according to the scanning line conversion apparatus of the first invention, it is possible to generate a horizontal synchronizing signal after the scanning line conversion by one horizontal counter, and the scanning line conversion can be performed on a small circuit scale. Is possible.
[0025]
Further, in the second invention, even when all the horizontal synchronization signals inputted to the liquid crystal panel to be displayed must be longer than the specification of the horizontal synchronization signal of the liquid crystal panel, the display can be performed without any problem.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a scanning line conversion device according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration example of a horizontal counter circuit of the scanning line conversion device. FIG. 4 is a diagram showing another configuration example of the horizontal counter circuit of the device. FIG. 4 is a diagram showing a configuration of a conventional scanning line conversion device. FIG. 5 is a diagram schematically showing a state on the screen of scanning line conversion. Explanation】
1 A / D converter 2 Sync separation circuit 3 PLL circuit 1
4 Dividing counter circuit 1
5 Horizontal processing circuit 6 Horizontal processing timing generation circuit 7 Memory 8 PLL circuit 2
9 Dividing counter circuit 2
DESCRIPTION OF SYMBOLS 10 Vertical processing timing generation circuit 11 Vertical processing circuit 12 Horizontal counter circuit 13 Adder 14 Selector 15 D-FF
16 One-shot circuit 17 Inverter circuit 18 OR circuit 19 Scan line conversion circuit 20 Timing generation circuit

Claims (1)

An A / D converter that converts an input signal into a digital video signal, a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the input signal, and a horizontal synchronization signal that is output from the synchronization separation circuit A first PLL circuit that generates a first clock, a first frequency divider counter that controls the oscillation frequency of the first clock that is the output of the first PLL circuit, and the horizontal synchronization signal. A second PLL circuit for generating a second clock, a second frequency dividing counter for controlling the oscillation frequency of the second clock, which is an output of the second PLL circuit, and the number of dots in the horizontal direction of the input signal A horizontal processing timing generation circuit for generating an interpolation coefficient and an interpolation timing used for an interpolation operation when performing conversion, and an interpolation coefficient and an interpolation timing which are outputs from the horizontal processing timing generation circuit. A horizontal processing circuit that performs interpolation calculation, a memory that writes data after interpolation calculation, which is an output of the horizontal processing circuit, with a first clock, and that reads with a second clock, and a horizontal sync signal after scanning line conversion A vertical processing timing generation circuit that generates an interpolation coefficient and interpolation timing used for interpolation calculation, and a vertical processing circuit that performs an interpolation calculation in the vertical direction from the interpolation coefficient and interpolation timing that are output from the vertical processing timing generation circuit A scanning line conversion device that operates with a second clock that is an output of the second PLL circuit and scans by a frequency dividing counter that resets only an initial value with a vertical synchronization signal that is an output of the synchronization separation circuit. 1. A scanning line conversion apparatus comprising a horizontal counter 2 for generating a horizontal synchronization signal after line conversion by a length of 1H last in one frame.

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