JPS62242988A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a raster scanning type display device C2, particularly when a video signal is sent to a monitor television device (hereinafter, television is abbreviated as TV). This is related to the synchronization method.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional device of this type, in which (1) is an image memo!J, +2 is a TV signal conversion circuit, and (3) is a monitor TV! ! , [4] is the timing generator, (5) is the parallel-to-serial converter, (
6) is a color map table, (7) is a latch, (8)
(9) is a TV interface section, and (9) is a phase adjustment section.

The timing generator (4) generates an address signal indicating the data position to be read out from the image memory (1) and a control clock that controls the time point at which the data should be output, thereby generating the image memory 11) manually. . The bit-parallel data read out from the image memory (11) by this address signal is sent to the parallel-to-serial converter (5) by the first synchronizing signal (
It is set at the time of the synchronization signal (hereinafter abbreviated as synchronous signal 1), is output as a color conversion address of the color map table (6), and the data of the color map table (6) is read out.

The data read from the color map table (6) is latched to the latch (7) by the second synchronization signal (hereinafter abbreviated as synchronization signal 2), and then sent to the TV interface section (
8).

On the other hand, the timing generator (4) outputs a signal from the monitor TV device (
3), a blanking signal is input to the phase adjustment section (9), the phase is adjusted, and then T
V interface section (8).

The TV interface 5 (8) converts the data from the color map table (6) to the video signal level of the monitor TV device (3) and outputs it to the monitor TV device (3). Further, during the blanking period using the blanking signal, the output is performed as a black level (a level not displayed on the monitor TV device (3)).

FIG. 2 is an operation time chart showing the signals of each part of the device shown in FIG.
) is the video signal, (23) is the blanking period, (24)
are video signals 1, (22a), (23a) sent to the monitor.

(24a) is the signal generated due to phase shift (22),
The relative relationship between (23) and (24) is shown in an enlarged manner. During the period of the blanking signal (23), the video signal (22) is not read out, and during that period the video signal (24) sent to the monitor is controlled by the TV interface unit (8) to be at black level. By the way, there is a time delay before the video signal corresponding to the data read out from the image memory (1) by the address signal reaches the TV interface section (8). On the other hand, since the blanking signal (23) is generated by the timing generator (4) in synchronization with the control clock, etc., if it is directly input to the TV interface unit (8:) without passing through the phase adjustment unit (9), Then, the signals (22a), (23a)
, (24a), a relative time difference is generated as shown in the enlarged view of the time axis, and the video signals are synchronized at a position shifted by one dot. 8 for blanking signal (23a)
91! - Since the image signal (22a) is delayed by one dot, one dot's worth of video signal (22a) is erased black at the -start point of the blanking signal (23a), and one dot's worth of video signal (22a) is erased in black at the -start point of the blanking signal (23a). An extra video signal will be displayed. In order to eliminate this shift, a phase vI4a section (9) is provided to give the blanking signal (23) the same time delay as the video signal (22). The phase adjustment section (9) is composed of a slow line or the like.

[Problem that the invention seeks to solve]

As described above, the conventional device requires a phase adjustment section, and the delay amount adjustment in the phase adjustment section requires elaborate adjustment. For example, in a display device whose resolution exceeds 1,000 horizontal dots, the frequency of the video signal exceeds 100 Mt4z.

Therefore, the length of one dot in the TV interface section in terms of time mj is 10 ns or less, and the phase adjustment accuracy in the phase adjustment section (91) needs to be at a fine IM precision that does not cause a shift of one dot.

Also, before the color map table (6) in Figure 3, the blanking signal and +5! : Synchronizing with the image signal is not preferable because, depending on the settings of the color map table, a video signal other than the black level during the blanking period C2 may be input to the monitor TV device 13).

This invention was made to solve the above problems, and aims to provide a display device that can automatically synchronize a blanking signal and a video signal even if the phase adjustment section is removed. The purpose is

[Means for solving problems]

In the display device of the present invention, synchronization between the read video data and the blanking signal is established at the time the data is read from the image memory, and then the video data becomes a video signal and is sent to the TV interface section (2. By making the blanking signal pass through the same circuit that it passed before, the blanking signal and the video signal are automatically connected (
2 synchronization, and in the case of dot synchronization at the TV interface section, a shift of one dot is prevented from occurring.

[Effect]

According to this invention (2), the video 4g signal and the blanking signal are synchronized at the time of generation (2), and both signals pass through the same circuit until they are input to the TV interface section. , there is no difference in the amount of delay between the two signals ζ2.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. 3 indicate the same or corresponding parts, and (10) is the same as the parallel-serial converter (5). A circuit having a circuit configuration similar to that of the color map table 16) will be temporarily referred to as a first synchronization section (abbreviated as synchronization section l), and a circuit having a circuit configuration similar to that of the color map table 16) will be temporarily referred to as a second synchronization section (abbreviated as synchronization section l). (12) is a circuit having a circuit configuration similar to that of latch (7).
It is called a synchronization section (abbreviated as synchronization section 3).

The operation of the VC position shown in FIG. 1 will be explained below. The operation regarding the video signal is similar to the operation in the apparatus shown in FIG. 1
iill 11 When the signal read from the memory (1) is loaded into the parallel-to-serial converter (5), the same synchronizing signal (shown as synchronizing signal l in the drawing) (second blanking signal is also applied to the synchronizing unit 1 (10) In other words, the video signal and the blanking signal are synchronized at the time of generation.Also, in this case, since multiple bits of both signals are loaded at the same time, the TV interface section (8)
Synchronization is easier than synchronization on a dot-by-dot basis.

Immediately after, both signals pass through the same circuit, so they are given the same amount of delay, and when they reach the TV interface section (8), there is no relative delay between the two signals, so T
A one-dot shift does not occur in synchronization at the V interface section (8).

In addition, in FIG. 1, the synchronizer 1 (10) is integrated with the parallel-to-serial converter (5), and the synchronizer 2 (11) is integrated with the parallel-serial converter (5).
is integrated with the color map table (6), and the synchronization section 3 (
12) can also be integrated with the latch (7). For example, empty addresses in the color map table can be used for blanking signals.

Further, the present invention can be generally applied to phase synchronization of two signals having small fundamental frequencies.

〔Effect of the invention〕

As described above, according to invention C2, by passing the two signals, the video signal and the blanking signal, through the same circuit, the time delays due to the passing circuit for the two signals are made the same. This makes it easy to synchronize both signals at the TV interface.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is an operation time chart showing synchronization of a video signal and a blanking signal in a monitor device, and Figure 3 is a block diagram showing a conventional device. 11) is the image memo IJ, +23 is the TV signal conversion circuit, (
3) is a monitor TV device, (4) is a timing generator, (
5) is a parallel-to-serial conversion section, (6) is a color map table, (7) is a latch, (8) is a TV interface section, (10) is a high IkTj period section 1. (11) is synchronous f
a2, (12) is the synchronization part 3°. The same symbol in the valley diagram indicates IeQ- or a corresponding part.

Claims (1)

[Claims] The data stored in the image memory is read out according to the address signal, the read data is converted into a data format by a parallel-serial converter, and is inputted as a color conversion address of a color map table. In a raster scanning display device that temporarily stores data read from a table in a latch and displays the contents of this latch on a monitor television device via a television interface section, an address signal input to the image memory, an address signal input to the above monitor It has a timing generation section that generates a blanking signal to be input to the television device and various synchronization signals, and a parallel-to-serial conversion circuit configuration similar to the above-mentioned parallel-to-serial conversion section. a first synchronization section in which the blanking signal is set by the same synchronization signal that sets data from the parallel-to-serial conversion section, and the blanking signal is read out in synchronization with data reading from the parallel-to-serial conversion section; a second synchronization section having a memory circuit configuration similar to that of the color map table and from which a blanking signal is read out using the output of the first synchronization section as an address; a second synchronization section having a latch circuit configuration similar to the above latch; a third synchronization section in which a blanking signal from the second synchronization section is set by the same synchronization signal that sets the output of the color map table in the latch; A display device comprising: means for reading out a blanking signal from the third synchronizing section in response to a synchronizing signal of and inputting the blanking signal as a blanking signal to the monitor television device via the television interface section.